CSR_SETBIT_1      307 dev/ic/re.c    	CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
CSR_SETBIT_1      312 dev/ic/re.c    		CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
CSR_SETBIT_1      200 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
CSR_SETBIT_1      201 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
CSR_SETBIT_1      207 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD);
CSR_SETBIT_1      329 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD);
CSR_SETBIT_1      368 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD);
CSR_SETBIT_1      397 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
CSR_SETBIT_1      410 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
CSR_SETBIT_1      425 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA);
CSR_SETBIT_1      435 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE);
CSR_SETBIT_1      452 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
CSR_SETBIT_1      455 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8),
CSR_SETBIT_1      464 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
CSR_SETBIT_1      554 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD);
CSR_SETBIT_1     1529 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2);
CSR_SETBIT_1     1533 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128);
CSR_SETBIT_1     1535 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK);
CSR_SETBIT_1     1540 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET);
CSR_SETBIT_1     1543 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS);
CSR_SETBIT_1     1571 dev/pci/if_vge.c 		CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC);
CSR_SETBIT_1     1576 dev/pci/if_vge.c 		CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST);
CSR_SETBIT_1     1581 dev/pci/if_vge.c 		CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST);
CSR_SETBIT_1     1606 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES);
CSR_SETBIT_1     1621 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF);
CSR_SETBIT_1     1630 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR);
CSR_SETBIT_1     1635 dev/pci/if_vge.c 	CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
CSR_SETBIT_1     1711 dev/pci/if_vge.c 		CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
CSR_SETBIT_1     1716 dev/pci/if_vge.c 		CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
CSR_SETBIT_1     1718 dev/pci/if_vge.c 			CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
CSR_SETBIT_1     1771 dev/pci/if_vge.c 				CSR_SETBIT_1(sc, VGE_RXCTL,