root/dev/ic/re.c

DEFINITIONS

1. re_set_bufaddr
2. re_eeprom_putbyte
3. re_eeprom_getword
4. re_read_eeprom
5. re_gmii_readreg
6. re_gmii_writereg
7. re_miibus_readreg
8. re_miibus_writereg
9. re_miibus_statchg
10. re_setmulti
11. re_setpromisc
12. re_reset
13. re_diag
14. re_attach
15. re_newbuf
16. re_tx_list_init
17. re_rx_list_init
18. re_rxeof
19. re_txeof
20. re_tick
21. re_intr
22. re_encap
23. re_start
24. re_init
25. re_ifmedia_upd
26. re_ifmedia_sts
27. re_ioctl
28. re_watchdog
29. re_stop

    1 /*      $OpenBSD: re.c,v 1.74 2007/07/16 19:15:01 millert Exp $ */
    2 /*      $FreeBSD: if_re.c,v 1.31 2004/09/04 07:54:05 ru Exp $   */
    3 /*
    4  * Copyright (c) 1997, 1998-2003
    5  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  */
   35 /*
   36  * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
   37  *
   38  * Written by Bill Paul <wpaul@windriver.com>
   39  * Senior Networking Software Engineer
   40  * Wind River Systems
   41  */
   43 /*
   44  * This driver is designed to support RealTek's next generation of
   45  * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
   46  * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
   47  * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
   48  *
   49  * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
   50  * with the older 8139 family, however it also supports a special
   51  * C+ mode of operation that provides several new performance enhancing
   52  * features. These include:
   53  *
   54  *      o Descriptor based DMA mechanism. Each descriptor represents
   55  *        a single packet fragment. Data buffers may be aligned on
   56  *        any byte boundary.
   57  *
   58  *      o 64-bit DMA
   59  *
   60  *      o TCP/IP checksum offload for both RX and TX
   61  *
   62  *      o High and normal priority transmit DMA rings
   63  *
   64  *      o VLAN tag insertion and extraction
   65  *
   66  *      o TCP large send (segmentation offload)
   67  *
   68  * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
   69  * programming API is fairly straightforward. The RX filtering, EEPROM
   70  * access and PHY access is the same as it is on the older 8139 series
   71  * chips.
   72  *
   73  * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
   74  * same programming API and feature set as the 8139C+ with the following
   75  * differences and additions:
   76  *
   77  *      o 1000Mbps mode
   78  *
   79  *      o Jumbo frames
   80  *
   81  *      o GMII and TBI ports/registers for interfacing with copper
   82  *        or fiber PHYs
   83  *
   84  *      o RX and TX DMA rings can have up to 1024 descriptors
   85  *        (the 8139C+ allows a maximum of 64)
   86  *
   87  *      o Slight differences in register layout from the 8139C+
   88  *
   89  * The TX start and timer interrupt registers are at different locations
   90  * on the 8169 than they are on the 8139C+. Also, the status word in the
   91  * RX descriptor has a slightly different bit layout. The 8169 does not
   92  * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
   93  * copper gigE PHY.
   94  *
   95  * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
   96  * (the 'S' stands for 'single-chip'). These devices have the same
   97  * programming API as the older 8169, but also have some vendor-specific
   98  * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
   99  * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
  100  * 
  101  * This driver takes advantage of the RX and TX checksum offload and
  102  * VLAN tag insertion/extraction features. It also implements TX
  103  * interrupt moderation using the timer interrupt registers, which
  104  * significantly reduces TX interrupt load. There is also support
  105  * for jumbo frames, however the 8169/8169S/8110S can not transmit
  106  * jumbo frames larger than 7440, so the max MTU possible with this
  107  * driver is 7422 bytes.
  108  */
  110 #include "bpfilter.h"
  111 #include "vlan.h"
  113 #include <sys/param.h>
  114 #include <sys/endian.h>
  115 #include <sys/systm.h>
  116 #include <sys/sockio.h>
  117 #include <sys/mbuf.h>
  118 #include <sys/malloc.h>
  119 #include <sys/kernel.h>
  120 #include <sys/device.h>
  121 #include <sys/timeout.h>
  122 #include <sys/socket.h>
  124 #include <net/if.h>
  125 #include <net/if_dl.h>
  126 #include <net/if_media.h>
  128 #ifdef INET
  129 #include <netinet/in.h>
  130 #include <netinet/in_systm.h>
  131 #include <netinet/in_var.h>
  132 #include <netinet/ip.h>
  133 #include <netinet/if_ether.h>
  134 #endif
  136 #if NVLAN > 0
  137 #include <net/if_types.h>
  138 #include <net/if_vlan_var.h>
  139 #endif
  141 #if NBPFILTER > 0
  142 #include <net/bpf.h>
  143 #endif
  145 #include <dev/mii/mii.h>
  146 #include <dev/mii/miivar.h>
  148 #include <dev/pci/pcireg.h>
  149 #include <dev/pci/pcivar.h>
  151 #include <dev/ic/rtl81x9reg.h>
  152 #include <dev/ic/revar.h>
  154 #ifdef RE_DEBUG
  155 int redebug = 0;
  156 #define DPRINTF(x)      do { if (redebug) printf x; } while (0)
  157 #else
  158 #define DPRINTF(x)
  159 #endif
  161 static inline void re_set_bufaddr(struct rl_desc *, bus_addr_t);
  163 int     re_encap(struct rl_softc *, struct mbuf *, int *);
  165 int     re_newbuf(struct rl_softc *, int, struct mbuf *);
  166 int     re_rx_list_init(struct rl_softc *);
  167 int     re_tx_list_init(struct rl_softc *);
  168 void    re_rxeof(struct rl_softc *);
  169 void    re_txeof(struct rl_softc *);
  170 void    re_tick(void *);
  171 void    re_start(struct ifnet *);
  172 int     re_ioctl(struct ifnet *, u_long, caddr_t);
  173 void    re_watchdog(struct ifnet *);
  174 int     re_ifmedia_upd(struct ifnet *);
  175 void    re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  177 void    re_eeprom_putbyte(struct rl_softc *, int);
  178 void    re_eeprom_getword(struct rl_softc *, int, u_int16_t *);
  179 void    re_read_eeprom(struct rl_softc *, caddr_t, int, int);
  181 int     re_gmii_readreg(struct device *, int, int);
  182 void    re_gmii_writereg(struct device *, int, int, int);
  184 int     re_miibus_readreg(struct device *, int, int);
  185 void    re_miibus_writereg(struct device *, int, int, int);
  186 void    re_miibus_statchg(struct device *);
  188 void    re_setmulti(struct rl_softc *);
  189 void    re_setpromisc(struct rl_softc *);
  190 void    re_reset(struct rl_softc *);
  192 #ifdef RE_DIAG
  193 int     re_diag(struct rl_softc *);
  194 #endif
  196 struct cfdriver re_cd = {
  197         0, "re", DV_IFNET
  198 };
  200 #define EE_SET(x)                                       \
CSR_WRITE_1(sc, RL_EECMD,                       \
CSR_READ_1(sc, RL_EECMD) | x)
  204 #define EE_CLR(x)                                       \
CSR_WRITE_1(sc, RL_EECMD,                       \
CSR_READ_1(sc, RL_EECMD) & ~x)
  208 static const struct re_revision {
u_int32_t               re_chipid;
  210         const char              *re_name;
  211 } re_revisions[] = {
  212         { RL_HWREV_8169,        "RTL8169" },
  213         { RL_HWREV_8110S,       "RTL8110S" },
  214         { RL_HWREV_8169S,       "RTL8169S" },
  215         { RL_HWREV_8169_8110SB, "RTL8169/8110SB" },
  216         { RL_HWREV_8169_8110SCd, "RTL8169/8110SCd" },
  217         { RL_HWREV_8168_SPIN1,  "RTL8168 1" },
  218         { RL_HWREV_8100E_SPIN1, "RTL8100E 1" },
  219         { RL_HWREV_8101E,       "RTL8101E" },
  220         { RL_HWREV_8168_SPIN2,  "RTL8168 2" },
  221         { RL_HWREV_8168_SPIN3,  "RTL8168 3" },
  222         { RL_HWREV_8100E_SPIN2, "RTL8100E 2" },
  223         { RL_HWREV_8139CPLUS,   "RTL8139C+" },
  224         { RL_HWREV_8101,        "RTL8101" },
  225         { RL_HWREV_8100,        "RTL8100" },
  226         { RL_HWREV_8169_8110SCe, "RTL8169/8110SCe" },
  228         { 0, NULL }
  229 };
  232 static inline void
re_set_bufaddr(struct rl_desc *d, bus_addr_t addr)
  234 {
d->rl_bufaddr_lo = htole32((uint32_t)addr);
  236         if (sizeof(bus_addr_t) == sizeof(uint64_t))
d->rl_bufaddr_hi = htole32((uint64_t)addr >> 32);
  238         else
d->rl_bufaddr_hi = 0;
  240 }
  242 /*
  243  * Send a read command and address to the EEPROM, check for ACK.
  244  */
  245 void
re_eeprom_putbyte(struct rl_softc *sc, int addr)
  247 {
  248         int     d, i;
d = addr | (RL_9346_READ << sc->rl_eewidth);
  252         /*
  253          * Feed in each bit and strobe the clock.
  254          */
  256         for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
  257                 if (d & i)
EE_SET(RL_EE_DATAIN);
  259                 else
EE_CLR(RL_EE_DATAIN);
DELAY(100);
EE_SET(RL_EE_CLK);
DELAY(150);
EE_CLR(RL_EE_CLK);
DELAY(100);
  266         }
  267 }
  269 /*
  270  * Read a word of data stored in the EEPROM at address 'addr.'
  271  */
  272 void
re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
  274 {
  275         int             i;
u_int16_t       word = 0;
  278         /*
  279          * Send address of word we want to read.
  280          */
re_eeprom_putbyte(sc, addr);
  283         /*
  284          * Start reading bits from EEPROM.
  285          */
  286         for (i = 0x8000; i; i >>= 1) {
EE_SET(RL_EE_CLK);
DELAY(100);
  289                 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
word |= i;
EE_CLR(RL_EE_CLK);
DELAY(100);
  293         }
  295         *dest = word;
  296 }
  298 /*
  299  * Read a sequence of words from the EEPROM.
  300  */
  301 void
re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
  303 {
  304         int             i;
u_int16_t       word = 0, *ptr;
CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
DELAY(100);
  311         for (i = 0; i < cnt; i++) {
CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
re_eeprom_getword(sc, off + i, &word);
CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
ptr = (u_int16_t *)(dest + (i * 2));
  316                 *ptr = word;
  317         }
CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
  320 }
  322 int
re_gmii_readreg(struct device *self, int phy, int reg)
  324 {
  325         struct rl_softc *sc = (struct rl_softc *)self;
u_int32_t       rval;
  327         int             i;
  329         if (phy != 7)
  330                 return (0);
  332         /* Let the rgephy driver read the GMEDIASTAT register */
  334         if (reg == RL_GMEDIASTAT) {
rval = CSR_READ_1(sc, RL_GMEDIASTAT);
  336                 return (rval);
  337         }
CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
DELAY(1000);
  342         for (i = 0; i < RL_TIMEOUT; i++) {
rval = CSR_READ_4(sc, RL_PHYAR);
  344                 if (rval & RL_PHYAR_BUSY)
  345                         break;
DELAY(100);
  347         }
  349         if (i == RL_TIMEOUT) {
printf ("%s: PHY read failed\n", sc->sc_dev.dv_xname);
  351                 return (0);
  352         }
  354         return (rval & RL_PHYAR_PHYDATA);
  355 }
  357 void
re_gmii_writereg(struct device *dev, int phy, int reg, int data)
  359 {
  360         struct rl_softc *sc = (struct rl_softc *)dev;
u_int32_t       rval;
  362         int             i;
CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
  365             (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
DELAY(1000);
  368         for (i = 0; i < RL_TIMEOUT; i++) {
rval = CSR_READ_4(sc, RL_PHYAR);
  370                 if (!(rval & RL_PHYAR_BUSY))
  371                         break;
DELAY(100);
  373         }
  375         if (i == RL_TIMEOUT)
printf ("%s: PHY write failed\n", sc->sc_dev.dv_xname);
  377 }
  379 int
re_miibus_readreg(struct device *dev, int phy, int reg)
  381 {
  382         struct rl_softc *sc = (struct rl_softc *)dev;
u_int16_t       rval = 0;
u_int16_t       re8139_reg = 0;
  385         int             s;
s = splnet();
  389         if (sc->rl_type == RL_8169) {
rval = re_gmii_readreg(dev, phy, reg);
splx(s);
  392                 return (rval);
  393         }
  395         /* Pretend the internal PHY is only at address 0 */
  396         if (phy) {
splx(s);
  398                 return (0);
  399         }
  400         switch(reg) {
  401         case MII_BMCR:
re8139_reg = RL_BMCR;
  403                 break;
  404         case MII_BMSR:
re8139_reg = RL_BMSR;
  406                 break;
  407         case MII_ANAR:
re8139_reg = RL_ANAR;
  409                 break;
  410         case MII_ANER:
re8139_reg = RL_ANER;
  412                 break;
  413         case MII_ANLPAR:
re8139_reg = RL_LPAR;
  415                 break;
  416         case MII_PHYIDR1:
  417         case MII_PHYIDR2:
splx(s);
  419                 return (0);
  420         /*
  421          * Allow the rlphy driver to read the media status
  422          * register. If we have a link partner which does not
  423          * support NWAY, this is the register which will tell
  424          * us the results of parallel detection.
  425          */
  426         case RL_MEDIASTAT:
rval = CSR_READ_1(sc, RL_MEDIASTAT);
splx(s);
  429                 return (rval);
  430         default:
printf("%s: bad phy register %x\n", sc->sc_dev.dv_xname, reg);
splx(s);
  433                 return (0);
  434         }
rval = CSR_READ_2(sc, re8139_reg);
  436         if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
  437                 /* 8139C+ has different bit layout. */
rval &= ~(BMCR_LOOP | BMCR_ISO);
  439         }
splx(s);
  441         return (rval);
  442 }
  444 void
re_miibus_writereg(struct device *dev, int phy, int reg, int data)
  446 {
  447         struct rl_softc *sc = (struct rl_softc *)dev;
u_int16_t       re8139_reg = 0;
  449         int             s;
s = splnet();
  453         if (sc->rl_type == RL_8169) {
re_gmii_writereg(dev, phy, reg, data);
splx(s);
  456                 return;
  457         }
  459         /* Pretend the internal PHY is only at address 0 */
  460         if (phy) {
splx(s);
  462                 return;
  463         }
  464         switch(reg) {
  465         case MII_BMCR:
re8139_reg = RL_BMCR;
  467                 if (sc->rl_type == RL_8139CPLUS) {
  468                         /* 8139C+ has different bit layout. */
data &= ~(BMCR_LOOP | BMCR_ISO);
  470                 }
  471                 break;
  472         case MII_BMSR:
re8139_reg = RL_BMSR;
  474                 break;
  475         case MII_ANAR:
re8139_reg = RL_ANAR;
  477                 break;
  478         case MII_ANER:
re8139_reg = RL_ANER;
  480                 break;
  481         case MII_ANLPAR:
re8139_reg = RL_LPAR;
  483                 break;
  484         case MII_PHYIDR1:
  485         case MII_PHYIDR2:
splx(s);
  487                 return;
  488                 break;
  489         default:
printf("%s: bad phy register %x\n", sc->sc_dev.dv_xname, reg);
splx(s);
  492                 return;
  493         }
CSR_WRITE_2(sc, re8139_reg, data);
splx(s);
  496 }
  498 void
re_miibus_statchg(struct device *dev)
  500 {
  501 }
  503 /*
  504  * Program the 64-bit multicast hash filter.
  505  */
  506 void
re_setmulti(struct rl_softc *sc)
  508 {
  509         struct ifnet            *ifp;
  510         int                     h = 0;
u_int32_t               hashes[2] = { 0, 0 };
u_int32_t               hwrev, rxfilt;
  513         int                     mcnt = 0;
  514         struct arpcom           *ac = &sc->sc_arpcom;
  515         struct ether_multi      *enm;
  516         struct ether_multistep  step;
ifp = &sc->sc_arpcom.ac_if;
rxfilt = CSR_READ_4(sc, RL_RXCFG);
  522         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
rxfilt |= RL_RXCFG_RX_MULTI;
CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
  527                 return;
  528         }
  530         /* first, zot all the existing hash bits */
CSR_WRITE_4(sc, RL_MAR0, 0);
CSR_WRITE_4(sc, RL_MAR4, 0);
  534         /* now program new ones */
ETHER_FIRST_MULTI(step, ac, enm);
  536         while (enm != NULL) {
  537                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
ifp->if_flags |= IFF_ALLMULTI;
mcnt = MAX_NUM_MULTICAST_ADDRESSES;
  540                 }
  541                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
  542                         break;
h = (ether_crc32_be(enm->enm_addrlo,
ETHER_ADDR_LEN) >> 26) & 0x0000003F;
  546                 if (h < 32)
hashes[0] |= (1 << h);
  548                 else
hashes[1] |= (1 << (h - 32));
mcnt++;
ETHER_NEXT_MULTI(step, enm);
  552         }
  554         if (mcnt)
rxfilt |= RL_RXCFG_RX_MULTI;
  556         else
rxfilt &= ~RL_RXCFG_RX_MULTI;
CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
  561         /*
  562          * For some unfathomable reason, RealTek decided to reverse
  563          * the order of the multicast hash registers in the PCI Express
  564          * parts. This means we have to write the hash pattern in reverse
  565          * order for those devices.
  566          */
hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
  568         if (hwrev == RL_HWREV_8100E_SPIN1 || hwrev == RL_HWREV_8100E_SPIN2 ||
hwrev == RL_HWREV_8101E || hwrev == RL_HWREV_8168_SPIN1 ||
hwrev == RL_HWREV_8168_SPIN2) {
CSR_WRITE_4(sc, RL_MAR0, swap32(hashes[1]));
CSR_WRITE_4(sc, RL_MAR4, swap32(hashes[0]));
  573         } else {
CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
  576         }
  577 }
  579 void
re_setpromisc(struct rl_softc *sc)
  581 {
  582         struct ifnet    *ifp;
u_int32_t       rxcfg = 0;
ifp = &sc->sc_arpcom.ac_if;
rxcfg = CSR_READ_4(sc, RL_RXCFG);
  588         if (ifp->if_flags & IFF_PROMISC) 
rxcfg |= RL_RXCFG_RX_ALLPHYS;
  590         else
rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
  593 }
  595 void
re_reset(struct rl_softc *sc)
  597 {
  598         int     i;
CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
  602         for (i = 0; i < RL_TIMEOUT; i++) {
DELAY(10);
  604                 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
  605                         break;
  606         }
  607         if (i == RL_TIMEOUT)
printf("%s: reset never completed!\n", sc->sc_dev.dv_xname);
CSR_WRITE_1(sc, 0x82, 1);
  611 }
  613 #ifdef RE_DIAG
  615 /*
  616  * The following routine is designed to test for a defect on some
  617  * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
  618  * lines connected to the bus, however for a 32-bit only card, they
  619  * should be pulled high. The result of this defect is that the
  620  * NIC will not work right if you plug it into a 64-bit slot: DMA
  621  * operations will be done with 64-bit transfers, which will fail
  622  * because the 64-bit data lines aren't connected.
  623  *
  624  * There's no way to work around this (short of talking a soldering
  625  * iron to the board), however we can detect it. The method we use
  626  * here is to put the NIC into digital loopback mode, set the receiver
  627  * to promiscuous mode, and then try to send a frame. We then compare
  628  * the frame data we sent to what was received. If the data matches,
  629  * then the NIC is working correctly, otherwise we know the user has
  630  * a defective NIC which has been mistakenly plugged into a 64-bit PCI
  631  * slot. In the latter case, there's no way the NIC can work correctly,
  632  * so we print out a message on the console and abort the device attach.
  633  */
  635 int
re_diag(struct rl_softc *sc)
  637 {
  638         struct ifnet            *ifp = &sc->sc_arpcom.ac_if;
  639         struct mbuf             *m0;
  640         struct ether_header     *eh;
  641         struct rl_rxsoft        *rxs;
  642         struct rl_desc          *cur_rx;
bus_dmamap_t            dmamap;
u_int16_t               status;
u_int32_t               rxstat;
  646         int                     total_len, i, s, error = 0, phyaddr;
u_int8_t                dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
u_int8_t                src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
DPRINTF(("inside re_diag\n"));
  651         /* Allocate a single mbuf */
MGETHDR(m0, M_DONTWAIT, MT_DATA);
  654         if (m0 == NULL)
  655                 return (ENOBUFS);
  657         /*
  658          * Initialize the NIC in test mode. This sets the chip up
  659          * so that it can send and receive frames, but performs the
  660          * following special functions:
  661          * - Puts receiver in promiscuous mode
  662          * - Enables digital loopback mode
  663          * - Leaves interrupts turned off
  664          */
ifp->if_flags |= IFF_PROMISC;
sc->rl_testmode = 1;
re_reset(sc);
re_init(ifp);
sc->rl_link = 1;
  671         if (sc->rl_type == RL_8169)
phyaddr = 1;
  673         else
phyaddr = 0;
re_miibus_writereg((struct device *)sc, phyaddr, MII_BMCR,
BMCR_RESET);
  678         for (i = 0; i < RL_TIMEOUT; i++) {
status = re_miibus_readreg((struct device *)sc,
phyaddr, MII_BMCR);
  681                 if (!(status & BMCR_RESET))
  682                         break;
  683         }
re_miibus_writereg((struct device *)sc, phyaddr, MII_BMCR,
BMCR_LOOP);
CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
DELAY(100000);
  691         /* Put some data in the mbuf */
eh = mtod(m0, struct ether_header *);
bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
eh->ether_type = htons(ETHERTYPE_IP);
m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
  699         /*
  700          * Queue the packet, start transmission.
  701          */
CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
s = splnet();
IFQ_ENQUEUE(&ifp->if_snd, m0, NULL, error);
re_start(ifp);
splx(s);
m0 = NULL;
DPRINTF(("re_diag: transmission started\n"));
  712         /* Wait for it to propagate through the chip */
DELAY(100000);
  715         for (i = 0; i < RL_TIMEOUT; i++) {
status = CSR_READ_2(sc, RL_ISR);
CSR_WRITE_2(sc, RL_ISR, status);
  718                 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
  719                     (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
  720                         break;
DELAY(10);
  722         }
  723         if (i == RL_TIMEOUT) {
printf("%s: diagnostic failed, failed to receive packet "
  725                     "in loopback mode\n", sc->sc_dev.dv_xname);
error = EIO;
  727                 goto done;
  728         }
  730         /*
  731          * The packet should have been dumped into the first
  732          * entry in the RX DMA ring. Grab it from there.
  733          */
rxs = &sc->rl_ldata.rl_rxsoft[0];
dmamap = rxs->rxs_dmamap;
bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->sc_dmat, dmamap);
m0 = rxs->rxs_mbuf;
rxs->rxs_mbuf = NULL;
eh = mtod(m0, struct ether_header *);
RL_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
cur_rx = &sc->rl_ldata.rl_rx_list[0];
rxstat = letoh32(cur_rx->rl_cmdstat);
total_len = rxstat & sc->rl_rxlenmask;
  750         if (total_len != ETHER_MIN_LEN) {
printf("%s: diagnostic failed, received short packet\n",
sc->sc_dev.dv_xname);
error = EIO;
  754                 goto done;
  755         }
DPRINTF(("re_diag: packet received\n"));
  759         /* Test that the received packet data matches what we sent. */
  761         if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
ntohs(eh->ether_type) != ETHERTYPE_IP) {
printf("%s: WARNING, DMA FAILURE!\n", sc->sc_dev.dv_xname);
printf("%s: expected TX data: %s",
sc->sc_dev.dv_xname, ether_sprintf(dst));
printf("/%s/0x%x\n", ether_sprintf(src), ETHERTYPE_IP);
printf("%s: received RX data: %s",
sc->sc_dev.dv_xname,
ether_sprintf(eh->ether_dhost));
printf("/%s/0x%x\n", ether_sprintf(eh->ether_shost),
ntohs(eh->ether_type));
printf("%s: You may have a defective 32-bit NIC plugged "
  774                     "into a 64-bit PCI slot.\n", sc->sc_dev.dv_xname);
printf("%s: Please re-install the NIC in a 32-bit slot "
  776                     "for proper operation.\n", sc->sc_dev.dv_xname);
printf("%s: Read the re(4) man page for more details.\n",
sc->sc_dev.dv_xname);
error = EIO;
  780         }
done:
  783         /* Turn interface off, release resources */
sc->rl_testmode = 0;
sc->rl_link = 0;
ifp->if_flags &= ~IFF_PROMISC;
re_stop(ifp, 1);
  789         if (m0 != NULL)
m_freem(m0);
DPRINTF(("leaving re_diag\n"));
  793         return (error);
  794 }
  796 #endif
  798 #ifdef __armish__ 
  799 /*
  800  * Thecus N2100 doesn't store the full mac address in eeprom
  801  * so we read the old mac address from the device before the reset
  802  * in hopes that the proper mac address is already there.
  803  */
  804 union {
u_int32_t eaddr_word[2];
u_char eaddr[ETHER_ADDR_LEN];
  807 } boot_eaddr;
  808 int boot_eaddr_valid;
  809 #endif /* __armish__ */
  810 /*
  811  * Attach the interface. Allocate softc structures, do ifmedia
  812  * setup and ethernet/BPF attach.
  813  */
  814 int
re_attach(struct rl_softc *sc, const char *intrstr)
  816 {
u_char          eaddr[ETHER_ADDR_LEN];
u_int16_t       as[ETHER_ADDR_LEN / 2];
  819         struct ifnet    *ifp;
u_int16_t       re_did = 0;
  821         int             error = 0, i;
u_int32_t       hwrev;
  823         const struct re_revision *rr;
  824         const char      *re_name = NULL;
  826         /* Reset the adapter. */
re_reset(sc);
sc->rl_eewidth = RL_9356_ADDR_LEN;
re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
  831         if (re_did != 0x8129)
sc->rl_eewidth = RL_9346_ADDR_LEN;
  834         /*
  835          * Get station address from the EEPROM.
  836          */
re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
  838         for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
as[i] = letoh16(as[i]);
bcopy(as, eaddr, sizeof(eaddr));
  841 #ifdef __armish__
  842         /*
  843          * On the Thecus N2100, the MAC address in the EEPROM is
  844          * always 00:14:fd:10:00:00.  The proper MAC address is stored
  845          * in flash.  Fortunately RedBoot configures the proper MAC
  846          * address (for the first onboard interface) which we can read
  847          * from the IDR.
  848          */
  849         if (eaddr[0] == 0x00 && eaddr[1] == 0x14 && eaddr[2] == 0xfd &&
eaddr[3] == 0x10 && eaddr[4] == 0x00 && eaddr[5] == 0x00) {
  851                 if (boot_eaddr_valid == 0) {
boot_eaddr.eaddr_word[1] = letoh32(CSR_READ_4(sc, RL_IDR4));
boot_eaddr.eaddr_word[0] = letoh32(CSR_READ_4(sc, RL_IDR0));
boot_eaddr_valid = 1;
  855                 }
bcopy(boot_eaddr.eaddr, eaddr, sizeof(eaddr));
eaddr[5] += sc->sc_dev.dv_unit;
  859         }
  860 #endif
  862         /*
  863          * Set RX length mask, TX poll request register
  864          * and TX descriptor count.
  865          */
  866         if (sc->rl_type == RL_8169) {
sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
sc->rl_txstart = RL_GTXSTART;
sc->rl_ldata.rl_tx_desc_cnt = RL_TX_DESC_CNT_8169;
  870         } else {
sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
sc->rl_txstart = RL_TXSTART;
sc->rl_ldata.rl_tx_desc_cnt = RL_TX_DESC_CNT_8139;
  874         }
bcopy(eaddr, (char *)&sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
  879         for (rr = re_revisions; rr->re_name != NULL; rr++) {
  880                 if (rr->re_chipid == hwrev)
re_name = rr->re_name;
  882         }
  884         if (re_name == NULL)
printf(": unknown ASIC (0x%04x)", hwrev >> 16);
  886         else
printf(": %s (0x%04x)", re_name, hwrev >> 16);
printf(", %s, address %s\n", intrstr,
ether_sprintf(sc->sc_arpcom.ac_enaddr));
  892         if (sc->rl_ldata.rl_tx_desc_cnt >
PAGE_SIZE / sizeof(struct rl_desc)) {
sc->rl_ldata.rl_tx_desc_cnt =
PAGE_SIZE / sizeof(struct rl_desc);
  896         }
  898         /* Allocate DMA'able memory for the TX ring */
  899         if ((error = bus_dmamem_alloc(sc->sc_dmat, RL_TX_LIST_SZ(sc),
RL_RING_ALIGN, 0, &sc->rl_ldata.rl_tx_listseg, 1,
  901                     &sc->rl_ldata.rl_tx_listnseg, BUS_DMA_NOWAIT)) != 0) {
printf("%s: can't allocate tx listseg, error = %d\n",
sc->sc_dev.dv_xname, error);
  904                 goto fail_0;
  905         }
  907         /* Load the map for the TX ring. */
  908         if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rl_ldata.rl_tx_listseg,
sc->rl_ldata.rl_tx_listnseg, RL_TX_LIST_SZ(sc),
  910                     (caddr_t *)&sc->rl_ldata.rl_tx_list,
BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) {
printf("%s: can't map tx list, error = %d\n",
sc->sc_dev.dv_xname, error);
  914                 goto fail_1;
  915         }
memset(sc->rl_ldata.rl_tx_list, 0, RL_TX_LIST_SZ(sc));
  918         if ((error = bus_dmamap_create(sc->sc_dmat, RL_TX_LIST_SZ(sc), 1,
RL_TX_LIST_SZ(sc), 0, 0,
  920                     &sc->rl_ldata.rl_tx_list_map)) != 0) {
printf("%s: can't create tx list map, error = %d\n",
sc->sc_dev.dv_xname, error);
  923                 goto fail_2;
  924         }
  926         if ((error = bus_dmamap_load(sc->sc_dmat,
sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
RL_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) {
printf("%s: can't load tx list, error = %d\n",
sc->sc_dev.dv_xname, error);
  931                 goto fail_3;
  932         }
  934         /* Create DMA maps for TX buffers */
  935         for (i = 0; i < RL_TX_QLEN; i++) {
error = bus_dmamap_create(sc->sc_dmat,
RL_JUMBO_FRAMELEN,
RL_TX_DESC_CNT(sc) - RL_NTXDESC_RSVD, RL_TDESC_CMD_FRAGLEN,
  939                     0, 0, &sc->rl_ldata.rl_txq[i].txq_dmamap);
  940                 if (error) {
printf("%s: can't create DMA map for TX\n",
sc->sc_dev.dv_xname);
  943                         goto fail_4;
  944                 }
  945         }
  947         /* Allocate DMA'able memory for the RX ring */
  948         if ((error = bus_dmamem_alloc(sc->sc_dmat, RL_RX_DMAMEM_SZ,
RL_RING_ALIGN, 0, &sc->rl_ldata.rl_rx_listseg, 1,
  950                     &sc->rl_ldata.rl_rx_listnseg, BUS_DMA_NOWAIT)) != 0) {
printf("%s: can't allocate rx listnseg, error = %d\n",
sc->sc_dev.dv_xname, error);
  953                 goto fail_4;
  954         }
  956         /* Load the map for the RX ring. */
  957         if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rl_ldata.rl_rx_listseg,
sc->rl_ldata.rl_rx_listnseg, RL_RX_DMAMEM_SZ,
  959                     (caddr_t *)&sc->rl_ldata.rl_rx_list,
BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) {
printf("%s: can't map rx list, error = %d\n",
sc->sc_dev.dv_xname, error);
  963                 goto fail_5;
  965         }
memset(sc->rl_ldata.rl_rx_list, 0, RL_RX_DMAMEM_SZ);
  968         if ((error = bus_dmamap_create(sc->sc_dmat, RL_RX_DMAMEM_SZ, 1,
RL_RX_DMAMEM_SZ, 0, 0,
  970                     &sc->rl_ldata.rl_rx_list_map)) != 0) {
printf("%s: can't create rx list map, error = %d\n",
sc->sc_dev.dv_xname, error);
  973                 goto fail_6;
  974         }
  976         if ((error = bus_dmamap_load(sc->sc_dmat,
sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
RL_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) {
printf("%s: can't load rx list, error = %d\n",
sc->sc_dev.dv_xname, error);
  981                 goto fail_7;
  982         }
  984         /* Create DMA maps for RX buffers */
  985         for (i = 0; i < RL_RX_DESC_CNT; i++) {
error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
  987                     0, 0, &sc->rl_ldata.rl_rxsoft[i].rxs_dmamap);
  988                 if (error) {
printf("%s: can't create DMA map for RX\n",
sc->sc_dev.dv_xname);
  991                         goto fail_8;
  992                 }
  993         }
ifp = &sc->sc_arpcom.ac_if;
ifp->if_softc = sc;
strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = re_ioctl;
ifp->if_start = re_start;
ifp->if_watchdog = re_watchdog;
ifp->if_init = re_init;
 1003         if (sc->rl_type == RL_8169)
ifp->if_hardmtu = RL_JUMBO_MTU;
IFQ_SET_MAXLEN(&ifp->if_snd, RL_TX_QLEN);
IFQ_SET_READY(&ifp->if_snd);
ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 |
IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
 1011 #if NVLAN > 0
ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
 1013 #endif
timeout_set(&sc->timer_handle, re_tick, sc);
 1017         /* Do MII setup */
sc->sc_mii.mii_ifp = ifp;
sc->sc_mii.mii_readreg = re_miibus_readreg;
sc->sc_mii.mii_writereg = re_miibus_writereg;
sc->sc_mii.mii_statchg = re_miibus_statchg;
ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, re_ifmedia_upd,
re_ifmedia_sts);
mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, MIIF_DOPAUSE);
 1026         if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
printf("%s: no PHY found!\n", sc->sc_dev.dv_xname);
ifmedia_add(&sc->sc_mii.mii_media,
IFM_ETHER|IFM_NONE, 0, NULL);
ifmedia_set(&sc->sc_mii.mii_media,
IFM_ETHER|IFM_NONE);
 1032         } else
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
 1035         /*
 1036          * Call MI attach routine.
 1037          */
re_reset(sc);
if_attach(ifp);
ether_ifattach(ifp);
 1042 #ifdef RE_DIAG
 1043         /*
 1044          * Perform hardware diagnostic on the original RTL8169.
 1045          * Some 32-bit cards were incorrectly wired and would
 1046          * malfunction if plugged into a 64-bit slot.
 1047          */
 1048         if (sc->rl_type == RL_8169) {
error = re_diag(sc);
 1050                 if (error) {
printf("%s: attach aborted due to hardware diag failure\n",
sc->sc_dev.dv_xname);
ether_ifdetach(ifp);
 1054                         goto fail_8;
 1055                 }
 1056         }
 1057 #endif
 1059         return (0);
fail_8:
 1062         /* Destroy DMA maps for RX buffers. */
 1063         for (i = 0; i < RL_RX_DESC_CNT; i++) {
 1064                 if (sc->rl_ldata.rl_rxsoft[i].rxs_dmamap != NULL)
bus_dmamap_destroy(sc->sc_dmat,
sc->rl_ldata.rl_rxsoft[i].rxs_dmamap);
 1067         }
 1069         /* Free DMA'able memory for the RX ring. */
bus_dmamap_unload(sc->sc_dmat, sc->rl_ldata.rl_rx_list_map);
fail_7:
bus_dmamap_destroy(sc->sc_dmat, sc->rl_ldata.rl_rx_list_map);
fail_6:
bus_dmamem_unmap(sc->sc_dmat,
 1075             (caddr_t)sc->rl_ldata.rl_rx_list, RL_RX_DMAMEM_SZ);
fail_5:
bus_dmamem_free(sc->sc_dmat,
 1078             &sc->rl_ldata.rl_rx_listseg, sc->rl_ldata.rl_rx_listnseg);
fail_4:
 1081         /* Destroy DMA maps for TX buffers. */
 1082         for (i = 0; i < RL_TX_QLEN; i++) {
 1083                 if (sc->rl_ldata.rl_txq[i].txq_dmamap != NULL)
bus_dmamap_destroy(sc->sc_dmat,
sc->rl_ldata.rl_txq[i].txq_dmamap);
 1086         }
 1088         /* Free DMA'able memory for the TX ring. */
bus_dmamap_unload(sc->sc_dmat, sc->rl_ldata.rl_tx_list_map);
fail_3:
bus_dmamap_destroy(sc->sc_dmat, sc->rl_ldata.rl_tx_list_map);
fail_2:
bus_dmamem_unmap(sc->sc_dmat,
 1094             (caddr_t)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ(sc));
fail_1:
bus_dmamem_free(sc->sc_dmat,
 1097             &sc->rl_ldata.rl_tx_listseg, sc->rl_ldata.rl_tx_listnseg);
fail_0:
 1099         return (1);
 1100 }
 1103 int
re_newbuf(struct rl_softc *sc, int idx, struct mbuf *m)
 1105 {
 1106         struct mbuf     *n = NULL;
bus_dmamap_t    map;
 1108         struct rl_desc  *d;
 1109         struct rl_rxsoft *rxs;
u_int32_t       cmdstat;
 1111         int             error;
 1113         if (m == NULL) {
MGETHDR(n, M_DONTWAIT, MT_DATA);
 1115                 if (n == NULL)
 1116                         return (ENOBUFS);
MCLGET(n, M_DONTWAIT);
 1119                 if (!(n->m_flags & M_EXT)) {
m_freem(n);
 1121                         return (ENOBUFS);
 1122                 }
m = n;
 1124         } else
m->m_data = m->m_ext.ext_buf;
 1127         /*
 1128          * Initialize mbuf length fields and fixup
 1129          * alignment so that the frame payload is
 1130          * longword aligned on strict alignment archs.
 1131          */
m->m_len = m->m_pkthdr.len = RE_RX_DESC_BUFLEN;
m->m_data += RE_ETHER_ALIGN;
rxs = &sc->rl_ldata.rl_rxsoft[idx];
map = rxs->rxs_dmamap;
error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
BUS_DMA_READ|BUS_DMA_NOWAIT);
 1140         if (error)
 1141                 goto out;
bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
BUS_DMASYNC_PREREAD);
d = &sc->rl_ldata.rl_rx_list[idx];
RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
cmdstat = letoh32(d->rl_cmdstat);
RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
 1150         if (cmdstat & RL_RDESC_STAT_OWN) {
printf("%s: tried to map busy RX descriptor\n",
sc->sc_dev.dv_xname);
 1153                 goto out;
 1154         }
rxs->rxs_mbuf = m;
d->rl_vlanctl = 0;
cmdstat = map->dm_segs[0].ds_len;
 1160         if (idx == (RL_RX_DESC_CNT - 1))
cmdstat |= RL_RDESC_CMD_EOR;
re_set_bufaddr(d, map->dm_segs[0].ds_addr);
d->rl_cmdstat = htole32(cmdstat);
RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
cmdstat |= RL_RDESC_CMD_OWN;
d->rl_cmdstat = htole32(cmdstat);
RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 1169         return (0);
out:
 1171         if (n != NULL)
m_freem(n);
 1173         return (ENOMEM);
 1174 }
 1177 int
re_tx_list_init(struct rl_softc *sc)
 1179 {
 1180         int i;
memset(sc->rl_ldata.rl_tx_list, 0, RL_TX_LIST_SZ(sc));
 1183         for (i = 0; i < RL_TX_QLEN; i++) {
sc->rl_ldata.rl_txq[i].txq_mbuf = NULL;
 1185         }
bus_dmamap_sync(sc->sc_dmat,
sc->rl_ldata.rl_tx_list_map, 0,
sc->rl_ldata.rl_tx_list_map->dm_mapsize,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
sc->rl_ldata.rl_txq_prodidx = 0;
sc->rl_ldata.rl_txq_considx = 0;
sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT(sc);
sc->rl_ldata.rl_tx_nextfree = 0;
 1196         return (0);
 1197 }
 1199 int
re_rx_list_init(struct rl_softc *sc)
 1201 {
 1202         int     i;
memset((char *)sc->rl_ldata.rl_rx_list, 0, RL_RX_LIST_SZ);
 1206         for (i = 0; i < RL_RX_DESC_CNT; i++) {
 1207                 if (re_newbuf(sc, i, NULL) == ENOBUFS)
 1208                         return (ENOBUFS);
 1209         }
sc->rl_ldata.rl_rx_prodidx = 0;
sc->rl_head = sc->rl_tail = NULL;
 1214         return (0);
 1215 }
 1217 /*
 1218  * RX handler for C+ and 8169. For the gigE chips, we support
 1219  * the reception of jumbo frames that have been fragmented
 1220  * across multiple 2K mbuf cluster buffers.
 1221  */
 1222 void
re_rxeof(struct rl_softc *sc)
 1224 {
 1225         struct mbuf     *m;
 1226         struct ifnet    *ifp;
 1227         int             i, total_len;
 1228         struct rl_desc  *cur_rx;
 1229         struct rl_rxsoft *rxs;
u_int32_t       rxstat;
ifp = &sc->sc_arpcom.ac_if;
 1234         for (i = sc->rl_ldata.rl_rx_prodidx;; i = RL_NEXT_RX_DESC(sc, i)) {
cur_rx = &sc->rl_ldata.rl_rx_list[i];
RL_RXDESCSYNC(sc, i,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
rxstat = letoh32(cur_rx->rl_cmdstat);
RL_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD);
 1240                 if ((rxstat & RL_RDESC_STAT_OWN) != 0)
 1241                         break;
total_len = rxstat & sc->rl_rxlenmask;
rxs = &sc->rl_ldata.rl_rxsoft[i];
m = rxs->rxs_mbuf;
 1246                 /* Invalidate the RX mbuf and unload its map */
bus_dmamap_sync(sc->sc_dmat,
rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize,
BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
 1253                 if (!(rxstat & RL_RDESC_STAT_EOF)) {
m->m_len = RE_RX_DESC_BUFLEN;
 1255                         if (sc->rl_head == NULL)
sc->rl_head = sc->rl_tail = m;
 1257                         else {
m->m_flags &= ~M_PKTHDR;
sc->rl_tail->m_next = m;
sc->rl_tail = m;
 1261                         }
re_newbuf(sc, i, NULL);
 1263                         continue;
 1264                 }
 1266                 /*
 1267                  * NOTE: for the 8139C+, the frame length field
 1268                  * is always 12 bits in size, but for the gigE chips,
 1269                  * it is 13 bits (since the max RX frame length is 16K).
 1270                  * Unfortunately, all 32 bits in the status word
 1271                  * were already used, so to make room for the extra
 1272                  * length bit, RealTek took out the 'frame alignment
 1273                  * error' bit and shifted the other status bits
 1274                  * over one slot. The OWN, EOR, FS and LS bits are
 1275                  * still in the same places. We have already extracted
 1276                  * the frame length and checked the OWN bit, so rather
 1277                  * than using an alternate bit mapping, we shift the
 1278                  * status bits one space to the right so we can evaluate
 1279                  * them using the 8169 status as though it was in the
 1280                  * same format as that of the 8139C+.
 1281                  */
 1282                 if (sc->rl_type == RL_8169)
rxstat >>= 1;
 1285                 /*
 1286                  * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
 1287                  * set, but if CRC is clear, it will still be a valid frame.
 1288                  */
 1289                 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 &&
 1290                     (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) {
ifp->if_ierrors++;
 1292                         /*
 1293                          * If this is part of a multi-fragment packet,
 1294                          * discard all the pieces.
 1295                          */
 1296                         if (sc->rl_head != NULL) {
m_freem(sc->rl_head);
sc->rl_head = sc->rl_tail = NULL;
 1299                         }
re_newbuf(sc, i, m);
 1301                         continue;
 1302                 }
 1304                 /*
 1305                  * If allocating a replacement mbuf fails,
 1306                  * reload the current one.
 1307                  */
 1309                 if (re_newbuf(sc, i, NULL)) {
ifp->if_ierrors++;
 1311                         if (sc->rl_head != NULL) {
m_freem(sc->rl_head);
sc->rl_head = sc->rl_tail = NULL;
 1314                         }
re_newbuf(sc, i, m);
 1316                         continue;
 1317                 }
 1319                 if (sc->rl_head != NULL) {
m->m_len = total_len % RE_RX_DESC_BUFLEN;
 1321                         if (m->m_len == 0)
m->m_len = RE_RX_DESC_BUFLEN;
 1323                         /* 
 1324                          * Special case: if there's 4 bytes or less
 1325                          * in this buffer, the mbuf can be discarded:
 1326                          * the last 4 bytes is the CRC, which we don't
 1327                          * care about anyway.
 1328                          */
 1329                         if (m->m_len <= ETHER_CRC_LEN) {
sc->rl_tail->m_len -=
 1331                                     (ETHER_CRC_LEN - m->m_len);
m_freem(m);
 1333                         } else {
m->m_len -= ETHER_CRC_LEN;
m->m_flags &= ~M_PKTHDR;
sc->rl_tail->m_next = m;
 1337                         }
m = sc->rl_head;
sc->rl_head = sc->rl_tail = NULL;
m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
 1341                 } else
m->m_pkthdr.len = m->m_len =
 1343                             (total_len - ETHER_CRC_LEN);
ifp->if_ipackets++;
m->m_pkthdr.rcvif = ifp;
 1348                 /* Do RX checksumming */
 1350                 /* Check IP header checksum */
 1351                 if ((rxstat & RL_RDESC_STAT_PROTOID) &&
 1352                     !(rxstat & RL_RDESC_STAT_IPSUMBAD))
m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK;
 1355                 /* Check TCP/UDP checksum */
 1356                 if ((RL_TCPPKT(rxstat) &&
 1357                     !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
 1358                     (RL_UDPPKT(rxstat) &&
 1359                     !(rxstat & RL_RDESC_STAT_UDPSUMBAD)))
m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK;
 1362 #if NBPFILTER > 0
 1363                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
 1365 #endif
ether_input_mbuf(ifp, m);
 1367         }
sc->rl_ldata.rl_rx_prodidx = i;
 1370 }
 1372 void
re_txeof(struct rl_softc *sc)
 1374 {
 1375         struct ifnet    *ifp;
 1376         struct rl_txq   *txq;
uint32_t        txstat;
 1378         int             idx, descidx;
ifp = &sc->sc_arpcom.ac_if;
 1382         for (idx = sc->rl_ldata.rl_txq_considx;; idx = RL_NEXT_TXQ(sc, idx)) {
txq = &sc->rl_ldata.rl_txq[idx];
 1385                 if (txq->txq_mbuf == NULL) {
KASSERT(idx == sc->rl_ldata.rl_txq_prodidx);
 1387                         break;
 1388                 }
descidx = txq->txq_descidx;
RL_TXDESCSYNC(sc, descidx,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
txstat =
letoh32(sc->rl_ldata.rl_tx_list[descidx].rl_cmdstat);
RL_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD);
KASSERT((txstat & RL_TDESC_CMD_EOF) != 0);
 1397                 if (txstat & RL_TDESC_CMD_OWN)
 1398                         break;
sc->rl_ldata.rl_tx_free += txq->txq_nsegs;
KASSERT(sc->rl_ldata.rl_tx_free <= RL_TX_DESC_CNT(sc));
bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap,
 1403                     0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap);
m_freem(txq->txq_mbuf);
txq->txq_mbuf = NULL;
 1408                 if (txstat & (RL_TDESC_STAT_EXCESSCOL | RL_TDESC_STAT_COLCNT))
ifp->if_collisions++;
 1410                 if (txstat & RL_TDESC_STAT_TXERRSUM)
ifp->if_oerrors++;
 1412                 else
ifp->if_opackets++;
 1414         }
sc->rl_ldata.rl_txq_considx = idx;
 1418         if (sc->rl_ldata.rl_tx_free > RL_NTXDESC_RSVD)
ifp->if_flags &= ~IFF_OACTIVE;
 1421         if (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT(sc)) {
 1422                 /*
 1423                  * Some chips will ignore a second TX request issued while an
 1424                  * existing transmission is in progress. If the transmitter goes
 1425                  * idle but there are still packets waiting to be sent, we need
 1426                  * to restart the channel here to flush them out. This only
 1427                  * seems to be required with the PCIe devices.
 1428                  */
CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
 1431                 /*
 1432                  * If not all descriptors have been released reaped yet,
 1433                  * reload the timer so that we will eventually get another
 1434                  * interrupt that will cause us to re-enter this routine.
 1435                  * This is done in case the transmitter has gone idle.
 1436                  */
CSR_WRITE_4(sc, RL_TIMERCNT, 1);
 1438         } else
ifp->if_timer = 0;
 1440 }
 1442 void
re_tick(void *xsc)
 1444 {
 1445         struct rl_softc *sc = xsc;
 1446         struct mii_data *mii;
 1447         struct ifnet    *ifp;
 1448         int s;
ifp = &sc->sc_arpcom.ac_if;
mii = &sc->sc_mii;
s = splnet();
mii_tick(mii);
 1456         if (sc->rl_link) {
 1457                 if (!(mii->mii_media_status & IFM_ACTIVE))
sc->rl_link = 0;
 1459         } else {
 1460                 if (mii->mii_media_status & IFM_ACTIVE &&
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
sc->rl_link = 1;
 1463                         if (!IFQ_IS_EMPTY(&ifp->if_snd))
re_start(ifp);
 1465                 }
 1466         }
splx(s);
timeout_add(&sc->timer_handle, hz);
 1470 }
 1472 int
re_intr(void *arg)
 1474 {
 1475         struct rl_softc *sc = arg;
 1476         struct ifnet    *ifp;
u_int16_t       status;
 1478         int             claimed = 0;
ifp = &sc->sc_arpcom.ac_if;
 1482         if (!(ifp->if_flags & IFF_UP))
 1483                 return (0);
 1485         for (;;) {
status = CSR_READ_2(sc, RL_ISR);
 1488                 /* If the card has gone away the read returns 0xffff. */
 1489                 if (status == 0xffff)
 1490                         break;
 1491                 if (status)
CSR_WRITE_2(sc, RL_ISR, status);
 1494                 if ((status & RL_INTRS_CPLUS) == 0)
 1495                         break;
 1497                 if (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR)) {
re_rxeof(sc);
claimed = 1;
 1500                 }
 1502                 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_TX_ERR |
RL_ISR_TX_DESC_UNAVAIL)) {
re_txeof(sc);
claimed = 1;
 1506                 }
 1508                 if (status & RL_ISR_SYSTEM_ERR) {
re_reset(sc);
re_init(ifp);
claimed = 1;
 1512                 }
 1514                 if (status & RL_ISR_LINKCHG) {
timeout_del(&sc->timer_handle);
re_tick(sc);
claimed = 1;
 1518                 }
 1519         }
 1521         if (claimed && !IFQ_IS_EMPTY(&ifp->if_snd))
re_start(ifp);
 1524         return (claimed);
 1525 }
 1527 int
re_encap(struct rl_softc *sc, struct mbuf *m, int *idx)
 1529 {
bus_dmamap_t    map;
 1531         int             error, seg, nsegs, uidx, startidx, curidx, lastidx, pad;
 1532         struct rl_desc  *d;
u_int32_t       cmdstat, rl_flags = 0;
 1534         struct rl_txq   *txq;
 1535 #if NVLAN > 0
 1536         struct ifvlan   *ifv = NULL;
 1538         if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
m->m_pkthdr.rcvif != NULL)
ifv = m->m_pkthdr.rcvif->if_softc;
 1541 #endif
 1543         if (sc->rl_ldata.rl_tx_free <= RL_NTXDESC_RSVD)
 1544                 return (EFBIG);
 1546         /*
 1547          * Set up checksum offload. Note: checksum offload bits must
 1548          * appear in all descriptors of a multi-descriptor transmit
 1549          * attempt. This is according to testing done with an 8169
 1550          * chip. This is a requirement.
 1551          */
 1553         /*
 1554          * Set RL_TDESC_CMD_IPCSUM if any checksum offloading
 1555          * is requested.  Otherwise, RL_TDESC_CMD_TCPCSUM/
 1556          * RL_TDESC_CMD_UDPCSUM does not take affect.
 1557          */
 1559         if ((m->m_pkthdr.csum_flags &
 1560             (M_IPV4_CSUM_OUT|M_TCPV4_CSUM_OUT|M_UDPV4_CSUM_OUT)) != 0) {
rl_flags |= RL_TDESC_CMD_IPCSUM;
 1562                 if (m->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT)
rl_flags |= RL_TDESC_CMD_TCPCSUM;
 1564                 if (m->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT)
rl_flags |= RL_TDESC_CMD_UDPCSUM;
 1566         }
txq = &sc->rl_ldata.rl_txq[*idx];
map = txq->txq_dmamap;
error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
BUS_DMA_WRITE|BUS_DMA_NOWAIT);
 1572         if (error) {
 1573                 /* XXX try to defrag if EFBIG? */
printf("%s: can't map mbuf (error %d)\n",
sc->sc_dev.dv_xname, error);
 1576                 return (error);
 1577         }
nsegs = map->dm_nsegs;
pad = 0;
 1581         if (m->m_pkthdr.len <= RL_IP4CSUMTX_PADLEN &&
 1582             (rl_flags & RL_TDESC_CMD_IPCSUM) != 0) {
pad = 1;
nsegs++;
 1585         }
 1587         if (nsegs > sc->rl_ldata.rl_tx_free - RL_NTXDESC_RSVD) {
error = EFBIG;
 1589                 goto fail_unload;
 1590         }
 1592         /*
 1593          * Make sure that the caches are synchronized before we
 1594          * ask the chip to start DMA for the packet data.
 1595          */
bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
BUS_DMASYNC_PREWRITE);
 1599         /*
 1600          * Map the segment array into descriptors. Note that we set the
 1601          * start-of-frame and end-of-frame markers for either TX or RX, but
 1602          * they really only have meaning in the TX case. (In the RX case,
 1603          * it's the chip that tells us where packets begin and end.)
 1604          * We also keep track of the end of the ring and set the
 1605          * end-of-ring bits as needed, and we set the ownership bits
 1606          * in all except the very first descriptor. (The caller will
 1607          * set this descriptor later when it start transmission or
 1608          * reception.)
 1609          */
curidx = startidx = sc->rl_ldata.rl_tx_nextfree;
lastidx = -1;
 1612         for (seg = 0; seg < map->dm_nsegs;
seg++, curidx = RL_NEXT_TX_DESC(sc, curidx)) {
d = &sc->rl_ldata.rl_tx_list[curidx];
RL_TXDESCSYNC(sc, curidx,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
cmdstat = letoh32(d->rl_cmdstat);
RL_TXDESCSYNC(sc, curidx, BUS_DMASYNC_PREREAD);
 1619                 if (cmdstat & RL_TDESC_STAT_OWN) {
printf("%s: tried to map busy TX descriptor\n",
sc->sc_dev.dv_xname);
 1622                         for (; seg > 0; seg --) {
uidx = (curidx + RL_TX_DESC_CNT(sc) - seg) %
RL_TX_DESC_CNT(sc);
sc->rl_ldata.rl_tx_list[uidx].rl_cmdstat = 0;
RL_TXDESCSYNC(sc, uidx,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 1628                         }
error = ENOBUFS;
 1630                         goto fail_unload;
 1631                 }
d->rl_vlanctl = 0;
re_set_bufaddr(d, map->dm_segs[seg].ds_addr);
cmdstat = rl_flags | map->dm_segs[seg].ds_len;
 1636                 if (seg == 0)
cmdstat |= RL_TDESC_CMD_SOF;
 1638                 else
cmdstat |= RL_TDESC_CMD_OWN;
 1640                 if (curidx == (RL_TX_DESC_CNT(sc) - 1))
cmdstat |= RL_TDESC_CMD_EOR;
 1642                 if (seg == nsegs - 1) {
cmdstat |= RL_TDESC_CMD_EOF;
lastidx = curidx;
 1645                 }
d->rl_cmdstat = htole32(cmdstat);
RL_TXDESCSYNC(sc, curidx,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 1649         }
 1650         if (pad) {
bus_addr_t paddaddr;
d = &sc->rl_ldata.rl_tx_list[curidx];
d->rl_vlanctl = 0;
paddaddr = RL_TXPADDADDR(sc);
re_set_bufaddr(d, paddaddr);
cmdstat = rl_flags |
RL_TDESC_CMD_OWN | RL_TDESC_CMD_EOF |
 1659                     (RL_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len);
 1660                 if (curidx == (RL_TX_DESC_CNT(sc) - 1))
cmdstat |= RL_TDESC_CMD_EOR;
d->rl_cmdstat = htole32(cmdstat);
RL_TXDESCSYNC(sc, curidx,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
lastidx = curidx;
curidx = RL_NEXT_TX_DESC(sc, curidx);
 1667         }
KASSERT(lastidx != -1);
 1670         /*
 1671          * Set up hardware VLAN tagging. Note: vlan tag info must
 1672          * appear in the first descriptor of a multi-descriptor
 1673          * transmission attempt.
 1674          */
 1676 #if NVLAN > 0
 1677         if (ifv != NULL) {
sc->rl_ldata.rl_tx_list[startidx].rl_vlanctl =
htole32(swap16(ifv->ifv_tag) |
RL_TDESC_VLANCTL_TAG);
 1681         }
 1682 #endif
 1684         /* Transfer ownership of packet to the chip. */
sc->rl_ldata.rl_tx_list[startidx].rl_cmdstat |=
htole32(RL_TDESC_CMD_OWN);
RL_TXDESCSYNC(sc, startidx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 1690         /* update info of TX queue and descriptors */
txq->txq_mbuf = m;
txq->txq_descidx = lastidx;
txq->txq_nsegs = nsegs;
sc->rl_ldata.rl_tx_free -= nsegs;
sc->rl_ldata.rl_tx_nextfree = curidx;
 1698         *idx = RL_NEXT_TXQ(sc, *idx);
 1700         return (0);
fail_unload:
bus_dmamap_unload(sc->sc_dmat, map);
 1705         return (error);
 1706 }
 1708 /*
 1709  * Main transmit routine for C+ and gigE NICs.
 1710  */
 1712 void
re_start(struct ifnet *ifp)
 1714 {
 1715         struct rl_softc *sc;
 1716         int             idx, queued = 0;
sc = ifp->if_softc;
 1720         if (!sc->rl_link || ifp->if_flags & IFF_OACTIVE)
 1721                 return;
idx = sc->rl_ldata.rl_txq_prodidx;
 1724         for (;;) {
 1725                 struct mbuf *m;
 1726                 int error;
IFQ_POLL(&ifp->if_snd, m);
 1729                 if (m == NULL)
 1730                         break;
 1732                 if (sc->rl_ldata.rl_txq[idx].txq_mbuf != NULL) {
KASSERT(idx == sc->rl_ldata.rl_txq_considx);
ifp->if_flags |= IFF_OACTIVE;
 1735                         break;
 1736                 }
error = re_encap(sc, m, &idx);
 1739                 if (error == EFBIG &&
sc->rl_ldata.rl_tx_free == RL_TX_DESC_CNT(sc)) {
IFQ_DEQUEUE(&ifp->if_snd, m);
m_freem(m);
ifp->if_oerrors++;
 1744                         continue;
 1745                 }
 1746                 if (error) {
ifp->if_flags |= IFF_OACTIVE;
 1748                         break;
 1749                 }
IFQ_DEQUEUE(&ifp->if_snd, m);
queued++;
 1754 #if NBPFILTER > 0
 1755                 /*
 1756                  * If there's a BPF listener, bounce a copy of this frame
 1757                  * to him.
 1758                  */
 1759                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
 1761 #endif
 1762         }
 1764         if (queued == 0) {
 1765                 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT(sc))
CSR_WRITE_4(sc, RL_TIMERCNT, 1);
 1767                 return;
 1768         }
sc->rl_ldata.rl_txq_prodidx = idx;
CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
 1774         /*
 1775          * Use the countdown timer for interrupt moderation.
 1776          * 'TX done' interrupts are disabled. Instead, we reset the
 1777          * countdown timer, which will begin counting until it hits
 1778          * the value in the TIMERINT register, and then trigger an
 1779          * interrupt. Each time we write to the TIMERCNT register,
 1780          * the timer count is reset to 0.
 1781          */
CSR_WRITE_4(sc, RL_TIMERCNT, 1);
 1784         /*
 1785          * Set a timeout in case the chip goes out to lunch.
 1786          */
ifp->if_timer = 5;
 1788 }
 1790 int
re_init(struct ifnet *ifp)
 1792 {
 1793         struct rl_softc *sc = ifp->if_softc;
u_int32_t       rxcfg = 0;
 1795         int             s;
 1796         union {
u_int32_t align_dummy;
u_char eaddr[ETHER_ADDR_LEN];
 1799         } eaddr;
s = splnet();
 1803         /*
 1804          * Cancel pending I/O and free all RX/TX buffers.
 1805          */
re_stop(ifp, 0);
 1808         /*
 1809          * Enable C+ RX and TX mode, as well as RX checksum offload.
 1810          * We must configure the C+ register before all others.
 1811          */
CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
RL_CPLUSCMD_RXCSUM_ENB);
 1816         /*
 1817          * Init our MAC address.  Even though the chipset
 1818          * documentation doesn't mention it, we need to enter "Config
 1819          * register write enable" mode to modify the ID registers.
 1820          */
bcopy(sc->sc_arpcom.ac_enaddr, eaddr.eaddr, ETHER_ADDR_LEN);
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
CSR_WRITE_4(sc, RL_IDR4,
htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
CSR_WRITE_4(sc, RL_IDR0,
htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 1829         /*
 1830          * For C+ mode, initialize the RX descriptors and mbufs.
 1831          */
re_rx_list_init(sc);
re_tx_list_init(sc);
 1835         /*
 1836          * Load the addresses of the RX and TX lists into the chip.
 1837          */
CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
RL_ADDR_HI(sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr));
CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
RL_ADDR_LO(sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr));
CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
RL_ADDR_HI(sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr));
CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
RL_ADDR_LO(sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr));
 1848         /*
 1849          * Enable transmit and receive.
 1850          */
CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
 1853         /*
 1854          * Set the initial TX and RX configuration.
 1855          */
 1856         if (sc->rl_testmode) {
 1857                 if (sc->rl_type == RL_8169)
CSR_WRITE_4(sc, RL_TXCFG,
RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
 1860                 else
CSR_WRITE_4(sc, RL_TXCFG,
RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
 1863         } else
CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
 1870         /* Set the individual bit to receive frames for this host only. */
rxcfg = CSR_READ_4(sc, RL_RXCFG);
rxcfg |= RL_RXCFG_RX_INDIV;
 1874         /*
 1875          * Set capture broadcast bit to capture broadcast frames.
 1876          */
 1877         if (ifp->if_flags & IFF_BROADCAST)
rxcfg |= RL_RXCFG_RX_BROAD;
 1879         else
rxcfg &= ~RL_RXCFG_RX_BROAD;
CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1884         /* Set promiscuous mode. */
re_setpromisc(sc);
 1887         /*
 1888          * Program the multicast filter, if necessary.
 1889          */
re_setmulti(sc);
 1892         /*
 1893          * Enable interrupts.
 1894          */
 1895         if (sc->rl_testmode)
CSR_WRITE_2(sc, RL_IMR, 0);
 1897         else
CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
 1901         /* Start RX/TX process. */
CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
 1903 #ifdef notdef
 1904         /* Enable receiver and transmitter. */
CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
 1906 #endif
 1908         /*
 1909          * Initialize the timer interrupt register so that
 1910          * a timer interrupt will be generated once the timer
 1911          * reaches a certain number of ticks. The timer is
 1912          * reloaded on each transmit. This gives us TX interrupt
 1913          * moderation, which dramatically improves TX frame rate.
 1914          */
 1915         if (sc->rl_type == RL_8169)
CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
 1917         else
CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
 1920         /*
 1921          * For 8169 gigE NICs, set the max allowed RX packet
 1922          * size so we can receive jumbo frames.
 1923          */
 1924         if (sc->rl_type == RL_8169)
CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
 1927         if (sc->rl_testmode)
 1928                 return (0);
mii_mediachg(&sc->sc_mii);
CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
splx(s);
sc->rl_link = 0;
timeout_add(&sc->timer_handle, hz);
 1943         return (0);
 1944 }
 1946 /*
 1947  * Set media options.
 1948  */
 1949 int
re_ifmedia_upd(struct ifnet *ifp)
 1951 {
 1952         struct rl_softc *sc;
sc = ifp->if_softc;
 1956         return (mii_mediachg(&sc->sc_mii));
 1957 }
 1959 /*
 1960  * Report current media status.
 1961  */
 1962 void
re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 1964 {
 1965         struct rl_softc *sc;
sc = ifp->if_softc;
mii_pollstat(&sc->sc_mii);
ifmr->ifm_active = sc->sc_mii.mii_media_active;
ifmr->ifm_status = sc->sc_mii.mii_media_status;
 1972 }
 1974 int
re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 1976 {
 1977         struct rl_softc *sc = ifp->if_softc;
 1978         struct ifreq    *ifr = (struct ifreq *) data;
 1979         struct ifaddr *ifa = (struct ifaddr *)data;
 1980         int             s, error = 0;
s = splnet();
 1984         if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command,
data)) > 0) {
splx(s);
 1987                 return (error);
 1988         }
 1990         switch(command) {
 1991         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
 1993                 if (!(ifp->if_flags & IFF_RUNNING))
re_init(ifp);
 1995 #ifdef INET
 1996                 if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc->sc_arpcom, ifa);
 1998 #endif /* INET */
 1999                 break;
 2000         case SIOCSIFMTU:
 2001                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
error = EINVAL;
 2003                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
 2005                 break;
 2006         case SIOCSIFFLAGS:
 2007                 if (ifp->if_flags & IFF_UP) {
 2008                         if (ifp->if_flags & IFF_RUNNING &&
 2009                             ((ifp->if_flags ^ sc->if_flags) &
IFF_PROMISC)) {
re_setpromisc(sc);
 2012                         } else {
 2013                                 if (!(ifp->if_flags & IFF_RUNNING))
re_init(ifp);
 2015                         }
 2016                 } else {
 2017                         if (ifp->if_flags & IFF_RUNNING)
re_stop(ifp, 1);
 2019                 }
sc->if_flags = ifp->if_flags;
 2021                 break;
 2022         case SIOCADDMULTI:
 2023         case SIOCDELMULTI:
error = (command == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_arpcom) :
ether_delmulti(ifr, &sc->sc_arpcom);
 2027                 if (error == ENETRESET) {
 2028                         /*
 2029                          * Multicast list has changed; set the hardware
 2030                          * filter accordingly.
 2031                          */
 2032                         if (ifp->if_flags & IFF_RUNNING)
re_setmulti(sc);
error = 0;
 2035                 }
 2036                 break;
 2037         case SIOCGIFMEDIA:
 2038         case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
 2040                 break;
 2041         default:
error = EINVAL;
 2043                 break;
 2044         }
splx(s);
 2048         return (error);
 2049 }
 2051 void
re_watchdog(struct ifnet *ifp)
 2053 {
 2054         struct rl_softc *sc;
 2055         int     s;
sc = ifp->if_softc;
s = splnet();
printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
ifp->if_oerrors++;
re_txeof(sc);
re_rxeof(sc);
re_init(ifp);
splx(s);
 2068 }
 2070 /*
 2071  * Stop the adapter and free any mbufs allocated to the
 2072  * RX and TX lists.
 2073  */
 2074 void
re_stop(struct ifnet *ifp, int disable)
 2076 {
 2077         struct rl_softc *sc;
 2078         int     i;
sc = ifp->if_softc;
ifp->if_timer = 0;
sc->rl_link = 0;
timeout_del(&sc->timer_handle);
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
mii_down(&sc->sc_mii);
CSR_WRITE_1(sc, RL_COMMAND, 0x00);
CSR_WRITE_2(sc, RL_IMR, 0x0000);
CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
 2094         if (sc->rl_head != NULL) {
m_freem(sc->rl_head);
sc->rl_head = sc->rl_tail = NULL;
 2097         }
 2099         /* Free the TX list buffers. */
 2100         for (i = 0; i < RL_TX_QLEN; i++) {
 2101                 if (sc->rl_ldata.rl_txq[i].txq_mbuf != NULL) {
bus_dmamap_unload(sc->sc_dmat,
sc->rl_ldata.rl_txq[i].txq_dmamap);
m_freem(sc->rl_ldata.rl_txq[i].txq_mbuf);
sc->rl_ldata.rl_txq[i].txq_mbuf = NULL;
 2106                 }
 2107         }
 2109         /* Free the RX list buffers. */
 2110         for (i = 0; i < RL_RX_DESC_CNT; i++) {
 2111                 if (sc->rl_ldata.rl_rxsoft[i].rxs_mbuf != NULL) {
bus_dmamap_unload(sc->sc_dmat,
sc->rl_ldata.rl_rxsoft[i].rxs_dmamap);
m_freem(sc->rl_ldata.rl_rxsoft[i].rxs_mbuf);
sc->rl_ldata.rl_rxsoft[i].rxs_mbuf = NULL;
 2116                 }
 2117         }
 2118 }