CSR_WRITE_1 821 dev/ic/fxp.c CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); CSR_WRITE_1 833 dev/ic/fxp.c CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); CSR_WRITE_1 1146 dev/ic/fxp.c CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); CSR_WRITE_1 1414 dev/ic/fxp.c CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); CSR_WRITE_1 201 dev/ic/re.c CSR_WRITE_1(sc, RL_EECMD, \ CSR_WRITE_1 205 dev/ic/re.c CSR_WRITE_1(sc, RL_EECMD, \ CSR_WRITE_1 600 dev/ic/re.c CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); CSR_WRITE_1 610 dev/ic/re.c CSR_WRITE_1(sc, 0x82, 1); CSR_WRITE_1 1429 dev/ic/re.c CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); CSR_WRITE_1 1772 dev/ic/re.c CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); CSR_WRITE_1 1822 dev/ic/re.c CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); CSR_WRITE_1 1827 dev/ic/re.c CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); CSR_WRITE_1 1851 dev/ic/re.c CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); CSR_WRITE_1 1866 dev/ic/re.c CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); CSR_WRITE_1 1905 dev/ic/re.c CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); CSR_WRITE_1 1932 dev/ic/re.c CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); CSR_WRITE_1 2090 dev/ic/re.c CSR_WRITE_1(sc, RL_COMMAND, 0x00); CSR_WRITE_1 166 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_EECMD, \ CSR_WRITE_1 170 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_EECMD, \ CSR_WRITE_1 213 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); CSR_WRITE_1 220 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); CSR_WRITE_1 235 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); CSR_WRITE_1 271 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_MII, \ CSR_WRITE_1 275 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_MII, \ CSR_WRITE_1 525 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); CSR_WRITE_1 984 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); CSR_WRITE_1 989 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); CSR_WRITE_1 1000 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); CSR_WRITE_1 1045 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); CSR_WRITE_1 1049 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); CSR_WRITE_1 1195 dev/ic/rtl81x9.c CSR_WRITE_1(sc, RL_COMMAND, 0x00); CSR_WRITE_1 789 dev/ic/rtl81x9reg.h CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) CSR_WRITE_1 792 dev/ic/rtl81x9reg.h CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) CSR_WRITE_1 485 dev/ic/xl.c CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); CSR_WRITE_1 487 dev/ic/xl.c CSR_WRITE_1(sc, XL_W3_MAC_CTRL, CSR_WRITE_1 781 dev/ic/xl.c CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); CSR_WRITE_1 784 dev/ic/xl.c CSR_WRITE_1(sc, XL_W3_MAC_CTRL, CSR_WRITE_1 1449 dev/ic/xl.c CSR_WRITE_1(sc, XL_DOWN_POLL, 64); CSR_WRITE_1 1462 dev/ic/xl.c CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); CSR_WRITE_1 1488 dev/ic/xl.c CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); CSR_WRITE_1 1962 dev/ic/xl.c CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, CSR_WRITE_1 1997 dev/ic/xl.c CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); CSR_WRITE_1 2068 dev/ic/xl.c CSR_WRITE_1(sc, XL_DOWN_POLL, 64); CSR_WRITE_1 2102 dev/ic/xl.c CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); CSR_WRITE_1 1989 dev/pci/if_ipw.c CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); CSR_WRITE_1 303 dev/pci/if_ipwreg.h CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \ CSR_WRITE_1 455 dev/pci/if_iwireg.h CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \ CSR_WRITE_1 253 dev/pci/if_msk.c CSR_WRITE_1(sc, reg, x); CSR_WRITE_1 830 dev/pci/if_msk.c CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET); CSR_WRITE_1 831 dev/pci/if_msk.c CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET); CSR_WRITE_1 834 dev/pci/if_msk.c CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET); CSR_WRITE_1 836 dev/pci/if_msk.c CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET); CSR_WRITE_1 870 dev/pci/if_msk.c CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET); CSR_WRITE_1 877 dev/pci/if_msk.c CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP); CSR_WRITE_1 878 dev/pci/if_msk.c CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR); CSR_WRITE_1 884 dev/pci/if_msk.c CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP); CSR_WRITE_1 885 dev/pci/if_msk.c CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR); CSR_WRITE_1 244 dev/pci/if_sk.c CSR_WRITE_1(sc, reg, x); CSR_WRITE_1 136 dev/pci/if_ste.c CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) CSR_WRITE_1 139 dev/pci/if_ste.c CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) CSR_WRITE_1 1108 dev/pci/if_ste.c CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); CSR_WRITE_1 1121 dev/pci/if_ste.c CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); CSR_WRITE_1 1127 dev/pci/if_ste.c CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, ETHER_MAX_DIX_LEN >> 8); CSR_WRITE_1 1133 dev/pci/if_ste.c CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (ETHER_MAX_DIX_LEN >> 4)); CSR_WRITE_1 1136 dev/pci/if_ste.c CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); CSR_WRITE_1 1163 dev/pci/if_ste.c CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); CSR_WRITE_1 1470 dev/pci/if_ste.c CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); CSR_WRITE_1 1241 dev/pci/if_stge.c CSR_WRITE_1(sc, STGE_StationAddress0 + i, CSR_WRITE_1 1274 dev/pci/if_stge.c CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); CSR_WRITE_1 1277 dev/pci/if_stge.c CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64); CSR_WRITE_1 1283 dev/pci/if_stge.c CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); CSR_WRITE_1 1284 dev/pci/if_stge.c CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); CSR_WRITE_1 1290 dev/pci/if_stge.c CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); CSR_WRITE_1 1291 dev/pci/if_stge.c CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); CSR_WRITE_1 1699 dev/pci/if_stge.c CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl); CSR_WRITE_1 336 dev/pci/if_tl.c CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); CSR_WRITE_1 370 dev/pci/if_tl.c CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); CSR_WRITE_1 385 dev/pci/if_tl.c CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); CSR_WRITE_1 204 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_EEADDR, addr); CSR_WRITE_1 262 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_MIICMD, 0); CSR_WRITE_1 281 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_MIICMD, 0); CSR_WRITE_1 282 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); CSR_WRITE_1 297 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); CSR_WRITE_1 326 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_MIIADDR, reg); CSR_WRITE_1 362 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_MIIADDR, reg); CSR_WRITE_1 398 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); CSR_WRITE_1 400 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CAM0 + i, 0); CSR_WRITE_1 404 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); CSR_WRITE_1 406 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CAM0 + i, 0); CSR_WRITE_1 408 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CAMADDR, 0); CSR_WRITE_1 428 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); CSR_WRITE_1 432 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); CSR_WRITE_1 462 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CAMADDR, 0); CSR_WRITE_1 538 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); CSR_WRITE_1 548 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); CSR_WRITE_1 1177 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); CSR_WRITE_1 1231 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); CSR_WRITE_1 1256 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); CSR_WRITE_1 1257 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); CSR_WRITE_1 1275 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); CSR_WRITE_1 1485 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); CSR_WRITE_1 1522 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); CSR_WRITE_1 1560 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); CSR_WRITE_1 1561 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); CSR_WRITE_1 1567 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); CSR_WRITE_1 1592 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRS2, 0x8B); CSR_WRITE_1 1597 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); CSR_WRITE_1 1598 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); CSR_WRITE_1 1599 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRS0, CSR_WRITE_1 1618 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); CSR_WRITE_1 1622 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ CSR_WRITE_1 1625 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); CSR_WRITE_1 1626 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); CSR_WRITE_1 1631 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ CSR_WRITE_1 1643 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); CSR_WRITE_1 1848 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); CSR_WRITE_1 1849 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); CSR_WRITE_1 1852 dev/pci/if_vge.c CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); CSR_WRITE_1 113 dev/pci/if_vgevar.h CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) CSR_WRITE_1 120 dev/pci/if_vgevar.h CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) CSR_WRITE_1 155 dev/pci/if_vr.c CSR_WRITE_1(sc, reg, \ CSR_WRITE_1 159 dev/pci/if_vr.c CSR_WRITE_1(sc, reg, \ CSR_WRITE_1 179 dev/pci/if_vr.c CSR_WRITE_1(sc, VR_MIICMD, \ CSR_WRITE_1 183 dev/pci/if_vr.c CSR_WRITE_1(sc, VR_MIICMD, \ CSR_WRITE_1 248 dev/pci/if_vr.c CSR_WRITE_1(sc, VR_MIICMD, 0); CSR_WRITE_1 328 dev/pci/if_vr.c CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| CSR_WRITE_1 332 dev/pci/if_vr.c CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); CSR_WRITE_1 361 dev/pci/if_vr.c CSR_WRITE_1(sc, VR_MIICMD, 0); CSR_WRITE_1 408 dev/pci/if_vr.c CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| CSR_WRITE_1 412 dev/pci/if_vr.c CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); CSR_WRITE_1 507 dev/pci/if_vr.c CSR_WRITE_1(sc, VR_RXCFG, rxfilt); CSR_WRITE_1 541 dev/pci/if_vr.c CSR_WRITE_1(sc, VR_RXCFG, rxfilt); CSR_WRITE_1 1409 dev/pci/if_vr.c CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); CSR_WRITE_1 1512 dev/pci/if_wb.c CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); CSR_WRITE_1 166 dev/sdmmc/sbt.c CSR_WRITE_1(sc, SBT_REG_IENA, ISTAT_INTRD); CSR_WRITE_1 285 dev/sdmmc/sbt.c CSR_WRITE_1(sc, SBT_REG_RPC, 0); CSR_WRITE_1 289 dev/sdmmc/sbt.c CSR_WRITE_1(sc, SBT_REG_RPC, RPC_PCRRT); CSR_WRITE_1 295 dev/sdmmc/sbt.c CSR_WRITE_1(sc, SBT_REG_RPC, 0); CSR_WRITE_1 317 dev/sdmmc/sbt.c CSR_WRITE_1(sc, SBT_REG_ICLR, status);