root/dev/ic/rtl81x9.c

DEFINITIONS

1. rl_eeprom_putbyte
2. rl_eeprom_getword
3. rl_read_eeprom
4. rl_mii_sync
5. rl_mii_send
6. rl_mii_readreg
7. rl_mii_writereg
8. rl_setmulti
9. rl_reset
10. rl_list_tx_init
11. rl_rxeof
12. rl_txeof
13. rl_intr
14. rl_encap
15. rl_start
16. rl_init
17. rl_ifmedia_upd
18. rl_ifmedia_sts
19. rl_ioctl
20. rl_watchdog
21. rl_stop
22. rl_attach
23. rl_shutdown
24. rl_powerhook
25. rl_miibus_readreg
26. rl_miibus_writereg
27. rl_miibus_statchg
28. rl_tick

    1 /*      $OpenBSD: rtl81x9.c,v 1.56 2007/05/08 18:49:32 deraadt Exp $ */
    3 /*
    4  * Copyright (c) 1997, 1998
    5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  */
   35 /*
   36  * RealTek 8129/8139 PCI NIC driver
   37  *
   38  * Supports several extremely cheap PCI 10/100 adapters based on
   39  * the RealTek chipset. Datasheets can be obtained from
   40  * www.realtek.com.tw.
   41  *
   42  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   43  * Electrical Engineering Department
   44  * Columbia University, New York City
   45  */
   47 /*
   48  * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
   49  * probably the worst PCI ethernet controller ever made, with the possible
   50  * exception of the FEAST chip made by SMC. The 8139 supports bus-master
   51  * DMA, but it has a terrible interface that nullifies any performance
   52  * gains that bus-master DMA usually offers.
   53  *
   54  * For transmission, the chip offers a series of four TX descriptor
   55  * registers. Each transmit frame must be in a contiguous buffer, aligned
   56  * on a longword (32-bit) boundary. This means we almost always have to
   57  * do mbuf copies in order to transmit a frame, except in the unlikely
   58  * case where a) the packet fits into a single mbuf, and b) the packet
   59  * is 32-bit aligned within the mbuf's data area. The presence of only
   60  * four descriptor registers means that we can never have more than four
   61  * packets queued for transmission at any one time.
   62  *
   63  * Reception is not much better. The driver has to allocate a single large
   64  * buffer area (up to 64K in size) into which the chip will DMA received
   65  * frames. Because we don't know where within this region received packets
   66  * will begin or end, we have no choice but to copy data from the buffer
   67  * area into mbufs in order to pass the packets up to the higher protocol
   68  * levels.
   69  *
   70  * It's impossible given this rotten design to really achieve decent
   71  * performance at 100Mbps, unless you happen to have a 400MHz PII or
   72  * some equally overmuscled CPU to drive it.
   73  *
   74  * On the bright side, the 8139 does have a built-in PHY, although
   75  * rather than using an MDIO serial interface like most other NICs, the
   76  * PHY registers are directly accessible through the 8139's register
   77  * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
   78  * filter.
   79  *
   80  * The 8129 chip is an older version of the 8139 that uses an external PHY
   81  * chip. The 8129 has a serial MDIO interface for accessing the MII where
   82  * the 8139 lets you directly access the on-board PHY registers. We need
   83  * to select which interface to use depending on the chip type.
   84  */
   86 #include "bpfilter.h"
   88 #include <sys/param.h>
   89 #include <sys/systm.h>
   90 #include <sys/sockio.h>
   91 #include <sys/mbuf.h>
   92 #include <sys/malloc.h>
   93 #include <sys/kernel.h>
   94 #include <sys/socket.h>
   95 #include <sys/device.h>
   96 #include <sys/timeout.h>
   98 #include <net/if.h>
   99 #include <net/if_dl.h>
  100 #include <net/if_types.h>
  102 #ifdef INET
  103 #include <netinet/in.h>
  104 #include <netinet/in_systm.h>
  105 #include <netinet/in_var.h>
  106 #include <netinet/ip.h>
  107 #include <netinet/if_ether.h>
  108 #endif
  110 #include <net/if_media.h>
  112 #if NBPFILTER > 0
  113 #include <net/bpf.h>
  114 #endif
  116 #include <machine/bus.h>
  118 #include <dev/mii/mii.h>
  119 #include <dev/mii/miivar.h>
  120 #include <dev/pci/pcireg.h>
  121 #include <dev/pci/pcivar.h>
  122 #include <dev/pci/pcidevs.h>
  124 #include <dev/ic/rtl81x9reg.h>
  126 /*
  127  * Various supported PHY vendors/types and their names. Note that
  128  * this driver will work with pretty much any MII-compliant PHY,
  129  * so failure to positively identify the chip is not a fatal error.
  130  */
  132 void rl_tick(void *);
  133 void rl_shutdown(void *);
  134 void rl_powerhook(int, void *);
  136 int rl_encap(struct rl_softc *, struct mbuf * );
  138 void rl_rxeof(struct rl_softc *);
  139 void rl_txeof(struct rl_softc *);
  140 void rl_start(struct ifnet *);
  141 int rl_ioctl(struct ifnet *, u_long, caddr_t);
  142 void rl_init(void *);
  143 void rl_stop(struct rl_softc *);
  144 void rl_watchdog(struct ifnet *);
  145 int rl_ifmedia_upd(struct ifnet *);
  146 void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  148 void rl_eeprom_getword(struct rl_softc *, int, int, u_int16_t *);
  149 void rl_eeprom_putbyte(struct rl_softc *, int, int);
  150 void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int, int);
  152 void rl_mii_sync(struct rl_softc *);
  153 void rl_mii_send(struct rl_softc *, u_int32_t, int);
  154 int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
  155 int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
  157 int rl_miibus_readreg(struct device *, int, int);
  158 void rl_miibus_writereg(struct device *, int, int, int);
  159 void rl_miibus_statchg(struct device *);
  161 void rl_setmulti(struct rl_softc *);
  162 void rl_reset(struct rl_softc *);
  163 int rl_list_tx_init(struct rl_softc *);
  165 #define EE_SET(x)                                       \
CSR_WRITE_1(sc, RL_EECMD,                       \
CSR_READ_1(sc, RL_EECMD) | x)
  169 #define EE_CLR(x)                                       \
CSR_WRITE_1(sc, RL_EECMD,                       \
CSR_READ_1(sc, RL_EECMD) & ~x)
  173 /*
  174  * Send a read command and address to the EEPROM, check for ACK.
  175  */
  176 void rl_eeprom_putbyte(sc, addr, addr_len)
  177         struct rl_softc         *sc;
  178         int                     addr, addr_len;
  179 {
  180         register int            d, i;
d = (RL_EECMD_READ << addr_len) | addr;
  184         /*
  185          * Feed in each bit and strobe the clock.
  186          */
  187         for (i = RL_EECMD_LEN + addr_len; i; i--) {
  188                 if (d & (1 << (i - 1)))
EE_SET(RL_EE_DATAIN);
  190                 else
EE_CLR(RL_EE_DATAIN);
DELAY(100);
EE_SET(RL_EE_CLK);
DELAY(150);
EE_CLR(RL_EE_CLK);
DELAY(100);
  198         }
  199 }
  201 /*
  202  * Read a word of data stored in the EEPROM at address 'addr.'
  203  */
  204 void rl_eeprom_getword(sc, addr, addr_len, dest)
  205         struct rl_softc         *sc;
  206         int                     addr, addr_len;
u_int16_t               *dest;
  208 {
  209         register int            i;
u_int16_t               word = 0;
  212         /* Enter EEPROM access mode. */
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
  215         /*
  216          * Send address of word we want to read.
  217          */
rl_eeprom_putbyte(sc, addr, addr_len);
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
  222         /*
  223          * Start reading bits from EEPROM.
  224          */
  225         for (i = 16; i > 0; i--) {
EE_SET(RL_EE_CLK);
DELAY(100);
  228                 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
word |= 1 << (i - 1);
EE_CLR(RL_EE_CLK);
DELAY(100);
  232         }
  234         /* Turn off EEPROM access mode. */
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
  237         *dest = word;
  238 }
  240 /*
  241  * Read a sequence of words from the EEPROM.
  242  */
  243 void rl_read_eeprom(sc, dest, off, addr_len, cnt, swap)
  244         struct rl_softc         *sc;
caddr_t                 dest;
  246         int                     off;
  247         int                     addr_len;
  248         int                     cnt;
  249         int                     swap;
  250 {
  251         int                     i;
u_int16_t               word = 0, *ptr;
  254         for (i = 0; i < cnt; i++) {
rl_eeprom_getword(sc, off + i, addr_len, &word);
ptr = (u_int16_t *)(dest + (i * 2));
  257                 if (swap)
  258                         *ptr = letoh16(word);
  259                 else
  260                         *ptr = word;
  261         }
  262 }
  264 /*
  265  * MII access routines are provided for the 8129, which
  266  * doesn't have a built-in PHY. For the 8139, we fake things
  267  * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
  268  * direct access PHY registers.
  269  */
  270 #define MII_SET(x)                                      \
CSR_WRITE_1(sc, RL_MII,                         \
CSR_READ_1(sc, RL_MII) | x)
  274 #define MII_CLR(x)                                      \
CSR_WRITE_1(sc, RL_MII,                         \
CSR_READ_1(sc, RL_MII) & ~x)
  278 /*
  279  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  280  */
  281 void rl_mii_sync(sc)
  282         struct rl_softc         *sc;
  283 {
  284         register int            i;
MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
  288         for (i = 0; i < 32; i++) {
MII_SET(RL_MII_CLK);
DELAY(1);
MII_CLR(RL_MII_CLK);
DELAY(1);
  293         }
  294 }
  296 /*
  297  * Clock a series of bits through the MII.
  298  */
  299 void rl_mii_send(sc, bits, cnt)
  300         struct rl_softc         *sc;
u_int32_t               bits;
  302         int                     cnt;
  303 {
  304         int                     i;
MII_CLR(RL_MII_CLK);
  308         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  309                 if (bits & i)
MII_SET(RL_MII_DATAOUT);
  311                 else
MII_CLR(RL_MII_DATAOUT);
DELAY(1);
MII_CLR(RL_MII_CLK);
DELAY(1);
MII_SET(RL_MII_CLK);
  317         }
  318 }
  320 /*
  321  * Read an PHY register through the MII.
  322  */
  323 int rl_mii_readreg(sc, frame)
  324         struct rl_softc         *sc;
  325         struct rl_mii_frame     *frame;
  326 {
  327         int                     i, ack, s;
s = splnet();
  331         /*
  332          * Set up frame for RX.
  333          */
frame->mii_stdelim = RL_MII_STARTDELIM;
frame->mii_opcode = RL_MII_READOP;
frame->mii_turnaround = 0;
frame->mii_data = 0;
CSR_WRITE_2(sc, RL_MII, 0);
  341         /*
  342          * Turn on data xmit.
  343          */
MII_SET(RL_MII_DIR);
rl_mii_sync(sc);
  348         /*
  349          * Send command/address info.
  350          */
rl_mii_send(sc, frame->mii_stdelim, 2);
rl_mii_send(sc, frame->mii_opcode, 2);
rl_mii_send(sc, frame->mii_phyaddr, 5);
rl_mii_send(sc, frame->mii_regaddr, 5);
  356         /* Idle bit */
MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
DELAY(1);
MII_SET(RL_MII_CLK);
DELAY(1);
  362         /* Turn off xmit. */
MII_CLR(RL_MII_DIR);
  365         /* Check for ack */
MII_CLR(RL_MII_CLK);
DELAY(1);
ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
MII_SET(RL_MII_CLK);
DELAY(1);
  372         /*
  373          * Now try reading data bits. If the ack failed, we still
  374          * need to clock through 16 cycles to keep the PHY(s) in sync.
  375          */
  376         if (ack) {
  377                 for(i = 0; i < 16; i++) {
MII_CLR(RL_MII_CLK);
DELAY(1);
MII_SET(RL_MII_CLK);
DELAY(1);
  382                 }
  383                 goto fail;
  384         }
  386         for (i = 0x8000; i; i >>= 1) {
MII_CLR(RL_MII_CLK);
DELAY(1);
  389                 if (!ack) {
  390                         if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
frame->mii_data |= i;
DELAY(1);
  393                 }
MII_SET(RL_MII_CLK);
DELAY(1);
  396         }
fail:
MII_CLR(RL_MII_CLK);
DELAY(1);
MII_SET(RL_MII_CLK);
DELAY(1);
splx(s);
  407         if (ack)
  408                 return(1);
  409         return(0);
  410 }
  412 /*
  413  * Write to a PHY register through the MII.
  414  */
  415 int rl_mii_writereg(sc, frame)
  416         struct rl_softc         *sc;
  417         struct rl_mii_frame     *frame;
  418 {
  419         int                     s;
s = splnet();
  422         /*
  423          * Set up frame for TX.
  424          */
frame->mii_stdelim = RL_MII_STARTDELIM;
frame->mii_opcode = RL_MII_WRITEOP;
frame->mii_turnaround = RL_MII_TURNAROUND;
  430         /*
  431          * Turn on data output.
  432          */
MII_SET(RL_MII_DIR);
rl_mii_sync(sc);
rl_mii_send(sc, frame->mii_stdelim, 2);
rl_mii_send(sc, frame->mii_opcode, 2);
rl_mii_send(sc, frame->mii_phyaddr, 5);
rl_mii_send(sc, frame->mii_regaddr, 5);
rl_mii_send(sc, frame->mii_turnaround, 2);
rl_mii_send(sc, frame->mii_data, 16);
  444         /* Idle bit. */
MII_SET(RL_MII_CLK);
DELAY(1);
MII_CLR(RL_MII_CLK);
DELAY(1);
  450         /*
  451          * Turn off xmit.
  452          */
MII_CLR(RL_MII_DIR);
splx(s);
  457         return(0);
  458 }
  460 /*
  461  * Program the 64-bit multicast hash filter.
  462  */
  463 void rl_setmulti(sc)
  464         struct rl_softc         *sc;
  465 {
  466         struct ifnet            *ifp;
  467         int                     h = 0;
u_int32_t               hashes[2] = { 0, 0 };
  469         struct arpcom           *ac = &sc->sc_arpcom;
  470         struct ether_multi      *enm;
  471         struct ether_multistep  step;
u_int32_t               rxfilt;
  473         int                     mcnt = 0;
ifp = &sc->sc_arpcom.ac_if;
rxfilt = CSR_READ_4(sc, RL_RXCFG);
allmulti:
  480         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
rxfilt |= RL_RXCFG_RX_MULTI;
CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
  485                 return;
  486         }
  488         /* first, zot all the existing hash bits */
CSR_WRITE_4(sc, RL_MAR0, 0);
CSR_WRITE_4(sc, RL_MAR4, 0);
  492         /* now program new ones */
ETHER_FIRST_MULTI(step, ac, enm);
  494         while (enm != NULL) {
  495                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
ifp->if_flags |= IFF_ALLMULTI;
  497                         goto allmulti;
  498                 }
mcnt++;
h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26;
  501                 if (h < 32)
hashes[0] |= (1 << h);
  503                 else
hashes[1] |= (1 << (h - 32));
mcnt++;
ETHER_NEXT_MULTI(step, enm);
  507         }
  509         if (mcnt)
rxfilt |= RL_RXCFG_RX_MULTI;
  511         else
rxfilt &= ~RL_RXCFG_RX_MULTI;
CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
  517 }
  519 void
rl_reset(sc)
  521         struct rl_softc         *sc;
  522 {
  523         register int            i;
CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
  527         for (i = 0; i < RL_TIMEOUT; i++) {
DELAY(10);
  529                 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
  530                         break;
  531         }
  532         if (i == RL_TIMEOUT)
printf("%s: reset never completed!\n", sc->sc_dev.dv_xname);
  535 }
  537 /*
  538  * Initialize the transmit descriptors.
  539  */
  540 int
rl_list_tx_init(sc)
  542         struct rl_softc         *sc;
  543 {
  544         struct rl_chain_data    *cd;
  545         int                     i;
cd = &sc->rl_cdata;
  548         for (i = 0; i < RL_TX_LIST_CNT; i++) {
cd->rl_tx_chain[i] = NULL;
CSR_WRITE_4(sc,
RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
  552         }
sc->rl_cdata.cur_tx = 0;
sc->rl_cdata.last_tx = 0;
  557         return(0);
  558 }
  560 /*
  561  * A frame has been uploaded: pass the resulting mbuf chain up to
  562  * the higher level protocols.
  563  *
  564  * You know there's something wrong with a PCI bus-master chip design
  565  * when you have to use m_devget().
  566  *
  567  * The receive operation is badly documented in the datasheet, so I'll
  568  * attempt to document it here. The driver provides a buffer area and
  569  * places its base address in the RX buffer start address register.
  570  * The chip then begins copying frames into the RX buffer. Each frame
  571  * is preceded by a 32-bit RX status word which specifies the length
  572  * of the frame and certain other status bits. Each frame (starting with
  573  * the status word) is also 32-bit aligned. The frame length is in the
  574  * first 16 bits of the status word; the lower 15 bits correspond with
  575  * the 'rx status register' mentioned in the datasheet.
  576  *
  577  * Note: to make the Alpha happy, the frame payload needs to be aligned
  578  * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
  579  * the ring buffer starting at an address two bytes before the actual
  580  * data location. We can then shave off the first two bytes using m_adj().
  581  * The reason we do this is because m_devget() doesn't let us specify an
  582  * offset into the mbuf storage space, so we have to artificially create
  583  * one. The ring is allocated in such a way that there are a few unused
  584  * bytes of space preceding it so that it will be safe for us to do the
  585  * 2-byte backstep even if reading from the ring at offset 0.
  586  */
  587 void
rl_rxeof(sc)
  589         struct rl_softc         *sc;
  590 {
  591         struct mbuf             *m;
  592         struct ifnet            *ifp;
  593         int                     total_len;
u_int32_t               rxstat;
caddr_t                 rxbufpos;
  596         int                     wrap = 0;
u_int16_t               cur_rx;
u_int16_t               limit;
u_int16_t               rx_bytes = 0, max_bytes;
ifp = &sc->sc_arpcom.ac_if;
cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
  605         /* Do not try to read past this point. */
limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
  608         if (limit < cur_rx)
max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
  610         else
max_bytes = limit - cur_rx;
  613         while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap,
  615                     0, sc->sc_rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
rxstat = *(u_int32_t *)rxbufpos;
  619                 /*
  620                  * Here's a totally undocumented fact for you. When the
  621                  * RealTek chip is in the process of copying a packet into
  622                  * RAM for you, the length will be 0xfff0. If you spot a
  623                  * packet header with this value, you need to stop. The
  624                  * datasheet makes absolutely no mention of this and
  625                  * RealTek should be shot for this.
  626                  */
rxstat = htole32(rxstat);
total_len = rxstat >> 16;
  629                 if (total_len == RL_RXSTAT_UNFINISHED) {
bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap,
  631                             0, sc->sc_rx_dmamap->dm_mapsize,
BUS_DMASYNC_PREREAD);
  633                         break;
  634                 }
  636                 if (!(rxstat & RL_RXSTAT_RXOK) ||
total_len < ETHER_MIN_LEN ||
total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
ifp->if_ierrors++;
rl_init(sc);
bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap,
  642                             0, sc->sc_rx_dmamap->dm_mapsize,
BUS_DMASYNC_PREREAD);
  644                         return;
  645                 }
  647                 /* No errors; receive the packet. */
rx_bytes += total_len + 4;
  650                 /*
  651                  * XXX The RealTek chip includes the CRC with every
  652                  * received frame, and there's no way to turn this
  653                  * behavior off (at least, I can't find anything in
  654                  * the manual that explains how to do it) so we have
  655                  * to trim off the CRC manually.
  656                  */
total_len -= ETHER_CRC_LEN;
  659                 /*
  660                  * Avoid trying to read more bytes than we know
  661                  * the chip has prepared for us.
  662                  */
  663                 if (rx_bytes > max_bytes) {
bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap,
  665                             0, sc->sc_rx_dmamap->dm_mapsize,
BUS_DMASYNC_PREREAD);
  667                         break;
  668                 }
rxbufpos = sc->rl_cdata.rl_rx_buf +
  671                         ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
  673                 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
rxbufpos = sc->rl_cdata.rl_rx_buf;
wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
  678                 if (total_len > wrap) {
m = m_devget(rxbufpos - ETHER_ALIGN,
wrap + ETHER_ALIGN, 0, ifp, NULL);
  681                         if (m == NULL)
ifp->if_ierrors++;
  683                         else {
m_copyback(m, wrap + ETHER_ALIGN,
total_len - wrap, sc->rl_cdata.rl_rx_buf);
m = m_pullup(m, sizeof(struct ip) +ETHER_ALIGN);
  687                                 if (m == NULL)
ifp->if_ierrors++;
  689                                 else
m_adj(m, ETHER_ALIGN);
  691                         }
cur_rx = (total_len - wrap + ETHER_CRC_LEN);
  693                 } else {
m = m_devget(rxbufpos - ETHER_ALIGN,
total_len + ETHER_ALIGN, 0, ifp, NULL);
  696                         if (m == NULL)
ifp->if_ierrors++;
  698                         else
m_adj(m, ETHER_ALIGN);
cur_rx += total_len + 4 + ETHER_CRC_LEN;
  701                 }
  703                 /*
  704                  * Round up to 32-bit boundary.
  705                  */
cur_rx = (cur_rx + 3) & ~3;
CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
  709                 if (m == NULL) {
bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap,
  711                             0, sc->sc_rx_dmamap->dm_mapsize,
BUS_DMASYNC_PREREAD);
  713                         continue;
  714                 }
ifp->if_ipackets++;
  718 #if NBPFILTER > 0
  719                 /*
  720                  * Handle BPF listeners. Let the BPF user see the packet.
  721                  */
  722                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
  724 #endif
ether_input_mbuf(ifp, m);
bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap,
  728                     0, sc->sc_rx_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
  729         }
  730 }
  732 /*
  733  * A frame was downloaded to the chip. It's safe for us to clean up
  734  * the list buffers.
  735  */
  736 void rl_txeof(sc)
  737         struct rl_softc         *sc;
  738 {
  739         struct ifnet            *ifp;
u_int32_t               txstat;
ifp = &sc->sc_arpcom.ac_if;
  744         /*
  745          * Go through our tx list and free mbufs for those
  746          * frames that have been uploaded.
  747          */
  748         do {
  749                 if (RL_LAST_TXMBUF(sc) == NULL)
  750                         break;
txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
  752                 if (!(txstat & (RL_TXSTAT_TX_OK|
RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
  754                         break;
ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
bus_dmamap_sync(sc->sc_dmat, RL_LAST_TXMAP(sc),
  759                     0, RL_LAST_TXMAP(sc)->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat, RL_LAST_TXMAP(sc));
m_freem(RL_LAST_TXMBUF(sc));
RL_LAST_TXMBUF(sc) = NULL;
  764                 /*
  765                  * If there was a transmit underrun, bump the TX threshold.
  766                  * Make sure not to overflow the 63 * 32byte we can address
  767                  * with the 6 available bit.
  768                  */
  769                 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
  770                     (sc->rl_txthresh < 2016))
sc->rl_txthresh += 32;
  772                 if (txstat & RL_TXSTAT_TX_OK)
ifp->if_opackets++;
  774                 else {
  775                         int oldthresh;
ifp->if_oerrors++;
  778                         if ((txstat & RL_TXSTAT_TXABRT) ||
  779                             (txstat & RL_TXSTAT_OUTOFWIN))
CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
oldthresh = sc->rl_txthresh;
  782                         /* error recovery */
rl_reset(sc);
rl_init(sc);
  785                         /* restore original threshold */
sc->rl_txthresh = oldthresh;
  787                         return;
  788                 }
RL_INC(sc->rl_cdata.last_tx);
ifp->if_flags &= ~IFF_OACTIVE;
  791         } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
  793         if (RL_LAST_TXMBUF(sc) == NULL)
ifp->if_timer = 0;
  795         else if (ifp->if_timer == 0)
ifp->if_timer = 5;
  797 }
  799 int rl_intr(arg)
  800         void                    *arg;
  801 {
  802         struct rl_softc         *sc;
  803         struct ifnet            *ifp;
  804         int                     claimed = 0;
u_int16_t               status;
sc = arg;
ifp = &sc->sc_arpcom.ac_if;
  810         /* Disable interrupts. */
CSR_WRITE_2(sc, RL_IMR, 0x0000);
  813         for (;;) {
status = CSR_READ_2(sc, RL_ISR);
  815                 /* If the card has gone away, the read returns 0xffff. */
  816                 if (status == 0xffff)
  817                         break;
  818                 if (status != 0)
CSR_WRITE_2(sc, RL_ISR, status);
  820                 if ((status & RL_INTRS) == 0)
  821                         break;
  822                 if (status & RL_ISR_RX_OK)
rl_rxeof(sc);
  824                 if (status & RL_ISR_RX_ERR)
rl_rxeof(sc);
  826                 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
rl_txeof(sc);
  828                 if (status & RL_ISR_SYSTEM_ERR) {
rl_reset(sc);
rl_init(sc);
  831                 }
claimed = 1;
  833         }
  835         /* Re-enable interrupts. */
CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
  838         if (!IFQ_IS_EMPTY(&ifp->if_snd))
rl_start(ifp);
  841         return (claimed);
  842 }
  844 /*
  845  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
  846  * pointers to the fragment pointers.
  847  */
  848 int rl_encap(sc, m_head)
  849         struct rl_softc         *sc;
  850         struct mbuf             *m_head;
  851 {
  852         struct mbuf             *m_new;
  854         /*
  855          * The RealTek is brain damaged and wants longword-aligned
  856          * TX buffers, plus we can only have one fragment buffer
  857          * per packet. We have to copy pretty much all the time.
  858          */
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
  860         if (m_new == NULL) {
m_freem(m_head);
  862                 return(1);
  863         }
  864         if (m_head->m_pkthdr.len > MHLEN) {
MCLGET(m_new, M_DONTWAIT);
  866                 if (!(m_new->m_flags & M_EXT)) {
m_freem(m_new);
m_freem(m_head);
  869                         return(1);
  870                 }
  871         }
m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
  875         /* Pad frames to at least 60 bytes. */
  876         if (m_new->m_pkthdr.len < RL_MIN_FRAMELEN) {
  877                 /*
  878                  * Make security-conscious people happy: zero out the
  879                  * bytes in the pad area, since we don't know what
  880                  * this mbuf cluster buffer's previous user might
  881                  * have left in it.
  882                  */
bzero(mtod(m_new, char *) + m_new->m_pkthdr.len,
RL_MIN_FRAMELEN - m_new->m_pkthdr.len);
m_new->m_pkthdr.len +=
  886                     (RL_MIN_FRAMELEN - m_new->m_pkthdr.len);
m_new->m_len = m_new->m_pkthdr.len;
  888         }
  890         if (bus_dmamap_load_mbuf(sc->sc_dmat, RL_CUR_TXMAP(sc),
m_new, BUS_DMA_NOWAIT) != 0) {
m_freem(m_new);
m_freem(m_head);
  894                 return (1);
  895         }
m_freem(m_head);
RL_CUR_TXMBUF(sc) = m_new;
bus_dmamap_sync(sc->sc_dmat, RL_CUR_TXMAP(sc), 0,
RL_CUR_TXMAP(sc)->dm_mapsize, BUS_DMASYNC_PREWRITE);
  901         return(0);
  902 }
  904 /*
  905  * Main transmit routine.
  906  */
  908 void rl_start(ifp)
  909         struct ifnet            *ifp;
  910 {
  911         struct rl_softc         *sc;
  912         struct mbuf             *m_head = NULL;
  913         int                     pkts = 0;
sc = ifp->if_softc;
  917         while(RL_CUR_TXMBUF(sc) == NULL) {
IFQ_DEQUEUE(&ifp->if_snd, m_head);
  919                 if (m_head == NULL)
  920                         break;
  922                 /* Pack the data into the descriptor. */
  923                 if (rl_encap(sc, m_head))
  924                         break;
pkts++;
  927 #if NBPFILTER > 0
  928                 /*
  929                  * If there's a BPF listener, bounce a copy of this frame
  930                  * to him.
  931                  */
  932                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, RL_CUR_TXMBUF(sc),
BPF_DIRECTION_OUT);
  935 #endif
  936                 /*
  937                  * Transmit the frame.
  938                  */
CSR_WRITE_4(sc, RL_CUR_TXADDR(sc),
RL_CUR_TXMAP(sc)->dm_segs[0].ds_addr);
CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
RL_TXTHRESH(sc->rl_txthresh) |
RL_CUR_TXMAP(sc)->dm_segs[0].ds_len);
RL_INC(sc->rl_cdata.cur_tx);
  947                 /*
  948                  * Set a timeout in case the chip goes out to lunch.
  949                  */
ifp->if_timer = 5;
  951         }
  952         if (pkts == 0)
  953                 return;
  955         /*
  956          * We broke out of the loop because all our TX slots are
  957          * full. Mark the NIC as busy until it drains some of the
  958          * packets from the queue.
  959          */
  960         if (RL_CUR_TXMBUF(sc) != NULL)
ifp->if_flags |= IFF_OACTIVE;
  962 }
  964 void rl_init(xsc)
  965         void                    *xsc;
  966 {
  967         struct rl_softc         *sc = xsc;
  968         struct ifnet            *ifp = &sc->sc_arpcom.ac_if;
  969         int                     s;
u_int32_t               rxcfg = 0;
s = splnet();
  974         /*
  975          * Cancel pending I/O and free all RX/TX buffers.
  976          */
rl_stop(sc);
  979         /*
  980          * Init our MAC address.  Even though the chipset
  981          * documentation doesn't mention it, we need to enter "Config
  982          * register write enable" mode to modify the ID registers.
  983          */
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
CSR_WRITE_RAW_4(sc, RL_IDR0,
  986             (u_int8_t *)(&sc->sc_arpcom.ac_enaddr[0]));
CSR_WRITE_RAW_4(sc, RL_IDR4,
  988             (u_int8_t *)(&sc->sc_arpcom.ac_enaddr[4]));
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
  991         /* Init the RX buffer pointer register. */
CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_pa);
  994         /* Init TX descriptors. */
rl_list_tx_init(sc);
  997         /*
  998          * Enable transmit and receive.
  999          */
CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
 1002         /*
 1003          * Set the initial TX and RX configuration.
 1004          */
CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
 1008         /* Set the individual bit to receive frames for this host only. */
rxcfg = CSR_READ_4(sc, RL_RXCFG);
rxcfg |= RL_RXCFG_RX_INDIV;
 1012         /* If we want promiscuous mode, set the allframes bit. */
 1013         if (ifp->if_flags & IFF_PROMISC)
rxcfg |= RL_RXCFG_RX_ALLPHYS;
 1015         else
rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1019         /*
 1020          * Set capture broadcast bit to capture broadcast frames.
 1021          */
 1022         if (ifp->if_flags & IFF_BROADCAST)
rxcfg |= RL_RXCFG_RX_BROAD;
 1024         else
rxcfg &= ~RL_RXCFG_RX_BROAD;
CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
 1028         /*
 1029          * Program the multicast filter, if necessary.
 1030          */
rl_setmulti(sc);
 1033         /*
 1034          * Enable interrupts.
 1035          */
CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
 1038         /* Set initial TX threshold */
sc->rl_txthresh = RL_TX_THRESH_INIT;
 1041         /* Start RX/TX process. */
CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
 1044         /* Enable receiver and transmitter. */
CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
mii_mediachg(&sc->sc_mii);
CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
splx(s);
timeout_set(&sc->sc_tick_tmo, rl_tick, sc);
timeout_add(&sc->sc_tick_tmo, hz);
 1058 }
 1060 /*
 1061  * Set media options.
 1062  */
 1063 int rl_ifmedia_upd(ifp)
 1064         struct ifnet            *ifp;
 1065 {
 1066         struct rl_softc *sc = (struct rl_softc *)ifp->if_softc;
mii_mediachg(&sc->sc_mii);
 1069         return (0);
 1070 }
 1072 /*
 1073  * Report current media status.
 1074  */
 1075 void rl_ifmedia_sts(ifp, ifmr)
 1076         struct ifnet            *ifp;
 1077         struct ifmediareq       *ifmr;
 1078 {
 1079         struct rl_softc *sc = ifp->if_softc;
mii_pollstat(&sc->sc_mii);
ifmr->ifm_status = sc->sc_mii.mii_media_status;
ifmr->ifm_active = sc->sc_mii.mii_media_active;
 1084 }
 1086 int rl_ioctl(ifp, command, data)
 1087         struct ifnet            *ifp;
u_long                  command;
caddr_t                 data;
 1090 {
 1091         struct rl_softc         *sc = ifp->if_softc;
 1092         struct ifreq            *ifr = (struct ifreq *) data;
 1093         struct ifaddr *ifa = (struct ifaddr *)data;
 1094         int                     s, error = 0;
s = splnet();
 1098         if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) {
splx(s);
 1100                 return error;
 1101         }
 1103         switch(command) {
 1104         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
 1106                 switch (ifa->ifa_addr->sa_family) {
 1107 #ifdef INET
 1108                 case AF_INET:
rl_init(sc);
arp_ifinit(&sc->sc_arpcom, ifa);
 1111                         break;
 1112 #endif /* INET */
 1113                 default:
rl_init(sc);
 1115                         break;
 1116                 }
 1117                 break;
 1118         case SIOCSIFMTU:
 1119                 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) {
error = EINVAL;
 1121                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
ifp->if_mtu = ifr->ifr_mtu;
 1123                 }
 1124                 break;
 1125         case SIOCSIFFLAGS:
 1126                 if (ifp->if_flags & IFF_UP) {
rl_init(sc);
 1128                 } else {
 1129                         if (ifp->if_flags & IFF_RUNNING)
rl_stop(sc);
 1131                 }
error = 0;
 1133                 break;
 1134         case SIOCADDMULTI:
 1135         case SIOCDELMULTI:
error = (command == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_arpcom) :
ether_delmulti(ifr, &sc->sc_arpcom);
 1140                 if (error == ENETRESET) {
 1141                         /*
 1142                          * Multicast list has changed; set the hardware
 1143                          * filter accordingly.
 1144                          */
 1145                         if (ifp->if_flags & IFF_RUNNING)
rl_setmulti(sc);
error = 0;
 1148                 }
 1149                 break;
 1150         case SIOCGIFMEDIA:
 1151         case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
 1153                 break;
 1154         default:
error = EINVAL;
 1156                 break;
 1157         }
splx(s);
 1161         return(error);
 1162 }
 1164 void rl_watchdog(ifp)
 1165         struct ifnet            *ifp;
 1166 {
 1167         struct rl_softc         *sc;
sc = ifp->if_softc;
printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
ifp->if_oerrors++;
rl_txeof(sc);
rl_rxeof(sc);
rl_init(sc);
 1176 }
 1178 /*
 1179  * Stop the adapter and free any mbufs allocated to the
 1180  * RX and TX lists.
 1181  */
 1182 void rl_stop(sc)
 1183         struct rl_softc         *sc;
 1184 {
 1185         register int            i;
 1186         struct ifnet            *ifp;
ifp = &sc->sc_arpcom.ac_if;
ifp->if_timer = 0;
timeout_del(&sc->sc_tick_tmo);
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
CSR_WRITE_1(sc, RL_COMMAND, 0x00);
CSR_WRITE_2(sc, RL_IMR, 0x0000);
 1198         /*
 1199          * Free the TX list buffers.
 1200          */
 1201         for (i = 0; i < RL_TX_LIST_CNT; i++) {
 1202                 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
bus_dmamap_sync(sc->sc_dmat,
sc->rl_cdata.rl_tx_dmamap[i], 0,
sc->rl_cdata.rl_tx_dmamap[i]->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat,
sc->rl_cdata.rl_tx_dmamap[i]);
m_freem(sc->rl_cdata.rl_tx_chain[i]);
sc->rl_cdata.rl_tx_chain[i] = NULL;
CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(u_int32_t)),
 1212                                 0x00000000);
 1213                 }
 1214         }
 1215 }
 1217 int
rl_attach(sc)
 1219         struct rl_softc *sc;
 1220 {
 1221         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
 1222         int rseg, i;
u_int16_t rl_id, rl_did;
caddr_t kva;
 1225         int addr_len;
rl_reset(sc);
 1229         /*
 1230          * Check EEPROM type 9346 or 9356.
 1231          */
rl_read_eeprom(sc, (caddr_t)&rl_id, RL_EE_ID, RL_EEADDR_LEN1, 1, 0);
 1233         if (rl_id == 0x8129)
addr_len = RL_EEADDR_LEN1;
 1235         else
addr_len = RL_EEADDR_LEN0;
 1238         /*
 1239          * Get station address.
 1240          */
rl_read_eeprom(sc, (caddr_t)sc->sc_arpcom.ac_enaddr, RL_EE_EADDR,
addr_len, 3, 1);
printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, addr_len, 1, 0);
 1248         if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
rl_did == DLINK_DEVICEID_8139 || rl_did == DLINK_DEVICEID_8139_2 ||
rl_did == ABOCOM_DEVICEID_8139)
sc->rl_type = RL_8139;
 1253         else if (rl_did == RT_DEVICEID_8129)
sc->rl_type = RL_8129;
 1255         else
sc->rl_type = RL_UNKNOWN;       /* could be 8138 or other */
 1258         if (bus_dmamem_alloc(sc->sc_dmat, RL_RXBUFLEN + 32, PAGE_SIZE, 0,
 1259             &sc->sc_rx_seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf("\n%s: can't alloc rx buffers\n", sc->sc_dev.dv_xname);
 1261                 return (1);
 1262         }
 1263         if (bus_dmamem_map(sc->sc_dmat, &sc->sc_rx_seg, rseg,
RL_RXBUFLEN + 32, &kva, BUS_DMA_NOWAIT)) {
printf("%s: can't map dma buffers (%d bytes)\n",
sc->sc_dev.dv_xname, RL_RXBUFLEN + 32);
bus_dmamem_free(sc->sc_dmat, &sc->sc_rx_seg, rseg);
 1268                 return (1);
 1269         }
 1270         if (bus_dmamap_create(sc->sc_dmat, RL_RXBUFLEN + 32, 1,
RL_RXBUFLEN + 32, 0, BUS_DMA_NOWAIT, &sc->sc_rx_dmamap)) {
printf("%s: can't create dma map\n", sc->sc_dev.dv_xname);
bus_dmamem_unmap(sc->sc_dmat, kva, RL_RXBUFLEN + 32);
bus_dmamem_free(sc->sc_dmat, &sc->sc_rx_seg, rseg);
 1275                 return (1);
 1276         }
 1277         if (bus_dmamap_load(sc->sc_dmat, sc->sc_rx_dmamap, kva,
RL_RXBUFLEN + 32, NULL, BUS_DMA_NOWAIT)) {
printf("%s: can't load dma map\n", sc->sc_dev.dv_xname);
bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamap);
bus_dmamem_unmap(sc->sc_dmat, kva, RL_RXBUFLEN + 32);
bus_dmamem_free(sc->sc_dmat, &sc->sc_rx_seg, rseg);
 1283                 return (1);
 1284         }
sc->rl_cdata.rl_rx_buf = kva;
sc->rl_cdata.rl_rx_buf_pa = sc->sc_rx_dmamap->dm_segs[0].ds_addr;
bzero(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32);
bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dmamap,
 1291             0, sc->sc_rx_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 1293         for (i = 0; i < RL_TX_LIST_CNT; i++) {
 1294                 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
BUS_DMA_NOWAIT, &sc->rl_cdata.rl_tx_dmamap[i]) != 0) {
printf("%s: can't create tx maps\n",
sc->sc_dev.dv_xname);
 1298                         /* XXX free any allocated... */
 1299                         return (1);
 1300                 }
 1301         }
 1303         /* Leave a few bytes before the start of the RX ring buffer. */
sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
sc->rl_cdata.rl_rx_buf_pa += sizeof(u_int64_t);
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = rl_ioctl;
ifp->if_start = rl_start;
ifp->if_watchdog = rl_watchdog;
ifp->if_baudrate = 10000000;
IFQ_SET_READY(&ifp->if_snd);
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
ifp->if_capabilities = IFCAP_VLAN_MTU;
 1320         /*
 1321          * Initialize our media structures and probe the MII.
 1322          */
sc->sc_mii.mii_ifp = ifp;
sc->sc_mii.mii_readreg = rl_miibus_readreg;
sc->sc_mii.mii_writereg = rl_miibus_writereg;
sc->sc_mii.mii_statchg = rl_miibus_statchg;
ifmedia_init(&sc->sc_mii.mii_media, 0, rl_ifmedia_upd, rl_ifmedia_sts);
mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, 0);
 1330         if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
 1333         } else
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
 1336         /*
 1337          * Attach us everywhere
 1338          */
if_attach(ifp);
ether_ifattach(ifp);
sc->sc_sdhook = shutdownhook_establish(rl_shutdown, sc);
sc->sc_pwrhook = powerhook_establish(rl_powerhook, sc);
 1345         return (0);
 1346 }
 1348 void
rl_shutdown(arg)
 1350         void                    *arg;
 1351 {
 1352         struct rl_softc         *sc = (struct rl_softc *)arg;
rl_stop(sc);
 1355 }
 1357 void
rl_powerhook(why, arg)
 1359         int why;
 1360         void *arg;
 1361 {
 1362         if (why == PWR_RESUME)
rl_init(arg);
 1364 }
 1366 int
rl_miibus_readreg(self, phy, reg)
 1368         struct device *self;
 1369         int phy, reg;
 1370 {
 1371         struct rl_softc *sc = (struct rl_softc *)self;
 1372         struct rl_mii_frame frame;
u_int16_t rl8139_reg;
 1375         if (sc->rl_type == RL_8139) {
 1376                 /*
 1377                 * The RTL8139 PHY is mapped into PCI registers, unfortunately
 1378                 * it has no phyid, or phyaddr, so assume it is phyaddr 0.
 1379                 */
 1380                 if (phy != 0)
 1381                         return(0);
 1383                 switch (reg) {
 1384                 case MII_BMCR:
rl8139_reg = RL_BMCR;
 1386                         break;
 1387                 case MII_BMSR:
rl8139_reg = RL_BMSR;
 1389                         break;
 1390                 case MII_ANAR:
rl8139_reg = RL_ANAR;
 1392                         break;
 1393                 case MII_ANER:
rl8139_reg = RL_ANER;
 1395                         break;
 1396                 case MII_ANLPAR:
rl8139_reg = RL_LPAR;
 1398                         break;
 1399                 case RL_MEDIASTAT:
 1400                         return (CSR_READ_1(sc, RL_MEDIASTAT));
 1401                 case MII_PHYIDR1:
 1402                 case MII_PHYIDR2:
 1403                 default:
 1404                         return (0);
 1405                 }
 1406                 return (CSR_READ_2(sc, rl8139_reg));
 1407         }
bzero((char *)&frame, sizeof(frame));
frame.mii_phyaddr = phy;
frame.mii_regaddr = reg;
rl_mii_readreg(sc, &frame);
 1415         return(frame.mii_data);
 1416 }
 1418 void
rl_miibus_writereg(self, phy, reg, val)
 1420         struct device *self;
 1421         int phy, reg, val;
 1422 {
 1423         struct rl_softc *sc = (struct rl_softc *)self;
 1424         struct rl_mii_frame frame;
u_int16_t rl8139_reg = 0;
 1427         if (sc->rl_type == RL_8139) {
 1428                 if (phy)
 1429                         return;
 1431                 switch (reg) {
 1432                 case MII_BMCR:
rl8139_reg = RL_BMCR;
 1434                         break;
 1435                 case MII_BMSR:
rl8139_reg = RL_BMSR;
 1437                         break;
 1438                 case MII_ANAR:
rl8139_reg = RL_ANAR;
 1440                         break;
 1441                 case MII_ANER:
rl8139_reg = RL_ANER;
 1443                         break;
 1444                 case MII_ANLPAR:
rl8139_reg = RL_LPAR;
 1446                         break;
 1447                 case MII_PHYIDR1:
 1448                 case MII_PHYIDR2:
 1449                         return;
 1450                 }
CSR_WRITE_2(sc, rl8139_reg, val);
 1452                 return;
 1453         }
bzero((char *)&frame, sizeof(frame));
frame.mii_phyaddr = phy;
frame.mii_regaddr = reg;
frame.mii_data = val;
rl_mii_writereg(sc, &frame);
 1460 }
 1462 void
rl_miibus_statchg(self)
 1464         struct device *self;
 1465 {
 1466 }
 1468 void
rl_tick(v)
 1470         void *v;
 1471 {
 1472         struct rl_softc *sc = v;
mii_tick(&sc->sc_mii);
timeout_add(&sc->sc_tick_tmo, hz);
 1476 }
 1478 struct cfdriver rl_cd = {
 1479         0, "rl", DV_IFNET
 1480 };