root/dev/pci/if_iwireg.h

INCLUDED FROM

    1 /*      $OpenBSD: if_iwireg.h,v 1.25 2006/08/19 11:07:45 damien Exp $   */
    3 /*-
    4  * Copyright (c) 2004-2006
    5  *      Damien Bergamini <damien.bergamini@free.fr>. All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice unmodified, this list of conditions, and the following
   12  *    disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  */
   30 #define IWI_CMD_RING_COUNT      16
   31 #define IWI_TX_RING_COUNT       64
   32 #define IWI_RX_RING_COUNT       32
   34 #define IWI_CSR_INTR            0x0008
   35 #define IWI_CSR_INTR_MASK       0x000c
   36 #define IWI_CSR_INDIRECT_ADDR   0x0010
   37 #define IWI_CSR_INDIRECT_DATA   0x0014
   38 #define IWI_CSR_AUTOINC_ADDR    0x0018
   39 #define IWI_CSR_AUTOINC_DATA    0x001c
   40 #define IWI_CSR_RST             0x0020
   41 #define IWI_CSR_CTL             0x0024
   42 #define IWI_CSR_IO              0x0030
   43 #define IWI_CSR_CMD_BASE        0x0200
   44 #define IWI_CSR_CMD_SIZE        0x0204
   45 #define IWI_CSR_TX1_BASE        0x0208
   46 #define IWI_CSR_TX1_SIZE        0x020c
   47 #define IWI_CSR_TX2_BASE        0x0210
   48 #define IWI_CSR_TX2_SIZE        0x0214
   49 #define IWI_CSR_TX3_BASE        0x0218
   50 #define IWI_CSR_TX3_SIZE        0x021c
   51 #define IWI_CSR_TX4_BASE        0x0220
   52 #define IWI_CSR_TX4_SIZE        0x0224
   53 #define IWI_CSR_CMD_RIDX        0x0280
   54 #define IWI_CSR_TX1_RIDX        0x0284
   55 #define IWI_CSR_TX2_RIDX        0x0288
   56 #define IWI_CSR_TX3_RIDX        0x028c
   57 #define IWI_CSR_TX4_RIDX        0x0290
   58 #define IWI_CSR_RX_RIDX         0x02a0
   59 #define IWI_CSR_RX_BASE         0x0500
   60 #define IWI_CSR_TABLE0_SIZE     0x0700
   61 #define IWI_CSR_TABLE0_BASE     0x0704
   62 #define IWI_CSR_NODE_BASE       0x0c0c
   63 #define IWI_CSR_CMD_WIDX        0x0f80
   64 #define IWI_CSR_TX1_WIDX        0x0f84
   65 #define IWI_CSR_TX2_WIDX        0x0f88
   66 #define IWI_CSR_TX3_WIDX        0x0f8c
   67 #define IWI_CSR_TX4_WIDX        0x0f90
   68 #define IWI_CSR_RX_WIDX         0x0fa0
   69 #define IWI_CSR_READ_INT        0x0ff4
   71 /* aliases */
   72 #define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE
   74 /* possible flags for IWI_CSR_INTR */
   75 #define IWI_INTR_RX_DONE        0x00000002
   76 #define IWI_INTR_CMD_DONE       0x00000800
   77 #define IWI_INTR_TX1_DONE       0x00001000
   78 #define IWI_INTR_TX2_DONE       0x00002000
   79 #define IWI_INTR_TX3_DONE       0x00004000
   80 #define IWI_INTR_TX4_DONE       0x00008000
   81 #define IWI_INTR_FW_INITED      0x01000000
   82 #define IWI_INTR_RADIO_OFF      0x04000000
   83 #define IWI_INTR_FATAL_ERROR    0x40000000
   84 #define IWI_INTR_PARITY_ERROR   0x80000000
   86 #define IWI_INTR_MASK                                                   \
   87         (IWI_INTR_RX_DONE | IWI_INTR_CMD_DONE | IWI_INTR_TX1_DONE |     \
IWI_INTR_TX2_DONE | IWI_INTR_TX3_DONE | IWI_INTR_TX4_DONE |    \
IWI_INTR_FW_INITED | IWI_INTR_RADIO_OFF |                      \
IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR)
   92 /* possible flags for register IWI_CSR_RST */
   93 #define IWI_RST_PRINCETON_RESET 0x00000001
   94 #define IWI_RST_SW_RESET        0x00000080
   95 #define IWI_RST_MASTER_DISABLED 0x00000100
   96 #define IWI_RST_STOP_MASTER     0x00000200
   98 /* possible flags for register IWI_CSR_CTL */
   99 #define IWI_CTL_CLOCK_READY     0x00000001
  100 #define IWI_CTL_ALLOW_STANDBY   0x00000002
  101 #define IWI_CTL_INIT            0x00000004
  103 /* possible flags for register IWI_CSR_IO */
  104 #define IWI_IO_RADIO_ENABLED    0x00010000
  106 /* possible flags for IWI_CSR_READ_INT */
  107 #define IWI_READ_INT_INIT_HOST  0x20000000
  109 /* constants for command blocks */
  110 #define IWI_CB_DEFAULT_CTL      0x8cea0000
  111 #define IWI_CB_MAXDATALEN       8191
  113 /* firmware binary image header */
  114 struct iwi_firmware_hdr {
uint8_t         oldvermaj;
uint8_t         oldvermin;
uint8_t         vermaj;
uint8_t         vermin;
uint32_t        bootsz;
uint32_t        ucodesz;
uint32_t        mainsz;
  122 } __packed;
  124 struct iwi_hdr {
uint8_t type;
  126 #define IWI_HDR_TYPE_DATA       0
  127 #define IWI_HDR_TYPE_COMMAND    1
  128 #define IWI_HDR_TYPE_NOTIF      3
  129 #define IWI_HDR_TYPE_FRAME      9
uint8_t seq;
uint8_t flags;
  133 #define IWI_HDR_FLAG_IRQ        0x04
uint8_t reserved;
  136 } __packed;
  138 struct iwi_notif {
uint32_t        reserved[2];
uint8_t         type;
  141 #define IWI_NOTIF_TYPE_ASSOCIATION      10
  142 #define IWI_NOTIF_TYPE_AUTHENTICATION   11
  143 #define IWI_NOTIF_TYPE_SCAN_CHANNEL     12
  144 #define IWI_NOTIF_TYPE_SCAN_COMPLETE    13
  145 #define IWI_NOTIF_TYPE_BAD_LINK         15
  146 #define IWI_NOTIF_TYPE_BEACON           17
  147 #define IWI_NOTIF_TYPE_CALIBRATION      20
  148 #define IWI_NOTIF_TYPE_NOISE            25
uint8_t         flags;
uint16_t        len;
  152 } __packed;
  154 /* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */
  155 struct iwi_notif_authentication {
uint8_t state;
  157 #define IWI_DEAUTHENTICATED     0
  158 #define IWI_AUTHENTICATED       9
  159 } __packed;
  161 /* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */
  162 struct iwi_notif_association {
uint8_t                 state;
  164 #define IWI_DEASSOCIATED        0
  165 #define IWI_ASSOCIATED          12
  167         struct ieee80211_frame  frame;
uint16_t                capinfo;
uint16_t                status;
uint16_t                associd;
  171 } __packed;
  173 /* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */
  174 struct iwi_notif_scan_channel {
uint8_t nchan;
uint8_t reserved[47];
  177 } __packed;
  179 /* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */
  180 struct iwi_notif_scan_complete {
uint8_t type;
uint8_t nchan;
uint8_t status;
uint8_t reserved;
  185 } __packed;
  187 /* structure for notification IWI_NOTIF_TYPE_BEACON */
  188 struct iwi_notif_beacon {
uint32_t        status;
  190 #define IWI_BEACON_MISSED       1
uint32_t        count;
  193 };
  195 /* received frame header */
  196 struct iwi_frame {
uint32_t        reserved1[2];
uint8_t         chan;
uint8_t         status;
uint8_t         rate;
uint8_t         rssi;   /* receiver signal strength indicator */
uint8_t         agc;    /* automatic gain control */
uint8_t         rssi_dbm;
uint16_t        signal;
uint16_t        noise;
uint8_t         antenna;
uint8_t         control;
uint8_t         reserved2[2];
uint16_t        len;
  210 } __packed;
  212 /* header for transmission */
  213 struct iwi_tx_desc {
  214         struct iwi_hdr  hdr;
uint32_t        reserved1;
uint8_t         station;
uint8_t         reserved2[3];
uint8_t         cmd;
  219 #define IWI_DATA_CMD_TX 0x0b
uint8_t         seq;
uint16_t        len;
uint8_t         priority;
uint8_t         flags;
  225 #define IWI_DATA_FLAG_SHPREAMBLE        (1 << 2)
  226 #define IWI_DATA_FLAG_NO_WEP            (1 << 5)
  227 #define IWI_DATA_FLAG_NEED_ACK          (1 << 7)
uint8_t         xflags;
  230 #define IWI_DATA_XFLAG_CCK      (1 << 0)
uint8_t         wep_txkey;
  233 #define IWI_DATA_KEY_WEP40      (1 << 6)
  234 #define IWI_DATA_KEY_WEP104     (1 << 7)
uint8_t         wepkey[IEEE80211_KEYBUF_SIZE];
uint8_t         rate;
uint8_t         antenna;
uint8_t         reserved3[10];
  241         struct ieee80211_qosframe_addr4 wh;
uint32_t        iv[2];
uint32_t        nseg;
  245 #define IWI_MAX_NSEG    6
  246 #define IWI_MAX_SCATTER (IWI_MAX_NSEG - 2)
uint32_t        seg_addr[IWI_MAX_NSEG];
uint16_t        seg_len[IWI_MAX_NSEG];
  250 } __packed;
  252 /* command */
  253 struct iwi_cmd_desc {
  254         struct iwi_hdr  hdr;
uint8_t         type;
  256 #define IWI_CMD_ENABLE                  2
  257 #define IWI_CMD_SET_CONFIG              6
  258 #define IWI_CMD_SET_ESSID               8
  259 #define IWI_CMD_SET_MAC_ADDRESS         11
  260 #define IWI_CMD_SET_RTS_THRESHOLD       15
  261 #define IWI_CMD_SET_FRAG_THRESHOLD      16
  262 #define IWI_CMD_SET_POWER_MODE          17
  263 #define IWI_CMD_SET_WEP_KEY             18
  264 #define IWI_CMD_ASSOCIATE               21
  265 #define IWI_CMD_SET_RATES               22
  266 #define IWI_CMD_SCAN                    26
  267 #define IWI_CMD_DISABLE                 33
  268 #define IWI_CMD_SET_IV                  34
  269 #define IWI_CMD_SET_TX_POWER            35
  270 #define IWI_CMD_SET_SENSITIVITY         42
uint8_t         len;
uint16_t        reserved;
uint8_t         data[120];
  275 } __packed;
  277 /* node information (IBSS) */
  278 struct iwi_node {
uint8_t bssid[IEEE80211_ADDR_LEN];
uint8_t reserved[2];
  281 } __packed;
  283 /* constants for 'mode' fields */
  284 #define IWI_MODE_11A    0
  285 #define IWI_MODE_11B    1
  286 #define IWI_MODE_11G    2
  288 /* possible values for command IWI_CMD_SET_POWER_MODE */
  289 #define IWI_POWER_MODE_CAM      0
  291 /* structure for command IWI_CMD_SET_RATES */
  292 struct iwi_rateset {
uint8_t mode;
uint8_t nrates;
uint8_t type;
  296 #define IWI_RATESET_TYPE_NEGOTIATED     0
  297 #define IWI_RATESET_TYPE_SUPPORTED      1
uint8_t reserved;
uint8_t rates[12];
  301 } __packed;
  303 /* structure for command IWI_CMD_SET_TX_POWER */
  304 struct iwi_txpower {
uint8_t nchan;
uint8_t mode;
  307         struct {
uint8_t chan;
uint8_t power;
  310 #define IWI_TXPOWER_MAX         20
  311 #define IWI_TXPOWER_RATIO       (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX)
  312         } __packed chan[37];
  313 } __packed;
  315 /* structure for command IWI_CMD_ASSOCIATE */
  316 struct iwi_associate {
uint8_t         chan;
uint8_t         auth;
  319 #define IWI_AUTH_OPEN   0
  320 #define IWI_AUTH_SHARED 1
  321 #define IWI_AUTH_NONE   3
uint8_t         type;
  324 #define IWI_ASSOC_ASSOCIATE     0
  325 #define IWI_ASSOC_REASSOCIATE   1
  326 #define IWI_ASSOC_DISASSOCIATE  2
  327 #define IWI_ASSOC_SIBSS         3
uint8_t         reserved1;
uint16_t        reserved2;
uint8_t         plen;
  332 #define IWI_ASSOC_SHPREAMBLE    (1 << 2)
uint8_t         mode;
uint8_t         bssid[IEEE80211_ADDR_LEN];
uint8_t         tstamp[8];
uint16_t        capinfo;
uint16_t        lintval;
uint16_t        intval;
uint8_t         dst[IEEE80211_ADDR_LEN];
uint32_t        reserved3;
uint16_t        reserved4;
  343 } __packed;
  345 /* structure for command IWI_CMD_SCAN */
  346 struct iwi_scan {
uint32_t        index;
uint8_t         channels[54];
  349 #define IWI_CHAN_5GHZ   (0 << 6)
  350 #define IWI_CHAN_2GHZ   (1 << 6)
uint8_t         type[27];
  353 #define IWI_SCAN_TYPE_PASSIVE   0x11
  354 #define IWI_SCAN_TYPE_DIRECTED  0x22
  355 #define IWI_SCAN_TYPE_BROADCAST 0x33
  356 #define IWI_SCAN_TYPE_BDIRECTED 0x44
uint8_t         reserved1;
uint16_t        reserved2;
uint16_t        passive;        /* dwell time */
uint16_t        directed;       /* dwell time */
uint16_t        broadcast;      /* dwell time */
uint16_t        bdirected;      /* dwell time */
  364 } __packed;
  366 /* structure for command IWI_CMD_SET_CONFIGURATION */
  367 struct iwi_configuration {
uint8_t bluetooth_coexistence;
uint8_t reserved1;
uint8_t answer_pbreq;
uint8_t allow_invalid_frames;
uint8_t multicast_enabled;
uint8_t exclude_unicast_unencrypted;
uint8_t disable_unicast_decryption;
uint8_t exclude_multicast_unencrypted;
uint8_t disable_multicast_decryption;
uint8_t antenna;
uint8_t reserved2;
uint8_t bg_autodetection;
uint8_t reserved3;
uint8_t enable_multicast_filtering;
uint8_t bluetooth_threshold;
uint8_t silence_threshold;
uint8_t allow_beacon_and_probe_resp;
uint8_t allow_mgt;
uint8_t report_noise;
uint8_t reserved5;
  388 } __packed;
  390 /* structure for command IWI_CMD_SET_WEP_KEY */
  391 struct iwi_wep_key {
uint8_t cmd;
  393 #define IWI_WEP_KEY_CMD_SETKEY  0x08
uint8_t seq;
uint8_t idx;
uint8_t len;
uint8_t key[IEEE80211_KEYBUF_SIZE];
  399 } __packed;
  401 #define IWI_MEM_EEPROM_CTL      0x00300040
  402 #define IWI_MEM_EVENT_CTL       0x00300004
  404 /* possible flags for register IWI_MEM_EVENT */
  405 #define IWI_LED_ASSOC   (1 << 5)
  406 #define IWI_LED_MASK    0xd9fffffb
  408 /* EEPROM = Electrically Erasable Programmable Read-Only Memory */
  410 #define IWI_EEPROM_MAC  0x21
  412 #define IWI_EEPROM_DELAY        1       /* minimum hold time (microsecond) */
  414 #define IWI_EEPROM_C    (1 << 0)        /* Serial Clock */
  415 #define IWI_EEPROM_S    (1 << 1)        /* Chip Select */
  416 #define IWI_EEPROM_D    (1 << 2)        /* Serial data input */
  417 #define IWI_EEPROM_Q    (1 << 4)        /* Serial data output */
  419 #define IWI_EEPROM_SHIFT_D      2
  420 #define IWI_EEPROM_SHIFT_Q      4
  422 /*
  423  * control and status registers access macros
  424  */
  425 #define CSR_READ_1(sc, reg)                                             \
bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
  428 #define CSR_READ_2(sc, reg)                                             \
bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
  431 #define CSR_READ_4(sc, reg)                                             \
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
  434 #define CSR_READ_REGION_4(sc, offset, datap, count)                     \
bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset),     \
  436             (datap), (count))
  438 #define CSR_WRITE_1(sc, reg, val)                                       \
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
  441 #define CSR_WRITE_2(sc, reg, val)                                       \
bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
  444 #define CSR_WRITE_4(sc, reg, val)                                       \
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
  447 #define CSR_WRITE_REGION_1(sc, offset, datap, count)                    \
bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset),    \
  449             (datap), (count))
  450 /*
  451  * indirect memory space access macros
  452  */
  453 #define MEM_WRITE_1(sc, addr, val) do {                                 \
CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr));               \
CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val));                \
  456 } while (/* CONSTCOND */0)
  458 #define MEM_WRITE_2(sc, addr, val) do {                                 \
CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr));               \
CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val));                \
  461 } while (/* CONSTCOND */0)
  463 #define MEM_WRITE_4(sc, addr, val) do {                                 \
CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr));               \
CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val));                \
  466 } while (/* CONSTCOND */0)
  468 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do {                      \
CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr));               \
CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len));   \
  471 } while (/* CONSTCOND */0)
  473 /*
  474  * EEPROM access macro
  475  */
  476 #define IWI_EEPROM_CTL(sc, val) do {                                    \
MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val));                   \
DELAY(IWI_EEPROM_DELAY);                                        \
  479 } while (/* CONSTCOND */0)