root/dev/pci/if_vr.c

DEFINITIONS

1. vr_mii_sync
2. vr_mii_send
3. vr_mii_readreg
4. vr_mii_writereg
5. vr_miibus_readreg
6. vr_miibus_writereg
7. vr_miibus_statchg
8. vr_setmulti
9. vr_setcfg
10. vr_reset
11. vr_probe
12. vr_attach
13. vr_list_tx_init
14. vr_list_rx_init
15. vr_rxeof
16. vr_rxeoc
17. vr_txeof
18. vr_tick
19. vr_intr
20. vr_encap
21. vr_start
22. vr_init
23. vr_ifmedia_upd
24. vr_ifmedia_sts
25. vr_ioctl
26. vr_watchdog
27. vr_stop
28. vr_shutdown

    1 /*      $OpenBSD: if_vr.c,v 1.67 2006/11/03 23:45:26 brad Exp $ */
    3 /*
    4  * Copyright (c) 1997, 1998
    5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  *
   34  * $FreeBSD: src/sys/pci/if_vr.c,v 1.73 2003/08/22 07:13:22 imp Exp $
   35  */
   37 /*
   38  * VIA Rhine fast ethernet PCI NIC driver
   39  *
   40  * Supports various network adapters based on the VIA Rhine
   41  * and Rhine II PCI controllers, including the D-Link DFE530TX.
   42  * Datasheets are available at http://www.via.com.tw.
   43  *
   44  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   45  * Electrical Engineering Department
   46  * Columbia University, New York City
   47  */
   49 /*
   50  * The VIA Rhine controllers are similar in some respects to the
   51  * the DEC tulip chips, except less complicated. The controller
   52  * uses an MII bus and an external physical layer interface. The
   53  * receiver has a one entry perfect filter and a 64-bit hash table
   54  * multicast filter. Transmit and receive descriptors are similar
   55  * to the tulip.
   56  *
   57  * The Rhine has a serious flaw in its transmit DMA mechanism:
   58  * transmit buffers must be longword aligned. Unfortunately,
   59  * FreeBSD doesn't guarantee that mbufs will be filled in starting
   60  * at longword boundaries, so we have to do a buffer copy before
   61  * transmission.
   62  */
   64 #include "bpfilter.h"
   66 #include <sys/param.h>
   67 #include <sys/systm.h>
   68 #include <sys/sockio.h>
   69 #include <sys/mbuf.h>
   70 #include <sys/malloc.h>
   71 #include <sys/kernel.h>
   72 #include <sys/timeout.h>
   73 #include <sys/socket.h>
   75 #include <net/if.h>
   76 #include <sys/device.h>
   77 #ifdef INET
   78 #include <netinet/in.h>
   79 #include <netinet/in_systm.h>
   80 #include <netinet/in_var.h>
   81 #include <netinet/ip.h>
   82 #include <netinet/if_ether.h>
   83 #endif  /* INET */
   84 #include <net/if_dl.h>
   85 #include <net/if_media.h>
   87 #if NBPFILTER > 0
   88 #include <net/bpf.h>
   89 #endif
   91 #include <machine/bus.h>
   93 #include <dev/mii/mii.h>
   94 #include <dev/mii/miivar.h>
   96 #include <dev/pci/pcireg.h>
   97 #include <dev/pci/pcivar.h>
   98 #include <dev/pci/pcidevs.h>
  100 #define VR_USEIOSPACE
  101 #undef VR_USESWSHIFT
  103 #include <dev/pci/if_vrreg.h>
  105 int vr_probe(struct device *, void *, void *);
  106 void vr_attach(struct device *, struct device *, void *);
  108 struct cfattach vr_ca = {
  109         sizeof(struct vr_softc), vr_probe, vr_attach
  110 };
  111 struct cfdriver vr_cd = {
  112         0, "vr", DV_IFNET
  113 };
  115 int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf *);
  116 void vr_rxeof(struct vr_softc *);
  117 void vr_rxeoc(struct vr_softc *);
  118 void vr_txeof(struct vr_softc *);
  119 void vr_tick(void *);
  120 int vr_intr(void *);
  121 void vr_start(struct ifnet *);
  122 int vr_ioctl(struct ifnet *, u_long, caddr_t);
  123 void vr_init(void *);
  124 void vr_stop(struct vr_softc *);
  125 void vr_watchdog(struct ifnet *);
  126 void vr_shutdown(void *);
  127 int vr_ifmedia_upd(struct ifnet *);
  128 void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  130 void vr_mii_sync(struct vr_softc *);
  131 void vr_mii_send(struct vr_softc *, u_int32_t, int);
  132 int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *);
  133 int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *);
  134 int vr_miibus_readreg(struct device *, int, int);
  135 void vr_miibus_writereg(struct device *, int, int, int);
  136 void vr_miibus_statchg(struct device *);
  138 void vr_setcfg(struct vr_softc *, int);
  139 void vr_setmulti(struct vr_softc *);
  140 void vr_reset(struct vr_softc *);
  141 int vr_list_rx_init(struct vr_softc *);
  142 int vr_list_tx_init(struct vr_softc *);
  144 const struct pci_matchid vr_devices[] = {
  145         { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_RHINE },
  146         { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_RHINEII },
  147         { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_RHINEII_2 },
  148         { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105 },
  149         { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105M },
  150         { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_RHINEII },
  151         { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_RHINEII }
  152 };
  154 #define VR_SETBIT(sc, reg, x)                           \
CSR_WRITE_1(sc, reg,                            \
CSR_READ_1(sc, reg) | (x))
  158 #define VR_CLRBIT(sc, reg, x)                           \
CSR_WRITE_1(sc, reg,                            \
CSR_READ_1(sc, reg) & ~(x))
  162 #define VR_SETBIT16(sc, reg, x)                         \
CSR_WRITE_2(sc, reg,                            \
CSR_READ_2(sc, reg) | (x))
  166 #define VR_CLRBIT16(sc, reg, x)                         \
CSR_WRITE_2(sc, reg,                            \
CSR_READ_2(sc, reg) & ~(x))
  170 #define VR_SETBIT32(sc, reg, x)                         \
CSR_WRITE_4(sc, reg,                            \
CSR_READ_4(sc, reg) | (x))
  174 #define VR_CLRBIT32(sc, reg, x)                         \
CSR_WRITE_4(sc, reg,                            \
CSR_READ_4(sc, reg) & ~(x))
  178 #define SIO_SET(x)                                      \
CSR_WRITE_1(sc, VR_MIICMD,                      \
CSR_READ_1(sc, VR_MIICMD) | (x))
  182 #define SIO_CLR(x)                                      \
CSR_WRITE_1(sc, VR_MIICMD,                      \
CSR_READ_1(sc, VR_MIICMD) & ~(x))
  186 #ifdef VR_USESWSHIFT
  187 /*
  188  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  189  */
  190 void
vr_mii_sync(struct vr_softc *sc)
  192 {
  193         int                     i;
SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
  197         for (i = 0; i < 32; i++) {
SIO_SET(VR_MIICMD_CLK);
DELAY(1);
SIO_CLR(VR_MIICMD_CLK);
DELAY(1);
  202         }
  203 }
  205 /*
  206  * Clock a series of bits through the MII.
  207  */
  208 void
vr_mii_send(struct vr_softc *sc, u_int32_t bits, int cnt)
  210 {
  211         int                     i;
SIO_CLR(VR_MIICMD_CLK);
  215         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  216                 if (bits & i) {
SIO_SET(VR_MIICMD_DATAIN);
  218                 } else {
SIO_CLR(VR_MIICMD_DATAIN);
  220                 }
DELAY(1);
SIO_CLR(VR_MIICMD_CLK);
DELAY(1);
SIO_SET(VR_MIICMD_CLK);
  225         }
  226 }
  227 #endif
  229 /*
  230  * Read an PHY register through the MII.
  231  */
  232 int
vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame)
  234 #ifdef VR_USESWSHIFT
  235 {
  236         int                     i, ack, s;
s = splnet();
  240         /*
  241          * Set up frame for RX.
  242          */
frame->mii_stdelim = VR_MII_STARTDELIM;
frame->mii_opcode = VR_MII_READOP;
frame->mii_turnaround = 0;
frame->mii_data = 0;
CSR_WRITE_1(sc, VR_MIICMD, 0);
VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
  251         /*
  252          * Turn on data xmit.
  253          */
SIO_SET(VR_MIICMD_DIR);
vr_mii_sync(sc);
  258         /*
  259          * Send command/address info.
  260          */
vr_mii_send(sc, frame->mii_stdelim, 2);
vr_mii_send(sc, frame->mii_opcode, 2);
vr_mii_send(sc, frame->mii_phyaddr, 5);
vr_mii_send(sc, frame->mii_regaddr, 5);
  266         /* Idle bit */
SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
DELAY(1);
SIO_SET(VR_MIICMD_CLK);
DELAY(1);
  272         /* Turn off xmit. */
SIO_CLR(VR_MIICMD_DIR);
  275         /* Check for ack */
SIO_CLR(VR_MIICMD_CLK);
DELAY(1);
ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
SIO_SET(VR_MIICMD_CLK);
DELAY(1);
  282         /*
  283          * Now try reading data bits. If the ack failed, we still
  284          * need to clock through 16 cycles to keep the PHY(s) in sync.
  285          */
  286         if (ack) {
  287                 for(i = 0; i < 16; i++) {
SIO_CLR(VR_MIICMD_CLK);
DELAY(1);
SIO_SET(VR_MIICMD_CLK);
DELAY(1);
  292                 }
  293                 goto fail;
  294         }
  296         for (i = 0x8000; i; i >>= 1) {
SIO_CLR(VR_MIICMD_CLK);
DELAY(1);
  299                 if (!ack) {
  300                         if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
frame->mii_data |= i;
DELAY(1);
  303                 }
SIO_SET(VR_MIICMD_CLK);
DELAY(1);
  306         }
fail:
SIO_CLR(VR_MIICMD_CLK);
DELAY(1);
SIO_SET(VR_MIICMD_CLK);
DELAY(1);
splx(s);
  317         if (ack)
  318                 return(1);
  319         return(0);
  320 }
  321 #else  
  322 {
  323         int                     s, i;
s = splnet();
  327         /* Set the PHY-address */
CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
frame->mii_phyaddr);
  331         /* Set the register-address */
CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
  335         for (i = 0; i < 10000; i++) {
  336                 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
  337                         break;
DELAY(1);
  339         }
frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
splx(s);
  345         return(0);
  346 }      
  347 #endif         
  350 /*
  351  * Write to a PHY register through the MII.
  352  */
  353 int
vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame)
  355 #ifdef VR_USESWSHIFT
  356 {
  357         int                     s;
s = splnet();
CSR_WRITE_1(sc, VR_MIICMD, 0);
VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
  364         /*
  365          * Set up frame for TX.
  366          */
frame->mii_stdelim = VR_MII_STARTDELIM;
frame->mii_opcode = VR_MII_WRITEOP;
frame->mii_turnaround = VR_MII_TURNAROUND;
  372         /*
  373          * Turn on data output.
  374          */
SIO_SET(VR_MIICMD_DIR);
vr_mii_sync(sc);
vr_mii_send(sc, frame->mii_stdelim, 2);
vr_mii_send(sc, frame->mii_opcode, 2);
vr_mii_send(sc, frame->mii_phyaddr, 5);
vr_mii_send(sc, frame->mii_regaddr, 5);
vr_mii_send(sc, frame->mii_turnaround, 2);
vr_mii_send(sc, frame->mii_data, 16);
  386         /* Idle bit. */
SIO_SET(VR_MIICMD_CLK);
DELAY(1);
SIO_CLR(VR_MIICMD_CLK);
DELAY(1);
  392         /*
  393          * Turn off xmit.
  394          */
SIO_CLR(VR_MIICMD_DIR);
splx(s);
  399         return(0);
  400 }
  401 #else  
  402 {      
  403         int                     s, i;
s = splnet();
  407         /* Set the PHY-address */
CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
frame->mii_phyaddr);
  411         /* Set the register-address and data to write */
CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);
VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
  417         for (i = 0; i < 10000; i++) {
  418                 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
  419                         break;
DELAY(1); 
  421         }
splx(s);
  425         return(0);
  426 }
  427 #endif                 
  429 int
vr_miibus_readreg(struct device *dev, int phy, int reg)
  431 {
  432         struct vr_softc *sc = (struct vr_softc *)dev;
  433         struct vr_mii_frame frame;
  435         switch (sc->vr_revid) {
  436         case REV_ID_VT6102_APOLLO:
  437         case REV_ID_VT6103:
  438                 if (phy != 1)
  439                         return 0;
  440         default:
  441                 break;
  442         }
bzero((char *)&frame, sizeof(frame));
frame.mii_phyaddr = phy;
frame.mii_regaddr = reg;
vr_mii_readreg(sc, &frame);
  450         return(frame.mii_data);
  451 }
  453 void
vr_miibus_writereg(struct device *dev, int phy, int reg, int data)
  455 {
  456         struct vr_softc *sc = (struct vr_softc *)dev;
  457         struct vr_mii_frame frame;
  459         switch (sc->vr_revid) {
  460         case REV_ID_VT6102_APOLLO:
  461         case REV_ID_VT6103:
  462                 if (phy != 1)
  463                         return;
  464         default:
  465                 break;
  466         }
bzero((char *)&frame, sizeof(frame));
frame.mii_phyaddr = phy;
frame.mii_regaddr = reg;
frame.mii_data = data;
vr_mii_writereg(sc, &frame);
  475 }
  477 void
vr_miibus_statchg(struct device *dev)
  479 {
  480         struct vr_softc *sc = (struct vr_softc *)dev;
vr_setcfg(sc, sc->sc_mii.mii_media_active);
  483 }
  485 /*
  486  * Program the 64-bit multicast hash filter.
  487  */
  488 void
vr_setmulti(struct vr_softc *sc)
  490 {
  491         struct ifnet            *ifp;
  492         int                     h = 0;
u_int32_t               hashes[2] = { 0, 0 };
  494         struct arpcom *ac = &sc->arpcom;
  495         struct ether_multi *enm;
  496         struct ether_multistep step;
u_int8_t                rxfilt;
  498         int                     mcnt = 0;
ifp = &sc->arpcom.ac_if;
rxfilt = CSR_READ_1(sc, VR_RXCFG);
  504         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
allmulti:
rxfilt |= VR_RXCFG_RX_MULTI;
CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
  510                 return;
  511         }
  513         /* first, zot all the existing hash bits */
CSR_WRITE_4(sc, VR_MAR0, 0);
CSR_WRITE_4(sc, VR_MAR1, 0);
  517         /* now program new ones */
ETHER_FIRST_MULTI(step, ac, enm);
  519         while (enm != NULL) {
  520                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
ifp->if_flags |= IFF_ALLMULTI;
  522                         goto allmulti;
  523                 }
h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26;
  525                 if (h < 32)
hashes[0] |= (1 << h);
  527                 else
hashes[1] |= (1 << (h - 32));
mcnt++;
ETHER_NEXT_MULTI(step, enm);
  532         }
  534         if (mcnt)
rxfilt |= VR_RXCFG_RX_MULTI;
  536         else
rxfilt &= ~VR_RXCFG_RX_MULTI;
CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
  542 }
  544 /*
  545  * In order to fiddle with the
  546  * 'full-duplex' and '100Mbps' bits in the netconfig register, we
  547  * first have to put the transmit and/or receive logic in the idle state.
  548  */
  549 void
vr_setcfg(struct vr_softc *sc, int media)
  551 {
  552         int restart = 0;
  554         if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
restart = 1;
VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
  557         }
  559         if ((media & IFM_GMASK) == IFM_FDX)
VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
  561         else
VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
  564         if (restart)
VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
  566 }
  568 void
vr_reset(struct vr_softc *sc)
  570 {
  571         int                     i;
VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
  575         for (i = 0; i < VR_TIMEOUT; i++) {
DELAY(10);
  577                 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
  578                         break;
  579         }
  580         if (i == VR_TIMEOUT) {
  581                 if (sc->vr_revid < REV_ID_VT3065_A)
printf("%s: reset never completed!\n",
sc->sc_dev.dv_xname);
  584                 else {
  585 #ifdef VR_DEBUG
  586                         /* Use newer force reset command */
printf("%s: Using force reset command.\n",
sc->sc_dev.dv_xname);
  589 #endif
VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
  591                 }
  592         }       
  594         /* Wait a little while for the chip to get its brains in order. */
DELAY(1000);
  596 }
  598 /*
  599  * Probe for a VIA Rhine chip.
  600  */
  601 int
vr_probe(struct device *parent, void *match, void *aux)
  603 {
  604         return (pci_matchbyid((struct pci_attach_args *)aux, vr_devices,
  605             sizeof(vr_devices)/sizeof(vr_devices[0])));
  606 }
  608 /*
  609  * Attach the interface. Allocate softc structures, do ifmedia
  610  * setup and ethernet/BPF attach.
  611  */
  612 void
vr_attach(struct device *parent, struct device *self, void *aux)
  614 {
  615         int                     i;
pcireg_t                command;
  617         struct vr_softc         *sc = (struct vr_softc *)self;
  618         struct pci_attach_args  *pa = aux;
pci_chipset_tag_t       pc = pa->pa_pc;
pci_intr_handle_t       ih;
  621         const char              *intrstr = NULL;
  622         struct ifnet            *ifp = &sc->arpcom.ac_if;
bus_size_t              size;
  624         int rseg;
caddr_t kva;
  627         /*
  628          * Handle power management nonsense.
  629          */
command = pci_conf_read(pa->pa_pc, pa->pa_tag,
VR_PCI_CAPID) & 0x000000ff;
  632         if (command == 0x01) {
command = pci_conf_read(pa->pa_pc, pa->pa_tag,
VR_PCI_PWRMGMTCTRL);
  635                 if (command & VR_PSTATE_MASK) {
pcireg_t        iobase, membase, irq;
  638                         /* Save important PCI config data. */
iobase = pci_conf_read(pa->pa_pc, pa->pa_tag,
VR_PCI_LOIO);
membase = pci_conf_read(pa->pa_pc, pa->pa_tag,
VR_PCI_LOMEM);
irq = pci_conf_read(pa->pa_pc, pa->pa_tag,
VR_PCI_INTLINE);
  646                         /* Reset the power state. */
command &= 0xFFFFFFFC;
pci_conf_write(pa->pa_pc, pa->pa_tag,
VR_PCI_PWRMGMTCTRL, command);
  651                         /* Restore PCI config data. */
pci_conf_write(pa->pa_pc, pa->pa_tag,
VR_PCI_LOIO, iobase);
pci_conf_write(pa->pa_pc, pa->pa_tag,
VR_PCI_LOMEM, membase);
pci_conf_write(pa->pa_pc, pa->pa_tag,
VR_PCI_INTLINE, irq);
  658                 }
  659         }
  661         /*
  662          * Map control/status registers.
  663          */
  665 #ifdef VR_USEIOSPACE
  666         if (pci_mapreg_map(pa, VR_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
  667             &sc->vr_btag, &sc->vr_bhandle, NULL, &size, 0)) {
printf(": failed to map i/o space\n");
  669                 return;
  670         }
  671 #else
  672         if (pci_mapreg_map(pa, VR_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
  673             &sc->vr_btag, &sc->vr_bhandle, NULL, &size, 0)) {
printf(": failed to map memory space\n");
  675                 return;
  676         }
  677 #endif
  679         /* Allocate interrupt */
  680         if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
  682                 goto fail_1;
  683         }
intrstr = pci_intr_string(pc, ih);
sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, vr_intr, sc,
self->dv_xname);
  687         if (sc->sc_ih == NULL) {
printf(": could not establish interrupt");
  689                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
  692                 goto fail_1;
  693         }
printf(": %s", intrstr);
sc->vr_revid = PCI_REVISION(pa->pa_class);
  698         /*
  699          * Windows may put the chip in suspend mode when it
  700          * shuts down. Be sure to kick it in the head to wake it
  701          * up again.
  702          */
VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
  705         /* Reset the adapter. */
vr_reset(sc);
  708         /*
  709          * Turn on bit2 (MIION) in PCI configuration register 0x53 during
  710          * initialization and disable AUTOPOLL.
  711          */
pci_conf_write(pa->pa_pc, pa->pa_tag, VR_PCI_MODE,
pci_conf_read(pa->pa_pc, pa->pa_tag, VR_PCI_MODE) |
  714             (VR_MODE3_MIION << 24));
VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
  717         /*
  718          * Get station address. The way the Rhine chips work,
  719          * you're not allowed to directly access the EEPROM once
  720          * they've been programmed a special way. Consequently,
  721          * we need to read the node address from the PAR0 and PAR1
  722          * registers.
  723          */
VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
DELAY(1000);
  726         for (i = 0; i < ETHER_ADDR_LEN; i++)
sc->arpcom.ac_enaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
  729         /*
  730          * A Rhine chip was detected. Inform the world.
  731          */
printf(", address %s\n", ether_sprintf(sc->arpcom.ac_enaddr));
sc->sc_dmat = pa->pa_dmat;
  735         if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct vr_list_data),
PAGE_SIZE, 0, &sc->sc_listseg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf(": can't alloc list\n");
  738                 goto fail_2;
  739         }
  740         if (bus_dmamem_map(sc->sc_dmat, &sc->sc_listseg, rseg,
  741             sizeof(struct vr_list_data), &kva, BUS_DMA_NOWAIT)) {
printf(": can't map dma buffers (%d bytes)\n",
  743                     sizeof(struct vr_list_data));
  744                 goto fail_3;
  745         }
  746         if (bus_dmamap_create(sc->sc_dmat, sizeof(struct vr_list_data), 1,
  747             sizeof(struct vr_list_data), 0, BUS_DMA_NOWAIT, &sc->sc_listmap)) {
printf(": can't create dma map\n");
  749                 goto fail_4;
  750         }
  751         if (bus_dmamap_load(sc->sc_dmat, sc->sc_listmap, kva,
  752             sizeof(struct vr_list_data), NULL, BUS_DMA_NOWAIT)) {
printf(": can't load dma map\n");
  754                 goto fail_5;
  755         }
sc->vr_ldata = (struct vr_list_data *)kva;
bzero(sc->vr_ldata, sizeof(struct vr_list_data));
ifp = &sc->arpcom.ac_if;
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = vr_ioctl;
ifp->if_start = vr_start;
ifp->if_watchdog = vr_watchdog;
ifp->if_baudrate = 10000000;
IFQ_SET_READY(&ifp->if_snd);
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
  769         /*
  770          * Do MII setup.
  771          */
sc->sc_mii.mii_ifp = ifp;
sc->sc_mii.mii_readreg = vr_miibus_readreg;
sc->sc_mii.mii_writereg = vr_miibus_writereg;
sc->sc_mii.mii_statchg = vr_miibus_statchg;
ifmedia_init(&sc->sc_mii.mii_media, 0, vr_ifmedia_upd, vr_ifmedia_sts);
mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY,
  778             0);
  779         if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
  782         } else
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
timeout_set(&sc->sc_to, vr_tick, sc);
  786         /*
  787          * Call MI attach routines.
  788          */
if_attach(ifp);
ether_ifattach(ifp);
shutdownhook_establish(vr_shutdown, sc);
  793         return;
fail_5:
bus_dmamap_destroy(sc->sc_dmat, sc->sc_listmap);
fail_4:
bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct vr_list_data));
fail_3:
bus_dmamem_free(sc->sc_dmat, &sc->sc_listseg, rseg);
fail_2:
pci_intr_disestablish(pc, sc->sc_ih);
fail_1:
bus_space_unmap(sc->vr_btag, sc->vr_bhandle, size);
  809 }
  811 /*
  812  * Initialize the transmit descriptors.
  813  */
  814 int
vr_list_tx_init(struct vr_softc *sc)
  816 {
  817         struct vr_chain_data    *cd;
  818         struct vr_list_data     *ld;
  819         int                     i;
cd = &sc->vr_cdata;
ld = sc->vr_ldata;
  823         for (i = 0; i < VR_TX_LIST_CNT; i++) {
cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i];
cd->vr_tx_chain[i].vr_paddr =
sc->sc_listmap->dm_segs[0].ds_addr +
offsetof(struct vr_list_data, vr_tx_list[i]);
  829                 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
MCLBYTES, 0, BUS_DMA_NOWAIT, &cd->vr_tx_chain[i].vr_map))
  831                         return (ENOBUFS);
  833                 if (i == (VR_TX_LIST_CNT - 1))
cd->vr_tx_chain[i].vr_nextdesc = 
  835                                 &cd->vr_tx_chain[0];
  836                 else
cd->vr_tx_chain[i].vr_nextdesc =
  838                                 &cd->vr_tx_chain[i + 1];
  839         }
cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0];
  843         return (0);
  844 }
  847 /*
  848  * Initialize the RX descriptors and allocate mbufs for them. Note that
  849  * we arrange the descriptors in a closed ring, so that the last descriptor
  850  * points back to the first.
  851  */
  852 int
vr_list_rx_init(struct vr_softc *sc)
  854 {
  855         struct vr_chain_data    *cd;
  856         struct vr_list_data     *ld;
  857         int                     i;
  858         struct vr_desc          *d;
cd = &sc->vr_cdata;
ld = sc->vr_ldata;
  863         for (i = 0; i < VR_RX_LIST_CNT; i++) {
d = (struct vr_desc *)&ld->vr_rx_list[i];
cd->vr_rx_chain[i].vr_ptr = d;
cd->vr_rx_chain[i].vr_paddr =
sc->sc_listmap->dm_segs[0].ds_addr +
offsetof(struct vr_list_data, vr_rx_list[i]);
cd->vr_rx_chain[i].vr_buf =
  870                     (u_int8_t *)malloc(MCLBYTES, M_DEVBUF, M_NOWAIT);
  871                 if (cd->vr_rx_chain[i].vr_buf == NULL)
  872                         return (ENOBUFS);
  874                 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 
  875                     0, BUS_DMA_NOWAIT | BUS_DMA_READ,
  876                     &cd->vr_rx_chain[i].vr_map))
  877                         return (ENOBUFS);
  879                 if (bus_dmamap_load(sc->sc_dmat, cd->vr_rx_chain[i].vr_map,
cd->vr_rx_chain[i].vr_buf, MCLBYTES, NULL, BUS_DMA_NOWAIT))
  881                         return (ENOBUFS);
bus_dmamap_sync(sc->sc_dmat, cd->vr_rx_chain[i].vr_map,
  883                     0, cd->vr_rx_chain[i].vr_map->dm_mapsize,
BUS_DMASYNC_PREREAD);
d->vr_status = htole32(VR_RXSTAT);
d->vr_data =
htole32(cd->vr_rx_chain[i].vr_map->dm_segs[0].ds_addr +
  889                     sizeof(u_int64_t));
d->vr_ctl = htole32(VR_RXCTL | VR_RXLEN);
  892                 if (i == (VR_RX_LIST_CNT - 1)) {
cd->vr_rx_chain[i].vr_nextdesc =
  894                             &cd->vr_rx_chain[0];
ld->vr_rx_list[i].vr_next =
htole32(sc->sc_listmap->dm_segs[0].ds_addr +
offsetof(struct vr_list_data, vr_rx_list[0]));
  898                 } else {
cd->vr_rx_chain[i].vr_nextdesc =
  900                             &cd->vr_rx_chain[i + 1];
ld->vr_rx_list[i].vr_next =
htole32(sc->sc_listmap->dm_segs[0].ds_addr +
offsetof(struct vr_list_data, vr_rx_list[i + 1]));
  904                 }
  905         }
cd->vr_rx_head = &cd->vr_rx_chain[0];
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 0,
sc->sc_listmap->dm_mapsize,
BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
  913         return(0);
  914 }
  916 /*
  917  * A frame has been uploaded: pass the resulting mbuf chain up to
  918  * the higher level protocols.
  919  */
  920 void
vr_rxeof(struct vr_softc *sc)
  922 {
  923         struct mbuf             *m0;
  924         struct ifnet            *ifp;
  925         struct vr_chain_onefrag *cur_rx;
  926         int                     total_len = 0;
u_int32_t               rxstat;
ifp = &sc->arpcom.ac_if;
  931         for (;;) {
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
  934                     0, sc->sc_listmap->dm_mapsize,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
rxstat = letoh32(sc->vr_cdata.vr_rx_head->vr_ptr->vr_status);
  937                 if (rxstat & VR_RXSTAT_OWN)
  938                         break;
m0 = NULL;
cur_rx = sc->vr_cdata.vr_rx_head;
sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc;
  944                 /*
  945                  * If an error occurs, update stats, clear the
  946                  * status word and leave the mbuf cluster in place:
  947                  * it should simply get re-used next time this descriptor
  948                  * comes up in the ring.
  949                  */
  950                 if (rxstat & VR_RXSTAT_RXERR) {
ifp->if_ierrors++;
  952 #ifdef VR_DEBUG
printf("%s: rx error (%02x):",
sc->sc_dev.dv_xname, rxstat & 0x000000ff);
  955                         if (rxstat & VR_RXSTAT_CRCERR)
printf(" crc error");
  957                         if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
printf(" frame alignment error");
  959                         if (rxstat & VR_RXSTAT_FIFOOFLOW)
printf(" FIFO overflow");
  961                         if (rxstat & VR_RXSTAT_GIANT)
printf(" received giant packet");
  963                         if (rxstat & VR_RXSTAT_RUNT)
printf(" received runt packet");
  965                         if (rxstat & VR_RXSTAT_BUSERR)
printf(" system bus error");
  967                         if (rxstat & VR_RXSTAT_BUFFERR)
printf(" rx buffer error");
printf("\n");
  970 #endif
  972                         /* Reinitialize descriptor */
cur_rx->vr_ptr->vr_status = htole32(VR_RXSTAT);
cur_rx->vr_ptr->vr_data =
htole32(cur_rx->vr_map->dm_segs[0].ds_addr +
  976                             sizeof(u_int64_t));
cur_rx->vr_ptr->vr_ctl = htole32(VR_RXCTL | VR_RXLEN);
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
  979                             0, sc->sc_listmap->dm_mapsize,
BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
  981                         continue;
  982                 }
  984                 /* No errors; receive the packet. */    
total_len = VR_RXBYTES(letoh32(cur_rx->vr_ptr->vr_status));
  987                 /*
  988                  * XXX The VIA Rhine chip includes the CRC with every
  989                  * received frame, and there's no way to turn this
  990                  * behavior off (at least, I can't find anything in
  991                  * the manual that explains how to do it) so we have
  992                  * to trim off the CRC manually.
  993                  */
total_len -= ETHER_CRC_LEN;
bus_dmamap_sync(sc->sc_dmat, cur_rx->vr_map, 0,
cur_rx->vr_map->dm_mapsize,
BUS_DMASYNC_POSTREAD);
m0 = m_devget(cur_rx->vr_buf + sizeof(u_int64_t) - ETHER_ALIGN,
total_len + ETHER_ALIGN, 0, ifp, NULL);
bus_dmamap_sync(sc->sc_dmat, cur_rx->vr_map, 0,
cur_rx->vr_map->dm_mapsize,
BUS_DMASYNC_PREREAD);
 1005                 /* Reinitialize descriptor */
cur_rx->vr_ptr->vr_status = htole32(VR_RXSTAT);
cur_rx->vr_ptr->vr_data =
htole32(cur_rx->vr_map->dm_segs[0].ds_addr +
 1009                     sizeof(u_int64_t));
cur_rx->vr_ptr->vr_ctl = htole32(VR_RXCTL | VR_RXLEN);
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 0,
sc->sc_listmap->dm_mapsize,
BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 1015                 if (m0 == NULL) {
ifp->if_ierrors++;
 1017                         continue;
 1018                 }
m_adj(m0, ETHER_ALIGN);
ifp->if_ipackets++;
 1023 #if NBPFILTER > 0
 1024                 /*
 1025                  * Handle BPF listeners. Let the BPF user see the packet.
 1026                  */
 1027                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_IN);
 1029 #endif
 1030                 /* pass it on. */
ether_input_mbuf(ifp, m0);
 1032         }
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
 1035             0, sc->sc_listmap->dm_mapsize,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1037 }
 1039 void
vr_rxeoc(struct vr_softc *sc)
 1041 {
 1042         struct ifnet            *ifp;
 1043         int                     i;
ifp = &sc->arpcom.ac_if;
ifp->if_ierrors++;      
VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);      
DELAY(10000);  
 1052         for (i = 0x400; 
i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);
i--)  
 1055                 ;       /* Wait for receiver to stop */
 1057         if (!i) {       
printf("%s: rx shutdown error!\n", sc->sc_dev.dv_xname);
sc->vr_flags |= VR_F_RESTART;
 1060                 return; 
 1061         }
vr_rxeof(sc);
CSR_WRITE_4(sc, VR_RXADDR, sc->vr_cdata.vr_rx_head->vr_paddr);
VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
 1068 }
 1070 /*
 1071  * A frame was downloaded to the chip. It's safe for us to clean up
 1072  * the list buffers.
 1073  */
 1075 void
vr_txeof(struct vr_softc *sc)
 1077 {
 1078         struct vr_chain         *cur_tx;
 1079         struct ifnet            *ifp;
ifp = &sc->arpcom.ac_if;
 1083         /*
 1084          * Go through our tx list and free mbufs for those
 1085          * frames that have been transmitted.
 1086          */
cur_tx = sc->vr_cdata.vr_tx_cons;
 1088         while(cur_tx->vr_mbuf != NULL) {
u_int32_t               txstat;
 1090                 int                     i;
txstat = letoh32(cur_tx->vr_ptr->vr_status);
 1094                 if ((txstat & VR_TXSTAT_ABRT) ||
 1095                     (txstat & VR_TXSTAT_UDF)) {
 1096                         for (i = 0x400;
i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);
i--)
 1099                                 ;       /* Wait for chip to shutdown */
 1100                         if (!i) {
printf("%s: tx shutdown timeout\n",
sc->sc_dev.dv_xname);
sc->vr_flags |= VR_F_RESTART;
 1104                                 break;
 1105                         }
VR_TXOWN(cur_tx) = htole32(VR_TXSTAT_OWN);
CSR_WRITE_4(sc, VR_TXADDR, cur_tx->vr_paddr);
 1108                         break;
 1109                 }
 1111                 if (txstat & VR_TXSTAT_OWN)
 1112                         break;
 1114                 if (txstat & VR_TXSTAT_ERRSUM) {
ifp->if_oerrors++;
 1116                         if (txstat & VR_TXSTAT_DEFER)
ifp->if_collisions++;
 1118                         if (txstat & VR_TXSTAT_LATECOLL)
ifp->if_collisions++;
 1120                 }
ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3;
ifp->if_opackets++;
 1125                 if (cur_tx->vr_map != NULL && cur_tx->vr_map->dm_nsegs > 0)
bus_dmamap_unload(sc->sc_dmat, cur_tx->vr_map);
m_freem(cur_tx->vr_mbuf);
cur_tx->vr_mbuf = NULL;
ifp->if_flags &= ~IFF_OACTIVE;
cur_tx = cur_tx->vr_nextdesc;
 1133         }
sc->vr_cdata.vr_tx_cons = cur_tx;
 1136         if (cur_tx->vr_mbuf == NULL)
ifp->if_timer = 0;
 1138 }
 1140 void
vr_tick(void *xsc)
 1142 {
 1143         struct vr_softc *sc = xsc;
 1144         int s;
s = splnet();
 1147         if (sc->vr_flags & VR_F_RESTART) {
printf("%s: restarting\n", sc->sc_dev.dv_xname);
vr_stop(sc);
vr_reset(sc);   
vr_init(sc);
sc->vr_flags &= ~VR_F_RESTART;
 1153         }           
mii_tick(&sc->sc_mii);
timeout_add(&sc->sc_to, hz);
splx(s);
 1158 }
 1160 int
vr_intr(void *arg)
 1162 {
 1163         struct vr_softc         *sc;
 1164         struct ifnet            *ifp;
u_int16_t               status;
 1166         int claimed = 0;
sc = arg;
ifp = &sc->arpcom.ac_if;
 1171         /* Supress unwanted interrupts. */
 1172         if (!(ifp->if_flags & IFF_UP)) {
vr_stop(sc);
 1174                 return 0;
 1175         }
 1177         /* Disable interrupts. */
CSR_WRITE_2(sc, VR_IMR, 0x0000);
 1180         for (;;) {
status = CSR_READ_2(sc, VR_ISR);
 1183                 if (status)
CSR_WRITE_2(sc, VR_ISR, status);
 1186                 if ((status & VR_INTRS) == 0)
 1187                         break;
claimed = 1;
 1191                 if (status & VR_ISR_RX_OK)
vr_rxeof(sc);
 1194                 if (status & VR_ISR_RX_DROPPED) {
 1195 #ifdef VR_DEBUG
printf("%s: rx packet lost\n", sc->sc_dev.dv_xname);
 1197 #endif
ifp->if_ierrors++;
 1199                 }       
 1201                 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) ||
 1202                     (status & VR_ISR_RX_OFLOW)) {
 1203 #ifdef VR_DEBUG
printf("%s: receive error (%04x)",
sc->sc_dev.dv_xname, status);
 1206                         if (status & VR_ISR_RX_NOBUF)
printf(" no buffers");
 1208                         if (status & VR_ISR_RX_OFLOW)
printf(" overflow");
printf("\n");
 1211 #endif
vr_rxeoc(sc);
 1213                 }
 1215                 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) {
 1216 #ifdef VR_DEBUG
 1217                         if (status & VR_ISR_BUSERR)
printf("%s: PCI bus error\n",
sc->sc_dev.dv_xname);
 1220                         if (status & VR_ISR_TX_UNDERRUN)
printf("%s: transmit underrun\n",
sc->sc_dev.dv_xname);
 1223 #endif
vr_reset(sc);
vr_init(sc);
 1226                         break;
 1227                 }
 1229                 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) ||
 1230                     (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) {
vr_txeof(sc);
 1232                         if ((status & VR_ISR_UDFI) ||
 1233                             (status & VR_ISR_TX_ABRT2) ||
 1234                             (status & VR_ISR_TX_ABRT)) {
 1235 #ifdef VR_DEBUG
 1236                                 if (status & (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2))
printf("%s: transmit aborted\n",
sc->sc_dev.dv_xname);
 1239                                 if (status & VR_ISR_UDFI)
printf("%s: transmit underflow\n",
sc->sc_dev.dv_xname);
 1242 #endif
ifp->if_oerrors++;
 1244                                 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) {
VR_SETBIT16(sc, VR_COMMAND,
VR_CMD_TX_ON);
VR_SETBIT16(sc, VR_COMMAND,
VR_CMD_TX_GO); 
 1249                                 }
 1250                         }
 1251                 }
 1252         }
 1254         /* Re-enable interrupts. */
CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
 1257         if (!IFQ_IS_EMPTY(&ifp->if_snd))
vr_start(ifp);
 1260         return (claimed);
 1261 }
 1263 /*
 1264  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
 1265  * pointers to the fragment pointers.
 1266  */
 1267 int
vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head)
 1269 {
 1270         struct vr_desc          *f = NULL;
 1271         struct mbuf             *m_new = NULL;
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1274         if (m_new == NULL)
 1275                 return (1);
 1276         if (m_head->m_pkthdr.len > MHLEN) {
MCLGET(m_new, M_DONTWAIT);
 1278                 if (!(m_new->m_flags & M_EXT)) {
m_freem(m_new);
 1280                         return (1);
 1281                 }
 1282         }
m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
 1286         /*
 1287          * The Rhine chip doesn't auto-pad, so we have to make
 1288          * sure to pad short frames out to the minimum frame length
 1289          * ourselves.
 1290          */
 1291         if (m_new->m_len < VR_MIN_FRAMELEN) {
 1292                 /* data field should be padded with octets of zero */
bzero(&m_new->m_data[m_new->m_len],
VR_MIN_FRAMELEN-m_new->m_len);
m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len;
m_new->m_len = m_new->m_pkthdr.len;
 1297         }
 1299         if (bus_dmamap_load_mbuf(sc->sc_dmat, c->vr_map, m_new,
BUS_DMA_NOWAIT | BUS_DMA_WRITE)) {
m_freem(m_new);
 1302                 return (1);
 1303         }
bus_dmamap_sync(sc->sc_dmat, c->vr_map, 0, c->vr_map->dm_mapsize,
BUS_DMASYNC_PREWRITE);
m_freem(m_head);
c->vr_mbuf = m_new;
f = c->vr_ptr;
f->vr_data = htole32(c->vr_map->dm_segs[0].ds_addr);
f->vr_ctl = htole32(c->vr_map->dm_mapsize);
f->vr_ctl |= htole32(VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG);
f->vr_status = htole32(0);
f->vr_ctl |= htole32(VR_TXCTL_LASTFRAG|VR_TXCTL_FINT);
f->vr_next = htole32(c->vr_nextdesc->vr_paddr);
 1320         return (0);
 1321 }
 1323 /*
 1324  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 1325  * to the mbuf data regions directly in the transmit lists. We also save a
 1326  * copy of the pointers since the transmit list fragment pointers are
 1327  * physical addresses.
 1328  */
 1330 void
vr_start(struct ifnet *ifp)
 1332 {
 1333         struct vr_softc         *sc;
 1334         struct mbuf             *m_head;
 1335         struct vr_chain         *cur_tx;
 1337         if (ifp->if_flags & IFF_OACTIVE)
 1338                 return;
sc = ifp->if_softc;
cur_tx = sc->vr_cdata.vr_tx_prod;
 1343         while (cur_tx->vr_mbuf == NULL) {
IFQ_DEQUEUE(&ifp->if_snd, m_head);
 1345                 if (m_head == NULL)
 1346                         break;
 1348                 /* Pack the data into the descriptor. */
 1349                 if (vr_encap(sc, cur_tx, m_head)) {
 1350                         /* Rollback, send what we were able to encap. */
 1351                         if (ALTQ_IS_ENABLED(&ifp->if_snd))
m_freem(m_head);
 1353                         else
IF_PREPEND(&ifp->if_snd, m_head);
 1355                         break;
 1356                 }
VR_TXOWN(cur_tx) = htole32(VR_TXSTAT_OWN);
 1360 #if NBPFILTER > 0
 1361                 /*
 1362                  * If there's a BPF listener, bounce a copy of this frame
 1363                  * to him.
 1364                  */
 1365                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, cur_tx->vr_mbuf,
BPF_DIRECTION_OUT);
 1368 #endif
cur_tx = cur_tx->vr_nextdesc;
 1370         }
 1371         if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) {
sc->vr_cdata.vr_tx_prod = cur_tx;
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 0,
sc->sc_listmap->dm_mapsize,
BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
 1378                 /* Tell the chip to start transmitting. */
VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO);
 1381                 /* Set a timeout in case the chip goes out to lunch. */
ifp->if_timer = 5;
 1384                 if (cur_tx->vr_mbuf != NULL)
ifp->if_flags |= IFF_OACTIVE;
 1386         }
 1387 }
 1389 void
vr_init(void *xsc)
 1391 {
 1392         struct vr_softc         *sc = xsc;
 1393         struct ifnet            *ifp = &sc->arpcom.ac_if;
 1394         struct mii_data         *mii = &sc->sc_mii;
 1395         int                     s, i;
s = splnet();
 1399         /*
 1400          * Cancel pending I/O and free all RX/TX buffers.
 1401          */
vr_stop(sc);
vr_reset(sc);
 1405         /*
 1406          * Set our station address.
 1407          */
 1408         for (i = 0; i < ETHER_ADDR_LEN; i++)
CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
 1411         /* Set DMA size */
VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
 1415         /*
 1416          * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
 1417          * so we must set both.
 1418          */
VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
 1431         /* Init circular RX list. */
 1432         if (vr_list_rx_init(sc) == ENOBUFS) {
printf("%s: initialization failed: no memory for rx buffers\n",
sc->sc_dev.dv_xname);
vr_stop(sc);
splx(s);
 1437                 return;
 1438         }
 1440         /*
 1441          * Init tx descriptors.
 1442          */
 1443         if (vr_list_tx_init(sc) == ENOBUFS) {
printf("%s: initialization failed: no memory for tx buffers\n",
sc->sc_dev.dv_xname);
vr_stop(sc);
splx(s);
 1448                 return;
 1449         }
 1451         /* If we want promiscuous mode, set the allframes bit. */
 1452         if (ifp->if_flags & IFF_PROMISC)
VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
 1454         else
VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
 1457         /* Set capture broadcast bit to capture broadcast frames. */
 1458         if (ifp->if_flags & IFF_BROADCAST)
VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
 1460         else
VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
 1463         /*
 1464          * Program the multicast filter, if necessary.
 1465          */
vr_setmulti(sc);
 1468         /*
 1469          * Load the address of the RX list.
 1470          */
CSR_WRITE_4(sc, VR_RXADDR, sc->vr_cdata.vr_rx_head->vr_paddr);
 1473         /* Enable receiver and transmitter. */
CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
VR_CMD_TX_ON|VR_CMD_RX_ON|
VR_CMD_RX_GO);
CSR_WRITE_4(sc, VR_TXADDR, sc->sc_listmap->dm_segs[0].ds_addr +
offsetof(struct vr_list_data, vr_tx_list[0]));
 1481         /*
 1482          * Enable interrupts.
 1483          */
CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
 1487         /* Restore state of BMCR */
mii_mediachg(mii);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
 1493         if (!timeout_pending(&sc->sc_to))
timeout_add(&sc->sc_to, hz);
splx(s);
 1497 }
 1499 /*
 1500  * Set media options.
 1501  */
 1502 int
vr_ifmedia_upd(struct ifnet *ifp)
 1504 {
 1505         struct vr_softc         *sc = ifp->if_softc;
 1507         if (ifp->if_flags & IFF_UP)
vr_init(sc);
 1510         return (0);
 1511 }
 1513 /*
 1514  * Report current media status.
 1515  */
 1516 void
vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 1518 {
 1519         struct vr_softc         *sc = ifp->if_softc;
 1520         struct mii_data         *mii = &sc->sc_mii;
mii_pollstat(mii);
ifmr->ifm_active = mii->mii_media_active;
ifmr->ifm_status = mii->mii_media_status;
 1525 }
 1527 int
vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 1529 {
 1530         struct vr_softc         *sc = ifp->if_softc;
 1531         struct ifreq            *ifr = (struct ifreq *) data;
 1532         int                     s, error = 0;
 1533         struct ifaddr *ifa = (struct ifaddr *)data;
s = splnet();
 1537         if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) {
splx(s);
 1539                 return error;
 1540         }
 1542         switch(command) {
 1543         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
 1545                 if (!(ifp->if_flags & IFF_RUNNING))
vr_init(sc);
 1547 #ifdef INET
 1548                 if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc->arpcom, ifa);
 1550 #endif
 1551                 break;
 1552         case SIOCSIFFLAGS:
 1553                 if (ifp->if_flags & IFF_UP) {
 1554                         if (ifp->if_flags & IFF_RUNNING &&
ifp->if_flags & IFF_PROMISC &&
 1556                             !(sc->sc_if_flags & IFF_PROMISC)) {
VR_SETBIT(sc, VR_RXCFG,
VR_RXCFG_RX_PROMISC);
vr_setmulti(sc);
 1560                         } else if (ifp->if_flags & IFF_RUNNING &&
 1561                             !(ifp->if_flags & IFF_PROMISC) &&
sc->sc_if_flags & IFF_PROMISC) {
VR_CLRBIT(sc, VR_RXCFG,
VR_RXCFG_RX_PROMISC);
vr_setmulti(sc);
 1566                         } else if (ifp->if_flags & IFF_RUNNING &&
 1567                             (ifp->if_flags ^ sc->sc_if_flags) & IFF_ALLMULTI) {
vr_setmulti(sc);
 1569                         } else {
 1570                                 if (!(ifp->if_flags & IFF_RUNNING))
vr_init(sc);
 1572                         }
 1573                 } else {
 1574                         if (ifp->if_flags & IFF_RUNNING)
vr_stop(sc);
 1576                 }
sc->sc_if_flags = ifp->if_flags;
 1578                 break;
 1579         case SIOCADDMULTI:
 1580         case SIOCDELMULTI:
error = (command == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->arpcom) :
ether_delmulti(ifr, &sc->arpcom);
 1585                 if (error == ENETRESET) {
 1586                         /*
 1587                          * Multicast list has changed; set the hardware
 1588                          * filter accordingly.
 1589                          */
 1590                         if (ifp->if_flags & IFF_RUNNING)
vr_setmulti(sc);
error = 0;
 1593                 }
 1594                 break;
 1595         case SIOCGIFMEDIA:
 1596         case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
 1598                 break;
 1599         default:
error = ENOTTY;
 1601                 break;
 1602         }
splx(s);
 1606         return(error);
 1607 }
 1609 void
vr_watchdog(struct ifnet *ifp)
 1611 {
 1612         struct vr_softc         *sc;
sc = ifp->if_softc;
ifp->if_oerrors++;
printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
vr_stop(sc);
vr_reset(sc);
vr_init(sc);
 1623         if (!IFQ_IS_EMPTY(&ifp->if_snd))
vr_start(ifp);
 1625 }
 1627 /*
 1628  * Stop the adapter and free any mbufs allocated to the
 1629  * RX and TX lists.
 1630  */
 1631 void
vr_stop(struct vr_softc *sc)
 1633 {
 1634         int             i;
 1635         struct ifnet    *ifp;
bus_dmamap_t    map;
ifp = &sc->arpcom.ac_if;
ifp->if_timer = 0;
 1641         if (timeout_pending(&sc->sc_to))
timeout_del(&sc->sc_to);
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
CSR_WRITE_2(sc, VR_IMR, 0x0000);
CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
 1652         /*
 1653          * Free data in the RX lists.
 1654          */
 1655         for (i = 0; i < VR_RX_LIST_CNT; i++) {
 1657                 if (sc->vr_cdata.vr_rx_chain[i].vr_buf != NULL) {
free(sc->vr_cdata.vr_rx_chain[i].vr_buf, M_DEVBUF);
sc->vr_cdata.vr_rx_chain[i].vr_buf = NULL;
 1660                 }
map = sc->vr_cdata.vr_rx_chain[i].vr_map;
 1663                 if (map != NULL) {
 1664                         if (map->dm_nsegs > 0)
bus_dmamap_unload(sc->sc_dmat, map);
bus_dmamap_destroy(sc->sc_dmat, map);
sc->vr_cdata.vr_rx_chain[i].vr_map = NULL;
 1668                 }
 1669         }
bzero((char *)&sc->vr_ldata->vr_rx_list,
 1671                 sizeof(sc->vr_ldata->vr_rx_list));
 1673         /*
 1674          * Free the TX list buffers.
 1675          */
 1676         for (i = 0; i < VR_TX_LIST_CNT; i++) {
bus_dmamap_t map;
 1679                 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) {
m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf);
sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL;
 1682                 }
map = sc->vr_cdata.vr_tx_chain[i].vr_map;
 1684                 if (map != NULL) {
 1685                         if (map->dm_nsegs > 0)
bus_dmamap_unload(sc->sc_dmat, map);
bus_dmamap_destroy(sc->sc_dmat, map);
sc->vr_cdata.vr_tx_chain[i].vr_map = NULL;
 1689                 }
 1690         }
bzero((char *)&sc->vr_ldata->vr_tx_list,
 1693                 sizeof(sc->vr_ldata->vr_tx_list));
 1694 }
 1696 /*
 1697  * Stop all chip I/O so that the kernel's probe routines don't
 1698  * get confused by errant DMAs when rebooting.
 1699  */
 1700 void
vr_shutdown(void *arg)
 1702 {
 1703         struct vr_softc         *sc = (struct vr_softc *)arg;
vr_stop(sc);
 1706 }