root/dev/ic/gem.c

DEFINITIONS

1. gem_config
2. gem_tick
3. gem_bitwait
4. gem_reset
5. gem_rxdrain
6. gem_stop
7. gem_reset_rx
8. gem_reset_tx
9. gem_disable_rx
10. gem_disable_tx
11. gem_meminit
12. gem_ringsize
13. gem_init
14. gem_init_regs
15. gem_rint
16. gem_add_rxbuf
17. gem_eint
18. gem_pint
19. gem_intr
20. gem_watchdog
21. gem_mifinit
22. gem_mii_readreg
23. gem_mii_writereg
24. gem_mii_statchg
25. gem_pcs_readreg
26. gem_pcs_writereg
27. gem_mediachange
28. gem_mediastatus
29. gem_ioctl
30. gem_shutdown
31. gem_setladrf
32. gem_encap
33. gem_tint
34. gem_start

    1 /*      $OpenBSD: gem.c,v 1.69 2007/04/19 19:00:01 kettenis Exp $       */
    2 /*      $NetBSD: gem.c,v 1.1 2001/09/16 00:11:43 eeh Exp $ */
    4 /*
    5  *
    6  * Copyright (C) 2001 Eduardo Horvath.
    7  * All rights reserved.
    8  *
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR  ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR  BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  *
   31  */
   33 /*
   34  * Driver for Sun GEM ethernet controllers.
   35  */
   37 #include "bpfilter.h"
   39 #include <sys/param.h>
   40 #include <sys/systm.h>
   41 #include <sys/timeout.h>
   42 #include <sys/mbuf.h>
   43 #include <sys/syslog.h>
   44 #include <sys/malloc.h>
   45 #include <sys/kernel.h>
   46 #include <sys/socket.h>
   47 #include <sys/ioctl.h>
   48 #include <sys/errno.h>
   49 #include <sys/device.h>
   51 #include <machine/endian.h>
   53 #include <net/if.h>
   54 #include <net/if_dl.h>
   55 #include <net/if_media.h>
   57 #ifdef INET
   58 #include <netinet/in.h>
   59 #include <netinet/if_ether.h>
   60 #endif
   62 #if NBPFILTER > 0
   63 #include <net/bpf.h>
   64 #endif
   66 #include <machine/bus.h>
   67 #include <machine/intr.h>
   69 #include <dev/mii/mii.h>
   70 #include <dev/mii/miivar.h>
   71 #include <dev/mii/mii_bitbang.h>
   73 #include <dev/ic/gemreg.h>
   74 #include <dev/ic/gemvar.h>
   76 #define TRIES   10000
   78 struct cfdriver gem_cd = {
NULL, "gem", DV_IFNET
   80 };
   82 void            gem_start(struct ifnet *);
   83 void            gem_stop(struct ifnet *, int);
   84 int             gem_ioctl(struct ifnet *, u_long, caddr_t);
   85 void            gem_tick(void *);
   86 void            gem_watchdog(struct ifnet *);
   87 void            gem_shutdown(void *);
   88 int             gem_init(struct ifnet *);
   89 void            gem_init_regs(struct gem_softc *);
   90 int             gem_ringsize(int);
   91 int             gem_meminit(struct gem_softc *);
   92 void            gem_mifinit(struct gem_softc *);
   93 int             gem_bitwait(struct gem_softc *, bus_space_handle_t, int,
u_int32_t, u_int32_t);
   95 void            gem_reset(struct gem_softc *);
   96 int             gem_reset_rx(struct gem_softc *);
   97 int             gem_reset_tx(struct gem_softc *);
   98 int             gem_disable_rx(struct gem_softc *);
   99 int             gem_disable_tx(struct gem_softc *);
  100 void            gem_rxdrain(struct gem_softc *);
  101 int             gem_add_rxbuf(struct gem_softc *, int idx);
  102 void            gem_setladrf(struct gem_softc *);
  103 int             gem_encap(struct gem_softc *, struct mbuf *, u_int32_t *);
  105 /* MII methods & callbacks */
  106 int             gem_mii_readreg(struct device *, int, int);
  107 void            gem_mii_writereg(struct device *, int, int, int);
  108 void            gem_mii_statchg(struct device *);
  109 int             gem_pcs_readreg(struct device *, int, int);
  110 void            gem_pcs_writereg(struct device *, int, int, int);
  112 int             gem_mediachange(struct ifnet *);
  113 void            gem_mediastatus(struct ifnet *, struct ifmediareq *);
  115 struct mbuf     *gem_get(struct gem_softc *, int, int);
  116 int             gem_eint(struct gem_softc *, u_int);
  117 int             gem_rint(struct gem_softc *);
  118 int             gem_tint(struct gem_softc *, u_int32_t);
  119 int             gem_pint(struct gem_softc *);
  121 #ifdef GEM_DEBUG
  122 #define DPRINTF(sc, x)  if ((sc)->sc_arpcom.ac_if.if_flags & IFF_DEBUG) \
printf x
  124 #else
  125 #define DPRINTF(sc, x)  /* nothing */
  126 #endif
  128 /*
  129  * Attach a Gem interface to the system.
  130  */
  131 void
gem_config(struct gem_softc *sc)
  133 {
  134         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  135         struct mii_data *mii = &sc->sc_mii;
  136         struct mii_softc *child;
  137         int i, error, phyad;
  138         struct ifmedia_entry *ifm;
  140         /* Make sure the chip is stopped. */
ifp->if_softc = sc;
gem_reset(sc);
  144         /*
  145          * Allocate the control data structures, and create and load the
  146          * DMA map for it.
  147          */
  148         if ((error = bus_dmamem_alloc(sc->sc_dmatag,
  149             sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg,
  150             1, &sc->sc_cdnseg, 0)) != 0) {
printf("\n%s: unable to allocate control data, error = %d\n",
sc->sc_dev.dv_xname, error);
  153                 goto fail_0;
  154         }
  156         /* XXX should map this in with correct endianness */
  157         if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg,
  158             sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data,
BUS_DMA_COHERENT)) != 0) {
printf("\n%s: unable to map control data, error = %d\n",
sc->sc_dev.dv_xname, error);
  162                 goto fail_1;
  163         }
  165         if ((error = bus_dmamap_create(sc->sc_dmatag,
  166             sizeof(struct gem_control_data), 1,
  167             sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
printf("\n%s: unable to create control data DMA map, "
  169                     "error = %d\n", sc->sc_dev.dv_xname, error);
  170                 goto fail_2;
  171         }
  173         if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap,
sc->sc_control_data, sizeof(struct gem_control_data), NULL,
  175             0)) != 0) {
printf("\n%s: unable to load control data DMA map, error = %d\n",
sc->sc_dev.dv_xname, error);
  178                 goto fail_3;
  179         }
  181         /*
  182          * Create the receive buffer DMA maps.
  183          */
  184         for (i = 0; i < GEM_NRXDESC; i++) {
  185                 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1,
MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
printf("\n%s: unable to create rx DMA map %d, "
  188                             "error = %d\n", sc->sc_dev.dv_xname, i, error);
  189                         goto fail_5;
  190                 }
sc->sc_rxsoft[i].rxs_mbuf = NULL;
  192         }
  193         /*
  194          * Create the transmit buffer DMA maps.
  195          */
  196         for (i = 0; i < GEM_NTXDESC; i++) {
  197                 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES,
GEM_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
  199                     &sc->sc_txd[i].sd_map)) != 0) {
printf("\n%s: unable to create tx DMA map %d, "
  201                             "error = %d\n", sc->sc_dev.dv_xname, i, error);
  202                         goto fail_6;
  203                 }
sc->sc_txd[i].sd_mbuf = NULL;
  205         }
  207         /*
  208          * From this point forward, the attachment cannot fail.  A failure
  209          * before this point releases all resources that may have been
  210          * allocated.
  211          */
  213         /* Announce ourselves. */
printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
  216         /* Get RX FIFO size */
sc->sc_rxfifosize = 64 *
bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_FIFO_SIZE);
  220         /* Initialize ifnet structure. */
strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname);
ifp->if_softc = sc;
ifp->if_flags =
IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
ifp->if_start = gem_start;
ifp->if_ioctl = gem_ioctl;
ifp->if_watchdog = gem_watchdog;
IFQ_SET_MAXLEN(&ifp->if_snd, GEM_NTXDESC - 1);
IFQ_SET_READY(&ifp->if_snd);
ifp->if_capabilities = IFCAP_VLAN_MTU;
  233         /* Initialize ifmedia structures and MII info */
mii->mii_ifp = ifp;
mii->mii_readreg = gem_mii_readreg;
mii->mii_writereg = gem_mii_writereg;
mii->mii_statchg = gem_mii_statchg;
ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus);
  241         /* Bad things will happen if we touch this register on ERI. */
  242         if (sc->sc_variant != GEM_SUN_ERI)
bus_space_write_4(sc->sc_bustag, sc->sc_h1,
GEM_MII_DATAPATH_MODE, 0);
gem_mifinit(sc);
  248         /* 
  249          * Look for an external PHY.
  250          */
  251         if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL;
bus_space_write_4(sc->sc_bustag, sc->sc_h1,
GEM_MIF_CONFIG, sc->sc_mif_config);
  256                 switch (sc->sc_variant) {
  257                 case GEM_SUN_ERI:
phyad = GEM_PHYAD_EXTERNAL;
  259                         break;
  260                 default:
phyad = MII_PHY_ANY;
  262                         break;
  263                 }
mii_attach(&sc->sc_dev, mii, 0xffffffff, phyad,
MII_OFFSET_ANY, 0);
  267         }
  269         /* 
  270          * Fall back on an internal PHY if no external PHY was found.
  271          */
child = LIST_FIRST(&mii->mii_phys);
  273         if (child == NULL && sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) {
sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL;
bus_space_write_4(sc->sc_bustag, sc->sc_h1,
GEM_MIF_CONFIG, sc->sc_mif_config);
  278                 switch (sc->sc_variant) {
  279                 case GEM_SUN_ERI:
  280                 case GEM_APPLE_K2_GMAC:
phyad = GEM_PHYAD_INTERNAL;
  282                         break;
  283                 case GEM_APPLE_GMAC:
phyad = GEM_PHYAD_EXTERNAL;
  285                         break;
  286                 default:
phyad = MII_PHY_ANY;
  288                         break;
  289                 }
mii_attach(&sc->sc_dev, mii, 0xffffffff, phyad,
MII_OFFSET_ANY, 0);
  293         }
  295         /* 
  296          * Try the external PCS SERDES if we didn't find any MII
  297          * devices.
  298          */
child = LIST_FIRST(&mii->mii_phys);
  300         if (child == NULL && sc->sc_variant != GEM_SUN_ERI &&
sc->sc_mif_config & (GEM_MIF_CONFIG_MDI0|GEM_MIF_CONFIG_MDI1)) {
bus_space_write_4(sc->sc_bustag, sc->sc_h1,
GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_SERDES);
bus_space_write_4(sc->sc_bustag, sc->sc_h1,
GEM_MII_SLINK_CONTROL,
GEM_MII_SLINK_LOOPBACK|GEM_MII_SLINK_EN_SYNC_D);
bus_space_write_4(sc->sc_bustag, sc->sc_h1,
GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE);
mii->mii_readreg = gem_pcs_readreg;
mii->mii_writereg = gem_pcs_writereg;
mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, MIIF_NOISOLATE);
  317         }
child = LIST_FIRST(&mii->mii_phys);
  320         if (child == NULL) {
  321                 /* No PHY attached */
ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
  324         } else {
  325                 /*
  326                  * XXX - we can really do the following ONLY if the
  327                  * phy indeed has the auto negotiation capability!!
  328                  */
ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO);
  330         }
  332         /* Check if we support GigE media. */
TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) {
  334                 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T ||
IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX ||
IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX ||
IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) {
sc->sc_flags |= GEM_GIGABIT;
  339                         break;
  340                 }
  341         }
  343         /* Attach the interface. */
if_attach(ifp);
ether_ifattach(ifp);
sc->sc_sh = shutdownhook_establish(gem_shutdown, sc);
  348         if (sc->sc_sh == NULL)
panic("gem_config: can't establish shutdownhook");
timeout_set(&sc->sc_tick_ch, gem_tick, sc);
  352         return;
  354         /*
  355          * Free any resources we've allocated during the failed attach
  356          * attempt.  Do this in reverse order and fall through.
  357          */
fail_6:
  359         for (i = 0; i < GEM_NTXDESC; i++) {
  360                 if (sc->sc_txd[i].sd_map != NULL)
bus_dmamap_destroy(sc->sc_dmatag,
sc->sc_txd[i].sd_map);
  363         }
fail_5:
  365         for (i = 0; i < GEM_NRXDESC; i++) {
  366                 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
bus_dmamap_destroy(sc->sc_dmatag,
sc->sc_rxsoft[i].rxs_dmamap);
  369         }
bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap);
fail_3:
bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap);
fail_2:
bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data,
  375             sizeof(struct gem_control_data));
fail_1:
bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg);
fail_0:
  379         return;
  380 }
  383 void
gem_tick(void *arg)
  385 {
  386         struct gem_softc *sc = arg;
  387         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mac = sc->sc_h1;
  390         int s;
  392         /* unload collisions counters */
ifp->if_collisions +=
bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) +
bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) +
bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) +
bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT);
  399         /* clear the hardware counters */
bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0);
bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0);
bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0);
bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0);
s = splnet();
mii_tick(&sc->sc_mii);
splx(s);
timeout_add(&sc->sc_tick_ch, hz);
  410 }
  412 int
gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r,
u_int32_t clr, u_int32_t set)
  415 {
  416         int i;
u_int32_t reg;
  419         for (i = TRIES; i--; DELAY(100)) {
reg = bus_space_read_4(sc->sc_bustag, h, r);
  421                 if ((reg & clr) == 0 && (reg & set) == set)
  422                         return (1);
  423         }
  425         return (0);
  426 }
  428 void
gem_reset(struct gem_softc *sc)
  430 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t h = sc->sc_h2;
  433         int s;
s = splnet();
DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname));
gem_reset_rx(sc);
gem_reset_tx(sc);
  440         /* Do a full reset */
bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX);
  442         if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
printf("%s: cannot reset device\n", sc->sc_dev.dv_xname);
splx(s);
  445 }
  448 /*
  449  * Drain the receive queue.
  450  */
  451 void
gem_rxdrain(struct gem_softc *sc)
  453 {
  454         struct gem_rxsoft *rxs;
  455         int i;
  457         for (i = 0; i < GEM_NRXDESC; i++) {
rxs = &sc->sc_rxsoft[i];
  459                 if (rxs->rxs_mbuf != NULL) {
bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap);
m_freem(rxs->rxs_mbuf);
rxs->rxs_mbuf = NULL;
  465                 }
  466         }
  467 }
  469 /*
  470  * Reset the whole thing.
  471  */
  472 void
gem_stop(struct ifnet *ifp, int disable)
  474 {
  475         struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
  476         struct gem_sxd *sd;
u_int32_t i;
DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname));
timeout_del(&sc->sc_tick_ch);
  483         /*
  484          * Mark the interface down and cancel the watchdog timer.
  485          */
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
ifp->if_timer = 0;
mii_down(&sc->sc_mii);
gem_reset_rx(sc);
gem_reset_tx(sc);
  494         /*
  495          * Release any queued transmit buffers.
  496          */
  497         for (i = 0; i < GEM_NTXDESC; i++) {
sd = &sc->sc_txd[i];
  499                 if (sd->sd_mbuf != NULL) {
bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0,
sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmatag, sd->sd_map);
m_freem(sd->sd_mbuf);
sd->sd_mbuf = NULL;
  505                 }
  506         }
sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0;
  509         if (disable)
gem_rxdrain(sc);
  511 }
  514 /*
  515  * Reset the receiver
  516  */
  517 int
gem_reset_rx(struct gem_softc *sc)
  519 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2;
  523         /*
  524          * Resetting while DMA is in progress can cause a bus hang, so we
  525          * disable DMA first.
  526          */
gem_disable_rx(sc);
bus_space_write_4(t, h, GEM_RX_CONFIG, 0);
  529         /* Wait till it finishes */
  530         if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0))
printf("%s: cannot disable rx dma\n", sc->sc_dev.dv_xname);
  532         /* Wait 5ms extra. */
delay(5000);
  535         /* Finally, reset the ERX */
bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX);
  537         /* Wait till it finishes */
  538         if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) {
printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname);
  540                 return (1);
  541         }
  542         return (0);
  543 }
  546 /*
  547  * Reset the transmitter
  548  */
  549 int
gem_reset_tx(struct gem_softc *sc)
  551 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2;
  555         /*
  556          * Resetting while DMA is in progress can cause a bus hang, so we
  557          * disable DMA first.
  558          */
gem_disable_tx(sc);
bus_space_write_4(t, h, GEM_TX_CONFIG, 0);
  561         /* Wait till it finishes */
  562         if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0))
printf("%s: cannot disable tx dma\n", sc->sc_dev.dv_xname);
  564         /* Wait 5ms extra. */
delay(5000);
  567         /* Finally, reset the ETX */
bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX);
  569         /* Wait till it finishes */
  570         if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) {
printf("%s: cannot reset transmitter\n",
sc->sc_dev.dv_xname);
  573                 return (1);
  574         }
  575         return (0);
  576 }
  578 /*
  579  * Disable receiver.
  580  */
  581 int
gem_disable_rx(struct gem_softc *sc)
  583 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t h = sc->sc_h1;
u_int32_t cfg;
  588         /* Flip the enable bit */
cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
cfg &= ~GEM_MAC_RX_ENABLE;
bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg);
  593         /* Wait for it to finish */
  594         return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
  595 }
  597 /*
  598  * Disable transmitter.
  599  */
  600 int
gem_disable_tx(struct gem_softc *sc)
  602 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t h = sc->sc_h1;
u_int32_t cfg;
  607         /* Flip the enable bit */
cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG);
cfg &= ~GEM_MAC_TX_ENABLE;
bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg);
  612         /* Wait for it to finish */
  613         return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
  614 }
  616 /*
  617  * Initialize interface.
  618  */
  619 int
gem_meminit(struct gem_softc *sc)
  621 {
  622         struct gem_rxsoft *rxs;
  623         int i, error;
  625         /*
  626          * Initialize the transmit descriptor ring.
  627          */
  628         for (i = 0; i < GEM_NTXDESC; i++) {
sc->sc_txdescs[i].gd_flags = 0;
sc->sc_txdescs[i].gd_addr = 0;
  631         }
GEM_CDTXSYNC(sc, 0, GEM_NTXDESC,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  635         /*
  636          * Initialize the receive descriptor and receive job
  637          * descriptor rings.
  638          */
  639         for (i = 0; i < GEM_NRXDESC; i++) {
rxs = &sc->sc_rxsoft[i];
  641                 if (rxs->rxs_mbuf == NULL) {
  642                         if ((error = gem_add_rxbuf(sc, i)) != 0) {
printf("%s: unable to allocate or map rx "
  644                                     "buffer %d, error = %d\n",
sc->sc_dev.dv_xname, i, error);
  646                                 /*
  647                                  * XXX Should attempt to run with fewer receive
  648                                  * XXX buffers instead of just failing.
  649                                  */
gem_rxdrain(sc);
  651                                 return (1);
  652                         }
  653                 } else
GEM_INIT_RXDESC(sc, i);
  655         }
sc->sc_rxptr = 0;
  658         return (0);
  659 }
  661 int
gem_ringsize(int sz)
  663 {
  664         switch (sz) {
  665         case 32:
  666                 return GEM_RING_SZ_32;
  667         case 64:
  668                 return GEM_RING_SZ_64;
  669         case 128:
  670                 return GEM_RING_SZ_128;
  671         case 256:
  672                 return GEM_RING_SZ_256;
  673         case 512:
  674                 return GEM_RING_SZ_512;
  675         case 1024:
  676                 return GEM_RING_SZ_1024;
  677         case 2048:
  678                 return GEM_RING_SZ_2048;
  679         case 4096:
  680                 return GEM_RING_SZ_4096;
  681         case 8192:
  682                 return GEM_RING_SZ_8192;
  683         default:
printf("gem: invalid Receive Descriptor ring size %d\n", sz);
  685                 return GEM_RING_SZ_32;
  686         }
  687 }
  689 /*
  690  * Initialization of interface; set up initialization block
  691  * and transmit/receive descriptor rings.
  692  */
  693 int
gem_init(struct ifnet *ifp)
  695 {
  697         struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t h = sc->sc_h1;
  700         int s;
u_int max_frame_size;
u_int32_t v;
s = splnet();
DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname));
  707         /*
  708          * Initialization sequence. The numbered steps below correspond
  709          * to the sequence outlined in section 6.3.5.1 in the Ethernet
  710          * Channel Engine manual (part of the PCIO manual).
  711          * See also the STP2002-STQ document from Sun Microsystems.
  712          */
  714         /* step 1 & 2. Reset the Ethernet Channel */
gem_stop(ifp, 0);
gem_reset(sc);
DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname));
  719         /* Re-initialize the MIF */
gem_mifinit(sc);
  722         /* Call MI reset function if any */
  723         if (sc->sc_hwreset)
  724                 (*sc->sc_hwreset)(sc);
  726         /* step 3. Setup data structures in host memory */
gem_meminit(sc);
  729         /* step 4. TX MAC registers & counters */
gem_init_regs(sc);
max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN;
v = (max_frame_size) | (0x2000 << 16) /* Burst size */;
bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v);
  735         /* step 5. RX MAC registers & counters */
gem_setladrf(sc);
  738         /* step 6 & 7. Program Descriptor Ring Base Addresses */
bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 
  740             (((uint64_t)GEM_CDTXADDR(sc,0)) >> 32));
bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 
  744             (((uint64_t)GEM_CDRXADDR(sc,0)) >> 32));
bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
  747         /* step 8. Global Configuration & Interrupt Mask */
bus_space_write_4(t, h, GEM_INTMASK,
  749                       ~(GEM_INTR_TX_INTME|
GEM_INTR_TX_EMPTY|
GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF|
GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS|
GEM_INTR_MAC_CONTROL|GEM_INTR_MIF|
GEM_INTR_BERR));
bus_space_write_4(t, h, GEM_MAC_RX_MASK,
GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT);
bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */
bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */
  760         /* step 9. ETX Configuration: use mostly default values */
  762         /* Enable DMA */
v = gem_ringsize(GEM_NTXDESC /*XXX*/);
bus_space_write_4(t, h, GEM_TX_CONFIG,
v|GEM_TX_CONFIG_TXDMA_EN|
  766                 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH));
bus_space_write_4(t, h, GEM_TX_KICK, 0);
  769         /* step 10. ERX Configuration */
  771         /* Encode Receive Descriptor ring size: four possible values */
v = gem_ringsize(GEM_NRXDESC /*XXX*/);
  774         /* Enable DMA */
bus_space_write_4(t, h, GEM_RX_CONFIG, 
v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)|
  777                 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN|
  778                 (0<<GEM_RX_CONFIG_CXM_START_SHFT));
  779         /*
  780          * The following value is for an OFF Threshold of about 3/4 full
  781          * and an ON Threshold of 1/4 full.
  782          */
bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
  784             (3 * sc->sc_rxfifosize / 256) |
  785             (   (sc->sc_rxfifosize / 256) << 12));
bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6);
  788         /* step 11. Configure Media */
mii_mediachg(&sc->sc_mii);
  791         /* step 12. RX_MAC Configuration Register */
v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC;
bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
  796         /* step 14. Issue Transmit Pending command */
  798         /* Call MI initialization function if any */
  799         if (sc->sc_hwinit)
  800                 (*sc->sc_hwinit)(sc);
  803         /* step 15.  Give the receiver a swift kick */
bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4);
  806         /* Start the one second timer. */
timeout_add(&sc->sc_tick_ch, hz);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
ifp->if_timer = 0;
splx(s);
  814         return (0);
  815 }
  817 void
gem_init_regs(struct gem_softc *sc)
  819 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t h = sc->sc_h1;
u_int32_t v;
  824         /* These regs are not cleared on reset */
sc->sc_inited = 0;
  826         if (!sc->sc_inited) {
  828                 /* Wooo.  Magic values. */
bus_space_write_4(t, h, GEM_MAC_IPG0, 0);
bus_space_write_4(t, h, GEM_MAC_IPG1, 8);
bus_space_write_4(t, h, GEM_MAC_IPG2, 4);
bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
  834                 /* Max frame and max burst size */
v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */;
bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v);
bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7);
bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4);
bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
  841                 /* Dunno.... */
bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
  844                     ((sc->sc_arpcom.ac_enaddr[5]<<8)|sc->sc_arpcom.ac_enaddr[4])&0x3ff);
  846                 /* Secondary MAC addr set to 0:0:0:0:0:0 */
bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
bus_space_write_4(t, h, GEM_MAC_ADDR4, 0);
bus_space_write_4(t, h, GEM_MAC_ADDR5, 0);
  850                 /* MAC control addr set to 0:1:c2:0:1:80 */
bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001);
bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200);
bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180);
  855                 /* MAC filter addr set to 0:0:0:0:0:0 */
bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0);
bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0);
bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0);
bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0);
bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0);
sc->sc_inited = 1;
  864         }
  866         /* Counters need to be zeroed */
bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0);
bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0);
bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0);
bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0);
bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0);
bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0);
bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0);
bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
  879         /* Un-pause stuff */
bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0);
  882         /*
  883          * Set the station address.
  884          */
bus_space_write_4(t, h, GEM_MAC_ADDR0, 
  886                 (sc->sc_arpcom.ac_enaddr[4]<<8) | sc->sc_arpcom.ac_enaddr[5]);
bus_space_write_4(t, h, GEM_MAC_ADDR1, 
  888                 (sc->sc_arpcom.ac_enaddr[2]<<8) | sc->sc_arpcom.ac_enaddr[3]);
bus_space_write_4(t, h, GEM_MAC_ADDR2, 
  890                 (sc->sc_arpcom.ac_enaddr[0]<<8) | sc->sc_arpcom.ac_enaddr[1]);
  893         /*
  894          * Enable MII outputs.  Enable GMII if there is a gigabit PHY.
  895          */
sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
v = GEM_MAC_XIF_TX_MII_ENA;
  898         if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
v |= GEM_MAC_XIF_FDPLX_LED;
  900                 if (sc->sc_flags & GEM_GIGABIT)
v |= GEM_MAC_XIF_GMII_MODE;
  902         }
bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
  904 }
  906 /*
  907  * Receive interrupt.
  908  */
  909 int
gem_rint(struct gem_softc *sc)
  911 {
  912         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t h = sc->sc_h1;
  915         struct ether_header *eh;
  916         struct gem_rxsoft *rxs;
  917         struct mbuf *m;
u_int64_t rxstat;
  919         int i, len;
  921         for (i = sc->sc_rxptr;; i = GEM_NEXTRX(i)) {
rxs = &sc->sc_rxsoft[i];
GEM_CDRXSYNC(sc, i,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
  929                 if (rxstat & GEM_RD_OWN) {
  930                         /*
  931                          * We have processed all of the receive buffers.
  932                          */
  933                         break;
  934                 }
  936                 if (rxstat & GEM_RD_BAD_CRC) {
  937 #ifdef GEM_DEBUG
printf("%s: receive error: CRC error\n",
sc->sc_dev.dv_xname);
  940 #endif
GEM_INIT_RXDESC(sc, i);
  942                         continue;
  943                 }
bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
  947 #ifdef GEM_DEBUG
  948                 if (ifp->if_flags & IFF_DEBUG) {
printf("    rxsoft %p descriptor %d: ", rxs, i);
printf("gd_flags: 0x%016llx\t", (long long)
GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags));
printf("gd_addr: 0x%016llx\n", (long long)
GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr));
  954                 }
  955 #endif
  957                 /* No errors; receive the packet. */
len = GEM_RD_BUFLEN(rxstat);
  960                 /*
  961                  * Allocate a new mbuf cluster.  If that fails, we are
  962                  * out of memory, and must drop the packet and recycle
  963                  * the buffer that's already attached to this descriptor.
  964                  */
m = rxs->rxs_mbuf;
  966                 if (gem_add_rxbuf(sc, i) != 0) {
ifp->if_ierrors++;
GEM_INIT_RXDESC(sc, i);
bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
  971                         continue;
  972                 }
m->m_data += 2; /* We're already off by two */
ifp->if_ipackets++;
eh = mtod(m, struct ether_header *);
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = m->m_len = len;
  980 #if NBPFILTER > 0
  981                 /*
  982                  * Pass this up to any BPF listeners, but only
  983                  * pass it up the stack if its for us.
  984                  */
  985                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
  987 #endif /* NPBFILTER > 0 */
  989                 /* Pass it on. */
ether_input_mbuf(ifp, m);
  991         }
  993         /* Update the receive pointer. */
sc->sc_rxptr = i;
bus_space_write_4(t, h, GEM_RX_KICK, i);
DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n",
sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)));
 1000         return (1);
 1001 }
 1004 /*
 1005  * Add a receive buffer to the indicated descriptor.
 1006  */
 1007 int
gem_add_rxbuf(struct gem_softc *sc, int idx)
 1009 {
 1010         struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
 1011         struct mbuf *m;
 1012         int error;
MGETHDR(m, M_DONTWAIT, MT_DATA);
 1015         if (m == NULL)
 1016                 return (ENOBUFS);
MCLGET(m, M_DONTWAIT);
 1019         if ((m->m_flags & M_EXT) == 0) {
m_freem(m);
 1021                 return (ENOBUFS);
 1022         }
 1024 #ifdef GEM_DEBUG
 1025 /* bzero the packet to check dma */
memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size);
 1027 #endif
 1029         if (rxs->rxs_mbuf != NULL)
bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap);
rxs->rxs_mbuf = m;
error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap,
m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
BUS_DMA_READ|BUS_DMA_NOWAIT);
 1037         if (error) {
printf("%s: can't load rx DMA map %d, error = %d\n",
sc->sc_dev.dv_xname, idx, error);
panic("gem_add_rxbuf"); /* XXX */
 1041         }
bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
GEM_INIT_RXDESC(sc, idx);
 1048         return (0);
 1049 }
 1052 int
gem_eint(struct gem_softc *sc, u_int status)
 1054 {
 1055         if ((status & GEM_INTR_MIF) != 0) {
 1056 #ifdef GEM_DEBUG
printf("%s: link status changed\n", sc->sc_dev.dv_xname);
 1058 #endif
 1059                 return (1);
 1060         }
printf("%s: status=%b\n", sc->sc_dev.dv_xname, status, GEM_INTR_BITS);
 1063         return (1);
 1064 }
 1066 int
gem_pint(struct gem_softc *sc)
 1068 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t seb = sc->sc_h1;
u_int32_t status;
status = bus_space_read_4(t, seb, GEM_MII_INTERRUP_STATUS);
status |= bus_space_read_4(t, seb, GEM_MII_INTERRUP_STATUS);
 1075 #ifdef GEM_DEBUG
 1076         if (status)
printf("%s: link status changed\n", sc->sc_dev.dv_xname);
 1078 #endif
 1079         return (1);
 1080 }
 1082 int
gem_intr(void *v)
 1084 {
 1085         struct gem_softc *sc = (struct gem_softc *)v;
 1086         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t seb = sc->sc_h1;
u_int32_t status;
 1090         int r = 0;
status = bus_space_read_4(t, seb, GEM_STATUS);
DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %b\n",
sc->sc_dev.dv_xname, (status>>19), status, GEM_INTR_BITS));
 1096         if ((status & GEM_INTR_PCS) != 0)
r |= gem_pint(sc);
 1099         if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0)
r |= gem_eint(sc, status);
 1102         if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
r |= gem_tint(sc, status);
 1105         if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
r |= gem_rint(sc);
 1108         /* We should eventually do more than just print out error stats. */
 1109         if (status & GEM_INTR_TX_MAC) {
 1110                 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS);
 1111 #ifdef GEM_DEBUG
 1112                 if (txstat & ~GEM_MAC_TX_XMIT_DONE)
printf("%s: MAC tx fault, status %x\n",
sc->sc_dev.dv_xname, txstat);
 1115 #endif
 1116                 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG))
gem_init(ifp);
 1118         }
 1119         if (status & GEM_INTR_RX_MAC) {
 1120                 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS);
 1121 #ifdef GEM_DEBUG
 1122                 if (rxstat & ~GEM_MAC_RX_DONE)
printf("%s: MAC rx fault, status %x\n",
sc->sc_dev.dv_xname, rxstat);
 1125 #endif
 1126                 /*
 1127                  * On some chip revisions GEM_MAC_RX_OVERFLOW happen often
 1128                  * due to a silicon bug so handle them silently.
 1129                  */
 1130                 if (rxstat & GEM_MAC_RX_OVERFLOW) {
ifp->if_ierrors++;
gem_init(ifp);
 1133                 }
 1134 #ifdef GEM_DEBUG
 1135                 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT))
printf("%s: MAC rx fault, status %x\n",
sc->sc_dev.dv_xname, rxstat);
 1138 #endif
 1139         }
 1140         return (r);
 1141 }
 1144 void
gem_watchdog(struct ifnet *ifp)
 1146 {
 1147         struct gem_softc *sc = ifp->if_softc;
DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x "
 1150                 "GEM_MAC_RX_CONFIG %x\n",
bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG),
bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS),
bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG)));
log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
 1156         ++ifp->if_oerrors;
 1158         /* Try to get more packets going. */
gem_init(ifp);
 1160 }
 1162 /*
 1163  * Initialize the MII Management Interface
 1164  */
 1165 void
gem_mifinit(struct gem_softc *sc)
 1167 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mif = sc->sc_h1;
 1171         /* Configure the MIF in frame mode */
sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA;
bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config);
 1175 }
 1177 /*
 1178  * MII interface
 1179  *
 1180  * The GEM MII interface supports at least three different operating modes:
 1181  *
 1182  * Bitbang mode is implemented using data, clock and output enable registers.
 1183  *
 1184  * Frame mode is implemented by loading a complete frame into the frame
 1185  * register and polling the valid bit for completion.
 1186  *
 1187  * Polling mode uses the frame register but completion is indicated by
 1188  * an interrupt.
 1189  *
 1190  */
 1191 int
gem_mii_readreg(struct device *self, int phy, int reg)
 1193 {
 1194         struct gem_softc *sc = (void *)self;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mif = sc->sc_h1;
 1197         int n;
u_int32_t v;
 1200 #ifdef GEM_DEBUG
 1201         if (sc->sc_debug)
printf("gem_mii_readreg: phy %d reg %d\n", phy, reg);
 1203 #endif
 1205         /* Construct the frame command */
v = (reg << GEM_MIF_REG_SHIFT)  | (phy << GEM_MIF_PHY_SHIFT) |
GEM_MIF_FRAME_READ;
bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
 1210         for (n = 0; n < 100; n++) {
DELAY(1);
v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
 1213                 if (v & GEM_MIF_FRAME_TA0)
 1214                         return (v & GEM_MIF_FRAME_DATA);
 1215         }
printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname);
 1218         return (0);
 1219 }
 1221 void
gem_mii_writereg(struct device *self, int phy, int reg, int val)
 1223 {
 1224         struct gem_softc *sc = (void *)self;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mif = sc->sc_h1;
 1227         int n;
u_int32_t v;
 1230 #ifdef GEM_DEBUG
 1231         if (sc->sc_debug)
printf("gem_mii_writereg: phy %d reg %d val %x\n",
phy, reg, val);
 1234 #endif
 1236         /* Construct the frame command */
v = GEM_MIF_FRAME_WRITE                 |
 1238             (phy << GEM_MIF_PHY_SHIFT)          |
 1239             (reg << GEM_MIF_REG_SHIFT)          |
 1240             (val & GEM_MIF_FRAME_DATA);
bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
 1243         for (n = 0; n < 100; n++) {
DELAY(1);
v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
 1246                 if (v & GEM_MIF_FRAME_TA0)
 1247                         return;
 1248         }
printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname);
 1251 }
 1253 void
gem_mii_statchg(struct device *dev)
 1255 {
 1256         struct gem_softc *sc = (void *)dev;
 1257 #ifdef GEM_DEBUG
 1258         int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
 1259 #endif
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mac = sc->sc_h1;
u_int32_t v;
 1264 #ifdef GEM_DEBUG
 1265         if (sc->sc_debug)
printf("gem_mii_statchg: status change: phy = %d\n", instance);
 1267 #endif
 1269         /* Set tx full duplex options */
bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0);
delay(10000); /* reg must be cleared and delay before changing. */
v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT|
GEM_MAC_TX_ENABLE;
 1274         if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) {
v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS;
 1276         }
bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v);
 1279         /* XIF Configuration */
 1280  /* We should really calculate all this rather than rely on defaults */
v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG);
v = GEM_MAC_XIF_LINK_LED;
v |= GEM_MAC_XIF_TX_MII_ENA;
 1284         /* If an external transceiver is connected, enable its MII drivers */
sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG);
 1286         if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
 1287                 /* External MII needs echo disable if half duplex. */
 1288                 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
 1289                         /* turn on full duplex LED */
v |= GEM_MAC_XIF_FDPLX_LED;
 1291                 else
 1292                         /* half duplex -- disable echo */
v |= GEM_MAC_XIF_ECHO_DISABL;
 1295                 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) {
 1296                 case IFM_1000_T:  /* Gigabit using GMII interface */
 1297                 case IFM_1000_SX:
v |= GEM_MAC_XIF_GMII_MODE;
 1299                         break;
 1300                 default:
v &= ~GEM_MAC_XIF_GMII_MODE;
 1302                 }
 1303         } else
 1304                 /* Internal MII needs buf enable */
v |= GEM_MAC_XIF_MII_BUF_ENA;
bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v);
 1307 }
 1309 int
gem_pcs_readreg(struct device *self, int phy, int reg)
 1311 {
 1312         struct gem_softc *sc = (void *)self;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t pcs = sc->sc_h1;
 1316 #ifdef GEM_DEBUG
 1317         if (sc->sc_debug)
printf("gem_pcs_readreg: phy %d reg %d\n", phy, reg);
 1319 #endif
 1321         if (phy != GEM_PHYAD_EXTERNAL)
 1322                 return (0);
 1324         switch (reg) {
 1325         case MII_BMCR:
reg = GEM_MII_CONTROL;
 1327                 break;
 1328         case MII_BMSR:
reg = GEM_MII_STATUS;
 1330                 break;
 1331         case MII_ANAR:
reg = GEM_MII_ANAR;
 1333                 break;
 1334         case MII_ANLPAR:
reg = GEM_MII_ANLPAR;
 1336                 break;
 1337         case MII_EXTSR:
 1338                 return (EXTSR_1000XFDX|EXTSR_1000XHDX);
 1339         default:
 1340                 return (0);
 1341         }
 1343         return bus_space_read_4(t, pcs, reg);
 1344 }
 1346 void
gem_pcs_writereg(struct device *self, int phy, int reg, int val)
 1348 {
 1349         struct gem_softc *sc = (void *)self;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t pcs = sc->sc_h1;
 1353 #ifdef GEM_DEBUG
 1354         if (sc->sc_debug)
printf("gem_pcs_writereg: phy %d reg %d val %x\n",
phy, reg, val);
 1357 #endif
 1359         if (phy != GEM_PHYAD_EXTERNAL)
 1360                 return;
 1362         switch (reg) {
 1363         case MII_BMCR:
reg = GEM_MII_CONTROL;
 1365                 break;
 1366         case MII_BMSR:
reg = GEM_MII_STATUS;
 1368                 break;
 1369         case MII_ANAR:
reg = GEM_MII_ANAR;
 1371                 break;
 1372         case MII_ANLPAR:
reg = GEM_MII_ANLPAR;
 1374                 break;
 1375         default:
 1376                 return;
 1377         }
bus_space_write_4(t, pcs, reg, val);
 1381         if (reg == GEM_MII_ANAR) {
bus_space_write_4(t, pcs, GEM_MII_SLINK_CONTROL,
GEM_MII_SLINK_LOOPBACK|GEM_MII_SLINK_EN_SYNC_D);
bus_space_write_4(t, pcs, GEM_MII_CONFIG,
GEM_MII_CONFIG_ENABLE);
 1386         }
 1387 }
 1389 int
gem_mediachange(struct ifnet *ifp)
 1391 {
 1392         struct gem_softc *sc = ifp->if_softc;
 1393         struct mii_data *mii = &sc->sc_mii;
 1395         if (mii->mii_instance) {
 1396                 struct mii_softc *miisc;
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
mii_phy_reset(miisc);
 1399         }
 1401         return (mii_mediachg(&sc->sc_mii));
 1402 }
 1404 void
gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 1406 {
 1407         struct gem_softc *sc = ifp->if_softc;
mii_pollstat(&sc->sc_mii);
ifmr->ifm_active = sc->sc_mii.mii_media_active;
ifmr->ifm_status = sc->sc_mii.mii_media_status;
 1412 }
 1414 /*
 1415  * Process an ioctl request.
 1416  */
 1417 int
gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 1419 {
 1420         struct gem_softc *sc = ifp->if_softc;
 1421         struct ifaddr *ifa = (struct ifaddr *)data;
 1422         struct ifreq *ifr = (struct ifreq *)data;
 1423         int s, error = 0;
s = splnet();
 1427         if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
splx(s);
 1429                 return (error);
 1430         }
 1432         switch (cmd) {
 1434         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
 1436                 if ((ifp->if_flags & IFF_RUNNING) == 0)
gem_init(ifp);
 1438 #ifdef INET
 1439                 if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc->sc_arpcom, ifa);
 1441 #endif
 1442                 break;
 1444         case SIOCSIFFLAGS:
 1445                 if (ifp->if_flags & IFF_UP) {
 1446                         if ((ifp->if_flags & IFF_RUNNING) &&
 1447                             ((ifp->if_flags ^ sc->sc_if_flags) &
 1448                              (IFF_ALLMULTI | IFF_PROMISC)) != 0)
gem_setladrf(sc);
 1450                         else {
 1451                                 if ((ifp->if_flags & IFF_RUNNING) == 0)
gem_init(ifp);
 1453                         }
 1454                 } else {
 1455                         if (ifp->if_flags & IFF_RUNNING)
gem_stop(ifp, 1);
 1457                 }
sc->sc_if_flags = ifp->if_flags;
 1460 #ifdef GEM_DEBUG
sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0;
 1462 #endif
 1463                 break;
 1465         case SIOCSIFMTU:
 1466                 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) {
error = EINVAL;
 1468                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
ifp->if_mtu = ifr->ifr_mtu;
 1470                 }
 1471                 break;
 1473         case SIOCADDMULTI:
 1474         case SIOCDELMULTI:
error = (cmd == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_arpcom) :
ether_delmulti(ifr, &sc->sc_arpcom);
 1479                 if (error == ENETRESET) {
 1480                         /*
 1481                          * Multicast list has changed; set the hardware filter
 1482                          * accordingly.
 1483                          */
 1484                         if (ifp->if_flags & IFF_RUNNING)
gem_setladrf(sc);
error = 0;
 1487                 }
 1488                 break;
 1490         case SIOCGIFMEDIA:
 1491         case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
 1493                 break;
 1495         default:
error = EINVAL;
 1497                 break;
 1498         }
splx(s);
 1501         return (error);
 1502 }
 1505 void
gem_shutdown(void *arg)
 1507 {
 1508         struct gem_softc *sc = (struct gem_softc *)arg;
 1509         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
gem_stop(ifp, 1);
 1512 }
 1514 /*
 1515  * Set up the logical address filter.
 1516  */
 1517 void
gem_setladrf(struct gem_softc *sc)
 1519 {
 1520         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
 1521         struct ether_multi *enm;
 1522         struct ether_multistep step;
 1523         struct arpcom *ac = &sc->sc_arpcom;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t h = sc->sc_h1;
u_int32_t crc, hash[16], v;
 1527         int i;
 1529         /* Get current RX configuration */
v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
 1533         /*
 1534          * Turn off promiscuous mode, promiscuous group mode (all multicast),
 1535          * and hash filter.  Depending on the case, the right bit will be
 1536          * enabled.
 1537          */
v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
GEM_MAC_RX_PROMISC_GRP);
 1541         if ((ifp->if_flags & IFF_PROMISC) != 0) {
 1542                 /* Turn on promiscuous mode */
v |= GEM_MAC_RX_PROMISCUOUS;
ifp->if_flags |= IFF_ALLMULTI;
 1545                 goto chipit;
 1546         }
 1548         /*
 1549          * Set up multicast address filter by passing all multicast addresses
 1550          * through a crc generator, and then using the high order 8 bits as an
 1551          * index into the 256 bit logical address filter.  The high order 4
 1552          * bits selects the word, while the other 4 bits select the bit within
 1553          * the word (where bit 0 is the MSB).
 1554          */
 1556         /* Clear hash table */
 1557         for (i = 0; i < 16; i++)
hash[i] = 0;
ETHER_FIRST_MULTI(step, ac, enm);
 1562         while (enm != NULL) {
 1563                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 1564                         /*
 1565                          * We must listen to a range of multicast addresses.
 1566                          * For now, just accept all multicasts, rather than
 1567                          * trying to set only those filter bits needed to match
 1568                          * the range.  (At this time, the only use of address
 1569                          * ranges is for IP multicast routing, for which the
 1570                          * range is big enough to require all bits set.)
 1571                          * XXX use the addr filter for this
 1572                          */
ifp->if_flags |= IFF_ALLMULTI;
v |= GEM_MAC_RX_PROMISC_GRP;
 1575                         goto chipit;
 1576                 }
crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
 1580                 /* Just want the 8 most significant bits. */
crc >>= 24;
 1583                 /* Set the corresponding bit in the filter. */
hash[crc >> 4] |= 1 << (15 - (crc & 15));
ETHER_NEXT_MULTI(step, enm);
 1587         }
v |= GEM_MAC_RX_HASH_FILTER;
ifp->if_flags &= ~IFF_ALLMULTI;
 1592         /* Now load the hash table into the chip (if we are using it) */
 1593         for (i = 0; i < 16; i++) {
bus_space_write_4(t, h,
GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
hash[i]);
 1597         }
chipit:
bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
 1601 }
 1603 int
gem_encap(struct gem_softc *sc, struct mbuf *mhead, u_int32_t *bixp)
 1605 {
u_int64_t flags;
u_int32_t cur, frag, i;
bus_dmamap_t map;
cur = frag = *bixp;
map = sc->sc_txd[cur].sd_map;
 1613         if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead,
BUS_DMA_NOWAIT) != 0) {
 1615                 return (ENOBUFS);
 1616         }
 1618         if ((sc->sc_tx_cnt + map->dm_nsegs) > (GEM_NTXDESC - 2)) {
bus_dmamap_unload(sc->sc_dmatag, map);
 1620                 return (ENOBUFS);
 1621         }
bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize,
BUS_DMASYNC_PREWRITE);
 1626         for (i = 0; i < map->dm_nsegs; i++) {
sc->sc_txdescs[frag].gd_addr =
GEM_DMA_WRITE(sc, map->dm_segs[i].ds_addr);
flags = (map->dm_segs[i].ds_len & GEM_TD_BUFSIZE) |
 1630                     (i == 0 ? GEM_TD_START_OF_PACKET : 0) |
 1631                     ((i == (map->dm_nsegs - 1)) ? GEM_TD_END_OF_PACKET : 0);
sc->sc_txdescs[frag].gd_flags = GEM_DMA_WRITE(sc, flags);
bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap,
GEM_CDTXOFF(frag), sizeof(struct gem_desc),
BUS_DMASYNC_PREWRITE);
cur = frag;
 1637                 if (++frag == GEM_NTXDESC)
frag = 0;
 1639         }
sc->sc_tx_cnt += map->dm_nsegs;
sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map;
sc->sc_txd[cur].sd_map = map;
sc->sc_txd[cur].sd_mbuf = mhead;
bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, frag);
 1648         *bixp = frag;
 1650         /* sync descriptors */
 1652         return (0);
 1653 }
 1655 /*
 1656  * Transmit interrupt.
 1657  */
 1658 int
gem_tint(struct gem_softc *sc, u_int32_t status)
 1660 {
 1661         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
 1662         struct gem_sxd *sd;
u_int32_t cons, hwcons;
hwcons = status >> 19;
cons = sc->sc_tx_cons;
 1667         while (cons != hwcons) {
sd = &sc->sc_txd[cons];
 1669                 if (sd->sd_mbuf != NULL) {
bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0,
sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmatag, sd->sd_map);
m_freem(sd->sd_mbuf);
sd->sd_mbuf = NULL;
 1675                 }
sc->sc_tx_cnt--;
ifp->if_opackets++;
 1678                 if (++cons == GEM_NTXDESC)
cons = 0;
 1680         }
sc->sc_tx_cons = cons;
gem_start(ifp);
 1685         if (sc->sc_tx_cnt == 0)
ifp->if_timer = 0;
 1688         return (1);
 1689 }
 1691 void
gem_start(struct ifnet *ifp)
 1693 {
 1694         struct gem_softc *sc = ifp->if_softc;
 1695         struct mbuf *m;
u_int32_t bix;
 1698         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
 1699                 return;
bix = sc->sc_tx_prod;
 1702         while (sc->sc_txd[bix].sd_mbuf == NULL) {
IFQ_POLL(&ifp->if_snd, m);
 1704                 if (m == NULL)
 1705                         break;
 1707 #if NBPFILTER > 0
 1708                 /*
 1709                  * If BPF is listening on this interface, let it see the
 1710                  * packet before we commit it to the wire.
 1711                  */
 1712                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
 1714 #endif
 1716                 /*
 1717                  * Encapsulate this packet and start it going...
 1718                  * or fail...
 1719                  */
 1720                 if (gem_encap(sc, m, &bix)) {
ifp->if_timer = 2;
 1722                         break;
 1723                 }
IFQ_DEQUEUE(&ifp->if_snd, m);
ifp->if_timer = 5;
 1727         }
sc->sc_tx_prod = bix;
 1730 }