root/dev/ic/gemreg.h

INCLUDED FROM

    1 /*      $OpenBSD: gemreg.h,v 1.13 2007/05/18 02:18:28 dlg Exp $ */
    2 /*      $NetBSD: gemreg.h,v 1.1 2001/09/16 00:11:43 eeh Exp $ */
    4 /*
    5  *
    6  * Copyright (C) 2001 Eduardo Horvath.
    7  * All rights reserved.
    8  *
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR  ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR  BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  *
   31  */
   33 #ifndef _IF_GEMREG_H
   34 #define _IF_GEMREG_H
   36 /* Register definitions for Sun GEM gigabit ethernet */
   38 /*
   39  * First bank: this registers live at the start of the PCI
   40  * mapping, and at the start of the second bank of the SBUS
   41  * version.
   42  */
   43 #define GEM_SEB_STATE           0x0000  /* SEB state reg, R/O */
   44 #define GEM_CONFIG              0x0004  /* config reg */
   45 #define GEM_STATUS              0x000c  /* status reg */
   46 /* Note: Reading the status reg clears bits 0-6 */
   47 #define GEM_INTMASK             0x0010
   48 #define GEM_INTACK              0x0014  /* Interrupt acknowledge, W/O */
   49 #define GEM_STATUS_ALIAS        0x001c
   51 /*
   52  * Second bank: this registers live at offset 0x1000 of the PCI
   53  * mapping, and at the start of the first bank of the SBUS
   54  * version.
   55  */
   56 #define GEM_PCI_BANK2_OFFSET    0x1000
   57 #define GEM_PCI_BANK2_SIZE      0x14
   58 /* This is the same as the GEM_STATUS reg but reading it does not clear bits. */
   59 #define GEM_ERROR_STATUS        0x0000  /* PCI error status R/C */
   60 #define GEM_ERROR_MASK          0x0004
   61 #define GEM_SBUS_CONFIG         0x0004
   62 #define GEM_BIF_CONFIG          0x0008  /* BIF config reg */
   63 #define GEM_BIF_DIAG            0x000c
   64 #define GEM_RESET               0x0010  /* Software reset register */
   66 /* Bits in GEM_SEB register */
   67 #define GEM_SEB_ARB             0x000000002     /* Arbitration status */
   68 #define GEM_SEB_RXWON           0x000000004
   70 /* Bits in GEM_SBUS_CONFIG register */
   71 #define GEM_SBUS_CFG_BMODE64    0x00000008
   72 #define GEM_SBUS_CFG_PARITY     0x00000200
   74 /* Bits in GEM_CONFIG register */
   75 #define GEM_CONFIG_BURST_64     0x000000000     /* 0->infinity, 1->64KB */
   76 #define GEM_CONFIG_BURST_INF    0x000000001     /* 0->infinity, 1->64KB */
   77 #define GEM_CONFIG_TXDMA_LIMIT  0x00000003e
   78 #define GEM_CONFIG_RXDMA_LIMIT  0x0000007c0
   80 #define GEM_CONFIG_TXDMA_LIMIT_SHIFT    1
   81 #define GEM_CONFIG_RXDMA_LIMIT_SHIFT    6
   83 /* Top part of GEM_STATUS has TX completion information */
   84 #define GEM_STATUS_TX_COMPL     0xfff800000     /* TX completion reg. */
   86 /*
   87  * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs.
   88  * Bits 0-6 auto-clear when read.
   89  */
   90 #define GEM_INTR_TX_INTME       0x000000001     /* Frame w/INTME bit set sent */
   91 #define GEM_INTR_TX_EMPTY       0x000000002     /* TX ring empty */
   92 #define GEM_INTR_TX_DONE        0x000000004     /* TX complete */
   93 #define GEM_INTR_RX_DONE        0x000000010     /* Got a packet */
   94 #define GEM_INTR_RX_NOBUF       0x000000020
   95 #define GEM_INTR_RX_TAG_ERR     0x000000040
   96 #define GEM_INTR_PCS            0x000002000     /* Physical Code Sub-layer */
   97 #define GEM_INTR_TX_MAC         0x000004000
   98 #define GEM_INTR_RX_MAC         0x000008000
   99 #define GEM_INTR_MAC_CONTROL    0x000010000     /* MAC control interrupt */
  100 #define GEM_INTR_MIF            0x000020000
  101 #define GEM_INTR_BERR           0x000040000     /* Bus error interrupt */
  102 #define GEM_INTR_BITS   "\020"                                  \
  103                         "\1INTME\2TXEMPTY\3TXDONE"              \
  104                         "\5RXDONE\6RXNOBUF\7RX_TAG_ERR"         \
  105                         "\16PCS\17TXMAC\20RXMAC"                \
  106                         "\21MACCONTROL\22MIF\23BERR"
  108 /* GEM_ERROR_STATUS and GEM_ERROR_MASK PCI error bits */
  109 #define GEM_ERROR_STAT_BADACK   0x000000001     /* No ACK64# */
  110 #define GEM_ERROR_STAT_DTRTO    0x000000002     /* Delayed xaction timeout */
  111 #define GEM_ERROR_STAT_OTHERS   0x000000004
  113 /* GEM_BIF_CONFIG register bits */
  114 #define GEM_BIF_CONFIG_SLOWCLK  0x000000001     /* Parity error timing */
  115 #define GEM_BIF_CONFIG_HOST_64  0x000000002     /* 64-bit host */
  116 #define GEM_BIF_CONFIG_B64D_DIS 0x000000004     /* no 64-bit data cycle */
  117 #define GEM_BIF_CONFIG_M66EN    0x000000008
  119 /* GEM_RESET register bits -- TX and RX self clear when complete. */
  120 #define GEM_RESET_TX            0x000000001     /* Reset TX half */
  121 #define GEM_RESET_RX            0x000000002     /* Reset RX half */
  122 #define GEM_RESET_RSTOUT        0x000000004     /* Force PCI RSTOUT# */
  124 /* GEM TX DMA registers */
  125 #define GEM_TX_KICK             0x2000          /* Write last valid desc + 1 */
  126 #define GEM_TX_CONFIG           0x2004
  127 #define GEM_TX_RING_PTR_LO      0x2008
  128 #define GEM_TX_RING_PTR_HI      0x200c
  130 #define GEM_TX_FIFO_WR_PTR      0x2014          /* FIFO write pointer */
  131 #define GEM_TX_FIFO_SDWR_PTR    0x2018          /* FIFO shadow write pointer */
  132 #define GEM_TX_FIFO_RD_PTR      0x201c          /* FIFO read pointer */
  133 #define GEM_TX_FIFO_SDRD_PTR    0x2020          /* FIFO shadow read pointer */
  134 #define GEM_TX_FIFO_PKT_CNT     0x2024          /* FIFO packet counter */
  136 #define GEM_TX_STATE_MACHINE    0x2028          /* ETX state machine reg */
  137 #define GEM_TX_DATA_PTR         0x2030          /* ETX state machine reg (64-bit)*/
  139 #define GEM_TX_COMPLETION       0x2100
  140 #define GEM_TX_FIFO_ADDRESS     0x2104
  141 #define GEM_TX_FIFO_TAG         0x2108
  142 #define GEM_TX_FIFO_DATA_LO     0x210c
  143 #define GEM_TX_FIFO_DATA_HI_T1  0x2110
  144 #define GEM_TX_FIFO_DATA_HI_T0  0x2114
  145 #define GEM_TX_FIFO_SIZE        0x2118
  146 #define GEM_TX_DEBUG            0x3028
  148 /* GEM_TX_CONFIG register bits. */
  149 #define GEM_TX_CONFIG_TXDMA_EN  0x00000001      /* TX DMA enable */
  150 #define GEM_TX_CONFIG_TXRING_SZ 0x0000001e      /* TX ring size */
  151 #define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00      /* TX fifo threshold */
  152 #define GEM_TX_CONFIG_PACED     0x00200000      /* TX_all_int modifier */
  154 #define GEM_RING_SZ_32          (0<<1)  /* 32 descriptors */
  155 #define GEM_RING_SZ_64          (1<<1)
  156 #define GEM_RING_SZ_128         (2<<1)
  157 #define GEM_RING_SZ_256         (3<<1)
  158 #define GEM_RING_SZ_512         (4<<1)
  159 #define GEM_RING_SZ_1024        (5<<1)
  160 #define GEM_RING_SZ_2048        (6<<1)
  161 #define GEM_RING_SZ_4096        (7<<1)
  162 #define GEM_RING_SZ_8192        (8<<1)
  164 /* GEM_TX_COMPLETION register bits */
  165 #define GEM_TX_COMPLETION_MASK  0x00001fff      /* # of last descriptor */
  167 /* GEM RX DMA registers */
  168 #define GEM_RX_CONFIG           0x4000
  169 #define GEM_RX_RING_PTR_LO      0x4004          /* 64-bits unaligned GAK! */
  170 #define GEM_RX_RING_PTR_HI      0x4008          /* 64-bits unaligned GAK! */
  172 #define GEM_RX_FIFO_WR_PTR      0x400c          /* FIFO write pointer */
  173 #define GEM_RX_FIFO_SDWR_PTR    0x4010          /* FIFO shadow write pointer */
  174 #define GEM_RX_FIFO_RD_PTR      0x4014          /* FIFO read pointer */
  175 #define GEM_RX_FIFO_PKT_CNT     0x4018          /* FIFO packet counter */
  177 #define GEM_RX_STATE_MACHINE    0x401c          /* ERX state machine reg */
  178 #define GEM_RX_PAUSE_THRESH     0x4020
  180 #define GEM_RX_DATA_PTR_LO      0x4024          /* ERX state machine reg */
  181 #define GEM_RX_DATA_PTR_HI      0x4028          /* Damn thing is unaligned */
  183 #define GEM_RX_KICK             0x4100          /* Write last valid desc + 1 */
  184 #define GEM_RX_COMPLETION       0x4104          /* First pending desc */
  185 #define GEM_RX_BLANKING         0x4108          /* Interrupt blanking reg */
  187 #define GEM_RX_FIFO_ADDRESS     0x410c
  188 #define GEM_RX_FIFO_TAG         0x4110
  189 #define GEM_RX_FIFO_DATA_LO     0x4114
  190 #define GEM_RX_FIFO_DATA_HI_T1  0x4118
  191 #define GEM_RX_FIFO_DATA_HI_T0  0x411c
  192 #define GEM_RX_FIFO_SIZE        0x4120
  194 /* GEM_RX_CONFIG register bits. */
  195 #define GEM_RX_CONFIG_RXDMA_EN  0x00000001      /* RX DMA enable */
  196 #define GEM_RX_CONFIG_RXRING_SZ 0x0000001e      /* RX ring size */
  197 #define GEM_RX_CONFIG_BATCH_DIS 0x00000020      /* desc batching disable */
  198 #define GEM_RX_CONFIG_FBOFF     0x00001c00      /* first byte offset */
  199 #define GEM_RX_CONFIG_CXM_START 0x000fe000      /* cksum start offset bytes */
  200 #define GEM_RX_CONFIG_FIFO_THRS 0x07000000      /* fifo threshold size */
  202 #define GEM_THRSH_64    0
  203 #define GEM_THRSH_128   1
  204 #define GEM_THRSH_256   2
  205 #define GEM_THRSH_512   3
  206 #define GEM_THRSH_1024  4
  207 #define GEM_THRSH_2048  5
  209 #define GEM_RX_CONFIG_FIFO_THRS_SHIFT   24
  210 #define GEM_RX_CONFIG_FBOFF_SHFT        10
  211 #define GEM_RX_CONFIG_CXM_START_SHFT    13
  213 /* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */
  214 #define GEM_RX_PTH_XOFF_THRESH  0x000001ff
  215 #define GEM_RX_PTH_XON_THRESH   0x07fc0000
  217 /* GEM_RX_BLANKING register bits */
  218 #define GEM_RX_BLANKING_PACKETS 0x000001ff      /* Delay intr for x packets */
  219 #define GEM_RX_BLANKING_TIME    0x03fc0000      /* Delay intr for x ticks */
  220 /* One tick is 1048 PCI clocs, or 16us at 66MHz */
  222 /* GEM_MAC registers */
  223 #define GEM_MAC_TXRESET         0x6000          /* Store 1, cleared when done */
  224 #define GEM_MAC_RXRESET         0x6004          /* ditto */
  225 #define GEM_MAC_SEND_PAUSE_CMD  0x6008
  226 #define GEM_MAC_TX_STATUS       0x6010
  227 #define GEM_MAC_RX_STATUS       0x6014
  228 #define GEM_MAC_CONTROL_STATUS  0x6018          /* MAC control status reg */
  229 #define GEM_MAC_TX_MASK         0x6020          /* TX MAC mask register */
  230 #define GEM_MAC_RX_MASK         0x6024
  231 #define GEM_MAC_CONTROL_MASK    0x6028
  232 #define GEM_MAC_TX_CONFIG       0x6030
  233 #define GEM_MAC_RX_CONFIG       0x6034
  234 #define GEM_MAC_CONTROL_CONFIG  0x6038
  235 #define GEM_MAC_XIF_CONFIG      0x603c
  236 #define GEM_MAC_IPG0            0x6040          /* inter packet gap 0 */
  237 #define GEM_MAC_IPG1            0x6044          /* inter packet gap 1 */
  238 #define GEM_MAC_IPG2            0x6048          /* inter packet gap 2 */
  239 #define GEM_MAC_SLOT_TIME       0x604c          /* slot time, bits 0-7 */
  240 #define GEM_MAC_MAC_MIN_FRAME   0x6050
  241 #define GEM_MAC_MAC_MAX_FRAME   0x6054
  242 #define GEM_MAC_PREAMBLE_LEN    0x6058
  243 #define GEM_MAC_JAM_SIZE        0x605c
  244 #define GEM_MAC_ATTEMPT_LIMIT   0x6060
  245 #define GEM_MAC_CONTROL_TYPE    0x6064
  247 #define GEM_MAC_ADDR0           0x6080          /* Normal MAC address 0 */
  248 #define GEM_MAC_ADDR1           0x6084
  249 #define GEM_MAC_ADDR2           0x6088
  250 #define GEM_MAC_ADDR3           0x608c          /* Alternate MAC address 0 */
  251 #define GEM_MAC_ADDR4           0x6090
  252 #define GEM_MAC_ADDR5           0x6094
  253 #define GEM_MAC_ADDR6           0x6098          /* Control MAC address 0 */
  254 #define GEM_MAC_ADDR7           0x609c
  255 #define GEM_MAC_ADDR8           0x60a0
  257 #define GEM_MAC_ADDR_FILTER0    0x60a4
  258 #define GEM_MAC_ADDR_FILTER1    0x60a8
  259 #define GEM_MAC_ADDR_FILTER2    0x60ac
  260 #define GEM_MAC_ADR_FLT_MASK1_2 0x60b0          /* Address filter mask 1,2 */
  261 #define GEM_MAC_ADR_FLT_MASK0   0x60b4          /* Address filter mask 0 reg */
  263 #define GEM_MAC_HASH0           0x60c0          /* Hash table 0 */
  264 #define GEM_MAC_HASH1           0x60c4
  265 #define GEM_MAC_HASH2           0x60c8
  266 #define GEM_MAC_HASH3           0x60cc
  267 #define GEM_MAC_HASH4           0x60d0
  268 #define GEM_MAC_HASH5           0x60d4
  269 #define GEM_MAC_HASH6           0x60d8
  270 #define GEM_MAC_HASH7           0x60dc
  271 #define GEM_MAC_HASH8           0x60e0
  272 #define GEM_MAC_HASH9           0x60e4
  273 #define GEM_MAC_HASH10          0x60e8
  274 #define GEM_MAC_HASH11          0x60ec
  275 #define GEM_MAC_HASH12          0x60f0
  276 #define GEM_MAC_HASH13          0x60f4
  277 #define GEM_MAC_HASH14          0x60f8
  278 #define GEM_MAC_HASH15          0x60fc
  280 #define GEM_MAC_NORM_COLL_CNT   0x6100          /* Normal collision counter */
  281 #define GEM_MAC_FIRST_COLL_CNT  0x6104          /* 1st successful collision cntr */
  282 #define GEM_MAC_EXCESS_COLL_CNT 0x6108          /* Excess collision counter */
  283 #define GEM_MAC_LATE_COLL_CNT   0x610c          /* Late collision counter */
  284 #define GEM_MAC_DEFER_TMR_CNT   0x6110          /* defer timer counter */
  285 #define GEM_MAC_PEAK_ATTEMPTS   0x6114
  286 #define GEM_MAC_RX_FRAME_COUNT  0x6118
  287 #define GEM_MAC_RX_LEN_ERR_CNT  0x611c
  288 #define GEM_MAC_RX_ALIGN_ERR    0x6120
  289 #define GEM_MAC_RX_CRC_ERR_CNT  0x6124
  290 #define GEM_MAC_RX_CODE_VIOL    0x6128
  291 #define GEM_MAC_RANDOM_SEED     0x6130
  292 #define GEM_MAC_MAC_STATE       0x6134          /* MAC sstate machine reg */
  294 /* GEM_MAC_SEND_PAUSE_CMD register bits */
  295 #define GEM_MAC_PAUSE_CMD_TIME  0x0000ffff
  296 #define GEM_MAC_PAUSE_CMD_SEND  0x00010000
  298 /* GEM_MAC_TX_STATUS and _MASK register bits */
  299 #define GEM_MAC_TX_XMIT_DONE    0x00000001
  300 #define GEM_MAC_TX_UNDERRUN     0x00000002
  301 #define GEM_MAC_TX_PKT_TOO_LONG 0x00000004
  302 #define GEM_MAC_TX_NCC_EXP      0x00000008      /* Normal collision cnt exp */
  303 #define GEM_MAC_TX_ECC_EXP      0x00000010
  304 #define GEM_MAC_TX_LCC_EXP      0x00000020
  305 #define GEM_MAC_TX_FCC_EXP      0x00000040
  306 #define GEM_MAC_TX_DEFER_EXP    0x00000080
  307 #define GEM_MAC_TX_PEAK_EXP     0x00000100
  309 /* GEM_MAC_RX_STATUS and _MASK register bits */
  310 #define GEM_MAC_RX_DONE         0x00000001
  311 #define GEM_MAC_RX_OVERFLOW     0x00000002
  312 #define GEM_MAC_RX_FRAME_CNT    0x00000004
  313 #define GEM_MAC_RX_ALIGN_EXP    0x00000008
  314 #define GEM_MAC_RX_CRC_EXP      0x00000010
  315 #define GEM_MAC_RX_LEN_EXP      0x00000020
  316 #define GEM_MAC_RX_CVI_EXP      0x00000040      /* Code violation */
  318 /* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */
  319 #define GEM_MAC_PAUSED          0x00000001      /* Pause received */
  320 #define GEM_MAC_PAUSE           0x00000002      /* enter pause state */
  321 #define GEM_MAC_RESUME          0x00000004      /* exit pause state */
  322 #define GEM_MAC_PAUSE_TIME      0xffff0000
  324 /* GEM_MAC_XIF_CONFIG register bits */
  325 #define GEM_MAC_XIF_TX_MII_ENA  0x00000001      /* Enable XIF output drivers */
  326 #define GEM_MAC_XIF_MII_LOOPBK  0x00000002      /* Enable MII loopback mode */
  327 #define GEM_MAC_XIF_ECHO_DISABL 0x00000004      /* Disable echo */
  328 #define GEM_MAC_XIF_GMII_MODE   0x00000008      /* Select GMII/MII mode */
  329 #define GEM_MAC_XIF_MII_BUF_ENA 0x00000010      /* Enable MII recv buffers */
  330 #define GEM_MAC_XIF_LINK_LED    0x00000020      /* force link LED active */
  331 #define GEM_MAC_XIF_FDPLX_LED   0x00000040      /* force FDPLX LED active */
  333 /* GEM_MAC_SLOT_TIME register bits */
  334 #define GEM_MAC_SLOT_INT        0x40
  335 #define GEM_MAC_SLOT_EXT        0x200           /* external phy */
  337 /* GEM_MAC_TX_CONFIG register bits */
  338 #define GEM_MAC_TX_ENABLE       0x00000001      /* TX enable */
  339 #define GEM_MAC_TX_IGN_CARRIER  0x00000002      /* Ignore carrier sense */
  340 #define GEM_MAC_TX_IGN_COLLIS   0x00000004      /* ignore collisions */
  341 #define GEM_MAC_TX_ENA_IPG0     0x00000008      /* extend Rx-to-TX IPG */
  342 #define GEM_MAC_TX_NGU          0x00000010      /* Never give up */
  343 #define GEM_MAC_TX_NGU_LIMIT    0x00000020      /* Never give up limit */
  344 #define GEM_MAC_TX_NO_BACKOFF   0x00000040
  345 #define GEM_MAC_TX_SLOWDOWN     0x00000080
  346 #define GEM_MAC_TX_NO_FCS       0x00000100      /* no FCS will be generated */
  347 #define GEM_MAC_TX_CARR_EXTEND  0x00000200      /* Ena TX Carrier Extension */
  348 /* Carrier Extension is required for half duplex Gbps operation */
  350 /* GEM_MAC_RX_CONFIG register bits */
  351 #define GEM_MAC_RX_ENABLE       0x00000001      /* RX enable */
  352 #define GEM_MAC_RX_STRIP_PAD    0x00000002      /* strip pad bytes */
  353 #define GEM_MAC_RX_STRIP_CRC    0x00000004
  354 #define GEM_MAC_RX_PROMISCUOUS  0x00000008      /* promiscuous mode */
  355 #define GEM_MAC_RX_PROMISC_GRP  0x00000010      /* promiscuous group mode */
  356 #define GEM_MAC_RX_HASH_FILTER  0x00000020      /* enable hash filter */
  357 #define GEM_MAC_RX_ADDR_FILTER  0x00000040      /* enable address filter */
  358 #define GEM_MAC_RX_ERRCHK_DIS   0x00000080      /* disable error checking */
  359 #define GEM_MAC_RX_CARR_EXTEND  0x00000100      /* Ena RX Carrier Extension */
  360 /*
  361  * Carrier Extension enables reception of packet bursts generated by
  362  * senders with carrier extension enabled.
  363  */
  365 /* GEM_MAC_CONTROL_CONFIG bits */
  366 #define GEM_MAC_CC_TX_PAUSE     0x00000001      /* send pause enabled */
  367 #define GEM_MAC_CC_RX_PAUSE     0x00000002      /* receive pause enabled */
  368 #define GEM_MAC_CC_PASS_PAUSE   0x00000004      /* pass pause up */
  370 /* GEM MIF registers */
  371 /* Bit bang registers use low bit only */
  372 #define GEM_MIF_BB_CLOCK        0x6200          /* bit bang clock */
  373 #define GEM_MIF_BB_DATA         0x6204          /* bit bang data */
  374 #define GEM_MIF_BB_OUTPUT_ENAB  0x6208
  375 #define GEM_MIF_FRAME           0x620c          /* MIF frame - ctl and data */
  376 #define GEM_MIF_CONFIG          0x6210
  377 #define GEM_MIF_INTERRUPT_MASK  0x6214
  378 #define GEM_MIF_BASIC_STATUS    0x6218
  379 #define GEM_MIF_STATE_MACHINE   0x621c
  381 /* GEM_MIF_FRAME bits */
  382 #define GEM_MIF_FRAME_DATA      0x0000ffff
  383 #define GEM_MIF_FRAME_TA0       0x00010000      /* TA bit, 1 for completion */
  384 #define GEM_MIF_FRAME_TA1       0x00020000      /* TA bits */
  385 #define GEM_MIF_FRAME_REG_ADDR  0x007c0000
  386 #define GEM_MIF_FRAME_PHY_ADDR  0x0f800000      /* phy address, should be 0 */
  387 #define GEM_MIF_FRAME_OP        0x30000000      /* operation - write/read */
  388 #define GEM_MIF_FRAME_START     0xc0000000      /* START bits */
  390 #define GEM_MIF_FRAME_READ      0x60020000
  391 #define GEM_MIF_FRAME_WRITE     0x50020000
  393 #define GEM_MIF_REG_SHIFT       18
  394 #define GEM_MIF_PHY_SHIFT       23
  396 /* GEM_MIF_CONFIG register bits */
  397 #define GEM_MIF_CONFIG_PHY_SEL  0x00000001      /* PHY select, 0=MDIO0 */
  398 #define GEM_MIF_CONFIG_POLL_ENA 0x00000002      /* poll enable */
  399 #define GEM_MIF_CONFIG_BB_ENA   0x00000004      /* bit bang enable */
  400 #define GEM_MIF_CONFIG_REG_ADR  0x000000f8      /* poll register address */
  401 #define GEM_MIF_CONFIG_MDI0     0x00000100      /* MDIO_0 Data/MDIO_0 atached */
  402 #define GEM_MIF_CONFIG_MDI1     0x00000200      /* MDIO_1 Data/MDIO_1 atached */
  403 #define GEM_MIF_CONFIG_PHY_ADR  0x00007c00      /* poll PHY address */
  404 /* MDI0 is onboard transceiver MDI1 is external, PHYAD for both is 0 */
  406 /* GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK bits */
  407 #define GEM_MIF_STATUS          0x0000ffff
  408 #define GEM_MIF_BASIC           0xffff0000
  409 /*
  410  * The Basic part is the last value read in the POLL field of the config
  411  * register.
  412  *
  413  * The status part indicates the bits that have changed.
  414  */
  416 /* The GEM PCS/Serial link registers. */
  417 /* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */
  418 #define GEM_MII_CONTROL         0x9000
  419 #define GEM_MII_STATUS          0x9004
  420 #define GEM_MII_ANAR            0x9008          /* MII advertisement reg */
  421 #define GEM_MII_ANLPAR          0x900c          /* Link Partner Ability Reg */
  422 #define GEM_MII_CONFIG          0x9010
  423 #define GEM_MII_STATE_MACHINE   0x9014
  424 #define GEM_MII_INTERRUP_STATUS 0x9018          /* PCS interrupt state */
  425 #define GEM_MII_DATAPATH_MODE   0x9050
  426 #define GEM_MII_SLINK_CONTROL   0x9054          /* Serial link control */
  427 #define GEM_MII_OUTPUT_SELECT   0x9058
  428 #define GEM_MII_SLINK_STATUS    0x905c          /* serial link status */
  430 /* GEM_MII_CONTROL bits */
  431 /* 
  432  * DO NOT TOUCH THIS REGISTER ON ERI -- IT HARD HANGS.
  433  */
  434 #define GEM_MII_CONTROL_RESET   0x00008000
  435 #define GEM_MII_CONTROL_LOOPBK  0x00004000      /* 10-bit i/f loopback */
  436 #define GEM_MII_CONTROL_1000M   0x00002000      /* speed select, always 0 */
  437 #define GEM_MII_CONTROL_AUTONEG 0x00001000      /* auto negotiation enabled */
  438 #define GEM_MII_CONTROL_POWERDN 0x00000800
  439 #define GEM_MII_CONTROL_ISOLATE 0x00000400      /* isolate phy from mii */
  440 #define GEM_MII_CONTROL_RAN     0x00000200      /* restart auto negotiation */
  441 #define GEM_MII_CONTROL_FDUPLEX 0x00000100      /* full duplex, always 0 */
  442 #define GEM_MII_CONTROL_COL_TST 0x00000080      /* collision test */
  444 /* GEM_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */
  445 #define GEM_MII_STATUS_GB_FDX   0x00000400      /* can perform GBit FDX */
  446 #define GEM_MII_STATUS_GB_HDX   0x00000200      /* can perform GBit HDX */
  447 #define GEM_MII_STATUS_UNK      0x00000100
  448 #define GEM_MII_STATUS_ANEG_CPT 0x00000020      /* auto negotiate compete */
  449 #define GEM_MII_STATUS_REM_FLT  0x00000010      /* remote fault detected */
  450 #define GEM_MII_STATUS_ACFG     0x00000008      /* can auto negotiate */
  451 #define GEM_MII_STATUS_LINK_STS 0x00000004      /* link status */
  452 #define GEM_MII_STATUS_JABBER   0x00000002      /* jabber condition detected */
  453 #define GEM_MII_STATUS_EXTCAP   0x00000001      /* extended register capability */
  455 /* GEM_MII_ANAR and GEM_MII_ANLPAR reg bits */
  456 #define GEM_MII_ANEG_NP         0x00008000      /* next page bit */
  457 #define GEM_MII_ANEG_ACK        0x00004000      /* ack reception of */
  458                                                 /* Link Partner Capability */
  459 #define GEM_MII_ANEG_RF         0x00003000      /* advertise remote fault cap */
  460 #define GEM_MII_ANEG_ASYM_PAUSE 0x00000100      /* asymmetric pause */
  461 #define GEM_MII_ANEG_SYM_PAUSE  0x00000080      /* symmetric pause */
  462 #define GEM_MII_ANEG_HLF_DUPLX  0x00000040
  463 #define GEM_MII_ANEG_FUL_DUPLX  0x00000020
  465 /* GEM_MII_CONFIG reg */
  466 #define GEM_MII_CONFIG_TIMER    0x0000000e      /* link monitor timer values */
  467 #define GEM_MII_CONFIG_ANTO     0x00000020      /* 10ms ANEG timer override */
  468 #define GEM_MII_CONFIG_JS       0x00000018      /* Jitter Study, 0 normal
  469                                                  * 1 high freq, 2 low freq */
  470 #define GEM_MII_CONFIG_SDL      0x00000004      /* Signal Detect active low */
  471 #define GEM_MII_CONFIG_SDO      0x00000002      /* Signal Detect Override */
  472 #define GEM_MII_CONFIG_ENABLE   0x00000001      /* Enable PCS */
  474 /*
  475  * GEM_MII_STATE_MACHINE
  476  * XXX These are best guesses from observed behavior.
  477  */
  478 #define GEM_MII_FSM_STOP        0x00000000      /* stopped */
  479 #define GEM_MII_FSM_RUN         0x00000001      /* running */
  480 #define GEM_MII_FSM_UNKWN       0x00000100      /* unknown */
  481 #define GEM_MII_FSM_DONE        0x00000101      /* complete */
  483 /*
  484  * GEM_MII_INTERRUP_STATUS reg
  485  * No mask register; mask with the global interrupt mask register.
  486  */
  487 #define GEM_MII_INTERRUP_LINK   0x00000002      /* PCS link status change */
  489 /* GEM_MII_DATAPATH_MODE reg */
  490 #define GEM_MII_DATAPATH_SERIAL 0x00000001      /* Serial link */
  491 #define GEM_MII_DATAPATH_SERDES 0x00000002      /* Use PCS via 10bit interfac */
  492 #define GEM_MII_DATAPATH_MII    0x00000004      /* Use {G}MII, not PCS */
  493 #define GEM_MII_DATAPATH_MIIOUT 0x00000008      /* enable serial output on GMII */
  495 /* GEM_MII_SLINK_CONTROL reg */
  496 #define GEM_MII_SLINK_LOOPBACK  0x00000001      /* enable loopback at sl, logic
  497                                                  * reversed for SERDES */
  498 #define GEM_MII_SLINK_EN_SYNC_D 0x00000002      /* enable sync detection */
  499 #define GEM_MII_SLINK_LOCK_REF  0x00000004      /* lock reference clock */
  500 #define GEM_MII_SLINK_EMPHASIS  0x00000008      /* enable emphasis */
  501 #define GEM_MII_SLINK_SELFTEST  0x000001c0
  502 #define GEM_MII_SLINK_POWER_OFF 0x00000200      /* Power down serial link */
  504 /* GEM_MII_SLINK_STATUS reg */
  505 #define GEM_MII_SLINK_TEST      0x00000000      /* undergoing test */
  506 #define GEM_MII_SLINK_LOCKED    0x00000001      /* waiting 500us lockrefn */
  507 #define GEM_MII_SLINK_COMMA     0x00000002      /* waiting for comma detect */
  508 #define GEM_MII_SLINK_SYNC      0x00000003      /* recv data synchronized */
  510 /* Wired GEM PHY addresses */
  511 #define GEM_PHYAD_INTERNAL      1
  512 #define GEM_PHYAD_EXTERNAL      0
  514 /*
  515  * GEM descriptor table structures.
  516  */
  517 struct gem_desc {
uint64_t        gd_flags;
uint64_t        gd_addr;
  520 };
  522 /* Transmit flags */
  523 #define GEM_TD_BUFSIZE          0x0000000000007fffLL
  524 #define GEM_TD_CXSUM_START      0x00000000001f8000LL    /* Cxsum start offset */
  525 #define GEM_TD_CXSUM_STARTSHFT  15
  526 #define GEM_TD_CXSUM_STUFF      0x000000001fe00000LL    /* Cxsum stuff offset */
  527 #define GEM_TD_CXSUM_STUFFSHFT  21
  528 #define GEM_TD_CXSUM_ENABLE     0x0000000020000000LL    /* Cxsum generation enable */
  529 #define GEM_TD_END_OF_PACKET    0x0000000040000000LL
  530 #define GEM_TD_START_OF_PACKET  0x0000000080000000LL
  531 #define GEM_TD_INTERRUPT_ME     0x0000000100000000LL    /* Interrupt me now */
  532 #define GEM_TD_NO_CRC           0x0000000200000000LL    /* do not insert crc */
  533 /*
  534  * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF,
  535  * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group.
  536  */
  538 /* Receive flags */
  539 #define GEM_RD_CHECKSUM         0x000000000000ffffLL    /* is the complement */
  540 #define GEM_RD_BUFSIZE          0x000000007fff0000LL
  541 #define GEM_RD_OWN              0x0000000080000000LL    /* 1 - owned by h/w */
  542 #define GEM_RD_HASHVAL          0x0ffff00000000000LL
  543 #define GEM_RD_HASH_PASS        0x1000000000000000LL    /* passed hash filter */
  544 #define GEM_RD_ALTERNATE_MAC    0x2000000000000000LL    /* Alternate MAC adrs */
  545 #define GEM_RD_BAD_CRC          0x4000000000000000LL
  547 #define GEM_RD_BUFSHIFT         16
  548 #define GEM_RD_BUFLEN(x)        (((x)&GEM_RD_BUFSIZE)>>GEM_RD_BUFSHIFT)
  550 #endif /* _IF_GEMREG_H */