root/dev/ic/pdqreg.h

INCLUDED FROM

DEFINITIONS

1. pdq_fwrev_t
2. PDQ_SUB_CMD_LINK_UNINIT
3. PDQ_SUB_CMD_DMA_BURST_SIZE_SET
4. PDQ_SUB_CMD_PDQ_REV_GET
5. pdq_sub_cmd_t
6. PDQ_DMA_BURST_4LW
7. PDQ_DMA_BURST_8LW
8. PDQ_DMA_BURST_16LW
9. PDQ_DMA_BURST_32LW
10. pdq_dma_burst_size_t
11. PDQ_CHIP_REV_A_B_OR_C
12. PDQ_CHIP_REV_D
13. PDQ_CHIP_REV_E
14. pdq_chip_rev_t
15. PDQH_SELFTEST_TIMEOUT
16. PDQH_HOST_BUS_PARITY_ERROR
17. PDQH_HOST_DIRECTED_HALT
18. PDQH_SOFTWARE_FAULT
19. PDQH_HARDWARE_FAULT
20. PDQH_PC_TRACE_PATH_TEST
21. PDQH_DMA_ERROR
22. PDQH_IMAGE_CRC_ERROR
23. PDQH_ADAPTER_PROCESSOR_ERROR
24. PDQH_MAX
25. pdq_halt_code_t
26. pdq_consumer_block_t
27. pdq_rxdesc_t
28. pdq_rxstatus_t
29. pdq_txdesc_t
30. pdq_descriptor_block_t
31. pdq_command_info_t
32. pdq_unsolicited_info_t
33. pdq_databuf_queue_t
34. pdq_rx_info_t
35. pdq_tx_info_t
36. PDQC_START
37. PDQC_FILTER_SET
38. PDQC_FILTER_GET
39. PDQC_CHARS_SET
40. PDQC_STATUS_CHARS_GET
41. PDQC_COUNTERS_GET
42. PDQC_COUNTERS_SET
43. PDQC_ADDR_FILTER_SET
44. PDQC_ADDR_FILTER_GET
45. PDQC_ERROR_LOG_CLEAR
46. PDQC_ERROR_LOG_GET
47. PDQC_FDDI_MIB_GET
48. PDQC_DEC_EXT_MIB_GET
49. PDQC_DEV_SPECIFIC_GET
50. PDQC_SNMP_SET
51. PDQC_SMT_MIB_GET
52. PDQC_SMT_MIB_SET
53. pdq_cmd_code_t
54. PDQR_SUCCESS
55. PDQR_FAILURE
56. PDQR_WARNING
57. PDQR_LOOP_MODE_BAD
58. PDQR_ITEM_CODE_BAD
59. PDQR_TVX_BAD
60. PDQR_TREQ_BAD
61. PDQR_RESTRICTED_TOKEN_BAD
62. PDQR_NO_EOL
63. PDQR_FILTER_STATE_BAD
64. PDQR_CMD_TYPE_BAD
65. PDQR_ADAPTER_STATE_BAD
66. PDQR_RING_PURGER_BAD
67. PDQR_LEM_THRESHOLD_BAD
68. PDQR_LOOP_NOT_SUPPORTED
69. PDQR_FLUSH_TIME_BAD
70. PDQR_NOT_YET_IMPLEMENTED
71. PDQR_CONFIG_POLICY_BAD
72. PDQR_STATION_ACTION_BAD
73. PDQR_MAC_ACTION_BAD
74. PDQR_CON_POLICIES_BAD
75. PDQR_MAC_LOOP_TIME_BAD
76. PDQR_TB_MAX_BAD
77. PDQR_LER_CUTOFF_BAD
78. PDQR_LER_ALARM_BAD
79. PDQR_MAC_PATHS_REQ_BAD
80. PDQR_MAC_T_REQ_BAD
81. PDQR_EMAC_RING_PURGER_BAD
82. PDQR_EMAC_RTOKEN_TIMOUT_AD
83. PDQR_NO_SUCH_ENTRY
84. PDQR_T_NOTIFY_BAD
85. PDQR_TR_MAX_EXP_BAD
86. PDQR_FRAME_ERR_THRESHOLD_BAD
87. PDQR_MAX_TREQ_BAD
88. PDQR_FULL_DUPLEX_ENABLE_BAD
89. PDQR_ITEM_INDEX_BAD
90. pdq_response_code_t
91. PDQI_EOL
92. PDQI_T_REQ
93. PDQI_TVX
94. PDQI_RESTRICTED_TOKEN
95. PDQI_LEM_THRESHOLD
96. PDQI_RING_PURGER
97. PDQI_COUNTER_INTERVAL
98. PDQI_IND_GROUP_PROM
99. PDQI_GROUP_PROM
100. PDQI_BROADCAST
101. PDQI_SMT_PROM
102. PDQI_SMT_USER
103. PDQI_RESERVED
104. PDQI_IMPLEMENTOR
105. PDQI_LOOPBACK_MODE
106. PDQI_SMT_CONFIG_POLICY
107. PDQI_SMT_CONNECTION_POLICY
108. PDQI_SMT_T_NOTIFY
109. PDQI_SMT_STATION_ACTION
110. PDQI_MAC_PATHS_REQUESTED
111. PDQI_MAC_ACTION
112. PDQI_PORT_CONNECTION_POLICIES
113. PDQI_PORT_PATHS_REQUESTED
114. PDQI_PORT_MAC_LOOP_TIME
115. PDQI_PORT_TB_MAX
116. PDQI_PORT_LER_CUTOFF
117. PDQI_PORT_LER_ALARM
118. PDQI_PORT_ACTION
119. PDQI_FLUSH_TIME
120. PDQI_SMT_USER_DATA
121. PDQI_SMT_STATUS_REPORT_POLICY
122. PDQI_SMT_TRACE_MAX_EXPIRATION
123. PDQI_MAC_FRAME_ERR_THRESHOLD
124. PDQI_MAC_UNIT_DATA_ENABLE
125. PDQI_PATH_TVX_LOWER_BOUND
126. PDQI_PATH_TMAX_LOWER_BOUND
127. PDQI_PATH_MAX_TREQ
128. PDQI_MAC_TREQ
129. PDQI_EMAC_RING_PURGER
130. PDQI_EMAC_RTOKEN_TIMEOUT
131. PDQI_FULL_DUPLEX_ENABLE
132. pdq_item_code_t
133. PDQ_FILTER_BLOCK
134. PDQ_FILTER_PASS
135. pdq_filter_state_t
136. PDQ_STATION_TYPE_SAS
137. PDQ_STATION_TYPE_DAC
138. PDQ_STATION_TYPE_SAC
139. PDQ_STATION_TYPE_NAC
140. PDQ_STATION_TYPE_DAS
141. pdq_station_type_t
142. PDQ_STATION_STATE_OFF
143. PDQ_STATION_STATE_ON
144. PDQ_STATION_STATE_LOOPBACK
145. pdq_station_state_t
146. PDQ_LINK_STATE_OFF_READY
147. PDQ_LINK_STATE_OFF_FAULT_RECOVERY
148. PDQ_LINK_STATE_ON_RING_INIT
149. PDQ_LINK_STATE_ON_RING_RUN
150. PDQ_LINK_STATE_BROKEN
151. pdq_link_state_t
152. PDQ_DA_TEST_STATE_UNKNOWN
153. PDQ_DA_TEST_STATE_SUCCESS
154. PDQ_DA_TEST_STATE_DUPLICATE
155. pdq_da_test_state_t
156. PDQ_RING_PURGER_STATE_OFF
157. PDQ_RING_PURGER_STATE_CANDIDATE
158. PDQ_RING_PURGER_STATE_NON_PURGER
159. PDQ_RING_PURGER_STATE_PURGER
160. pdq_ring_purger_state_t
161. PDQ_FRAME_STRING_MODE_SA_MATCH
162. PDQ_FRAME_STRING_MODE_FCI_STRIP
163. pdq_frame_strip_mode_t
164. PDQ_RING_ERROR_REASON_NO_ERROR
165. PDQ_RING_ERROR_REASON_RING_INIT_INITIATED
166. PDQ_RING_ERROR_REASON_RING_INIT_RECEIVED
167. PDQ_RING_ERROR_REASON_RING_BEACONING_INITIATED
168. PDQ_RING_ERROR_REASON_DUPLICATE_ADDRESS_DETECTED
169. PDQ_RING_ERROR_REASON_DUPLICATE_TOKEN_DETECTED
170. PDQ_RING_ERROR_REASON_RING_PURGER_ERROR
171. PDQ_RING_ERROR_REASON_FCI_STRIP_ERROR
172. PDQ_RING_ERROR_REASON_RING_OP_OSCILLATION
173. PDQ_RING_ERROR_REASON_DIRECTED_BEACON_RECEVIED
174. PDQ_RING_ERROR_REASON_PC_TRACE_INITIATED
175. PDQ_RING_ERROR_REASON_PC_TRACE_RECEVIED
176. pdq_ring_error_reason_t
177. PDQ_STATION_MODE_NORMAL
178. PDQ_STATION_MODE_INTERNAL_LOOPBACK
179. pdq_station_mode_t
180. PDQ_PHY_TYPE_A
181. PDQ_PHY_TYPE_B
182. PDQ_PHY_TYPE_S
183. PDQ_PHY_TYPE_M
184. PDQ_PHY_TYPE_UNKNOWN
185. pdq_phy_type_t
186. PDQ_PMD_TYPE_ANSI_MUTLI_MODE
187. PDQ_PMD_TYPE_ANSI_SINGLE_MODE_TYPE_1
188. PDQ_PMD_TYPE_ANSI_SIGNLE_MODE_TYPE_2
189. PDQ_PMD_TYPE_ANSI_SONET
190. PDQ_PMD_TYPE_LOW_POWER
191. PDQ_PMD_TYPE_THINWIRE
192. PDQ_PMD_TYPE_SHIELDED_TWISTED_PAIR
193. PDQ_PMD_TYPE_UNSHIELDED_TWISTED_PAIR
194. pdq_pmd_type_t
195. PDQ_PMD_CLASS_ANSI_MULTI_MODE
196. PDQ_PMD_CLASS_SINGLE_MODE_TYPE_1
197. PDQ_PMD_CLASS_SINGLE_MODE_TYPE_2
198. PDQ_PMD_CLASS_SONET
199. PDQ_PMD_CLASS_LOW_COST_POWER_FIBER
200. PDQ_PMD_CLASS_TWISTED_PAIR
201. PDQ_PMD_CLASS_UNKNOWN
202. PDQ_PMD_CLASS_UNSPECIFIED
203. pdq_pmd_class_t
204. PDQ_PHY_STATE_INTERNAL_LOOPBACK
205. PDQ_PHY_STATE_BROKEN
206. PDQ_PHY_STATE_OFF_READY
207. PDQ_PHY_STATE_WAITING
208. PDQ_PHY_STATE_STARTING
209. PDQ_PHY_STATE_FAILED
210. PDQ_PHY_STATE_WATCH
211. PDQ_PHY_STATE_INUSE
212. pdq_phy_state_t
213. PDQ_REJECT_REASON_NONE
214. PDQ_REJECT_REASON_LOCAL_LCT
215. PDQ_REJECT_REASON_REMOTE_LCT
216. PDQ_REJECT_REASON_LCT_BOTH_SIDES
217. PDQ_REJECT_REASON_LEM_REJECT
218. PDQ_REJECT_REASON_TOPOLOGY_ERROR
219. PDQ_REJECT_REASON_NOISE_REJECT
220. PDQ_REJECT_REASON_REMOTE_REJECT
221. PDQ_REJECT_REASON_TRACE_IN_PROGRESS
222. PDQ_REJECT_REASON_TRACE_RECEIVED_DISABLED
223. PDQ_REJECT_REASON_STANDBY
224. PDQ_REJECT_REASON_LCT_PROTOCOL_ERROR
225. pdq_reject_reason_t
226. PDQ_BROKEN_REASON_NONE
227. pdq_broken_reason_t
228. PDQ_RI_REASON_TVX_EXPIRED
229. PDQ_RI_REASON_TRT_EXPIRED
230. PDQ_RI_REASON_RING_PURGER_ELECTION_ATTEMPT_LIMIT_EXCEEDED
231. PDQ_RI_REASON_PURGE_ERROR_LIMIT_EXCEEDED
232. PDQ_RI_REASON_RESTRICTED_TOKEN_TIMEOUT
233. pdq_ri_reason_t
234. PDQ_LCT_DIRECTION_LOCAL_LCT
235. PDQ_LCT_DIRECTION_REMOTE_LCT
236. PDQ_LCT_DIRECTION_LCT_BOTH_SIDES
237. pdq_lct_direction_t
238. PDQ_PORT_A
239. PDQ_PORT_B
240. pdq_port_type_t
241. pdq_station_id_t
242. pdq_cmd_generic_t
243. pdq_response_generic_t
244. pdq_cmd_filter_set_t
245. pdq_response_filter_get_t
246. pdq_cmd_chars_set_t
247. pdq_cmd_addr_filter_set_t
248. pdq_response_addr_filter_get_t
249. pdq_response_status_chars_get_t
250. pdq_response_fddi_mib_get_t
251. PDQ_FDX_STATE_IDLE
252. PDQ_FDX_STATE_REQUEST
253. PDQ_FDX_STATE_CONFIRM
254. PDQ_FDX_STATE_OPERATION
255. pdq_fdx_state_t
256. pdq_response_dec_ext_mib_get_t
257. PDQ_CALLER_ID_NONE
258. PDQ_CALLER_ID_SELFTEST
259. PDQ_CALLER_ID_MFG
260. PDQ_CALLER_ID_FIRMWARE
261. PDQ_CALLER_ID_CONSOLE
262. pdq_caller_id_t
263. pdq_response_error_log_get_t
264. PDQ_UNSOLICITED_EVENT
265. PDQ_UNSOLICITED_COUNTERS
266. pdq_event_t
267. PDQ_ENTITY_STATION
268. PDQ_ENTITY_LINK
269. PDQ_ENTITY_PHY_PORT
270. pdq_entity_t
271. PDQ_STATION_EVENT_TRACE_RECEIVED
272. pdq_station_event_t
273. PDQ_STATION_EVENT_ARGUMENT_REASON
274. PDQ_STATION_EVENT_ARGUMENT_EOL
275. pdq_station_event_argument_t
276. PDQ_LINK_EVENT_TRANSMIT_UNDERRUN
277. PDQ_LINK_EVENT_TRANSMIT_FAILED
278. PDQ_LINK_EVENT_BLOCK_CHECK_ERROR
279. PDQ_LINK_EVENT_FRAME_STATUS_ERROR
280. PDQ_LINK_EVENT_PDU_LENGTH_ERROR
281. PDQ_LINK_EVENT_RECEIVE_DATA_OVERRUN
282. PDQ_LINK_EVENT_NO_USER_BUFFER
283. PDQ_LINK_EVENT_RING_INITIALIZATION_INITIATED
284. PDQ_LINK_EVENT_RING_INITIALIZATION_RECEIVED
285. PDQ_LINK_EVENT_RING_BEACON_INITIATED
286. PDQ_LINK_EVENT_DUPLICATE_ADDRESS_FAILURE
287. PDQ_LINK_EVENT_DUPLICATE_TOKEN_DETECTED
288. PDQ_LINK_EVENT_RING_PURGE_ERROR
289. PDQ_LINK_EVENT_FCI_STRIP_ERROR
290. PDQ_LINK_EVENT_TRACE_INITIATED
291. PDQ_LINK_EVENT_DIRECTED_BEACON_RECEIVED
292. pdq_link_event_t
293. PDQ_LINK_EVENT_ARGUMENT_REASON
294. PDQ_LINK_EVENT_ARGUMENT_DATA_LINK_HEADER
295. PDQ_LINK_EVENT_ARGUMENT_SOURCE
296. PDQ_LINK_EVENT_ARGUMENT_UPSTREAM_NEIGHBOR
297. PDQ_LINK_EVENT_ARGUMENT_EOL
298. pdq_link_event_argument_t
299. PDQ_PHY_EVENT_LEM_ERROR_MONITOR_REJECT
300. PDQ_PHY_EVENT_ELASTICITY_BUFFER_ERROR
301. PDQ_PHY_EVENT_LINK_CONFIDENCE_TEST_REJECT
302. pdq_phy_event_t
303. PDQ_PHY_EVENT_ARGUMENT_DIRECTION
304. PDQ_PHY_EVENT_ARGUMENT_EOL
305. pdq_phy_event_arguments

    1 /*      $OpenBSD: pdqreg.h,v 1.9 2002/06/02 22:50:00 deraadt Exp $      */
    2 /*      $NetBSD: pdqreg.h,v 1.6 1996/08/28 16:01:29 cgd Exp $   */
    4 /*-
    5  * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. The name of the author may not be used to endorse or promote products
   14  *    derived from this software without specific prior written permission
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   26  *
   27  * Id: pdqreg.h,v 1.9 1996/05/16 14:25:26 thomas Exp
   28  *
   29  */
   31 /*
   32  * DEC PDQ FDDI Controller; PDQ port driver definitions
   33  *
   34  */
   36 #ifndef _PDQREG_H
   37 #define _PDQREG_H
   39 #if !defined(__NetBSD__) && !defined(__OpenBSD__)
   40 #include <stddef.h>
   41 #if defined(PDQTEST) && !defined(PDQ_NDEBUG)
   42 #include <assert.h>
   43 #define PDQ_ASSERT      assert
   44 #else
   45 #define PDQ_ASSERT(x)   do { } while(0)
   46 #endif
   47 #else /* __NetBSD__ || __OpenBSD__*/
   49 /*
   50  * Can't directly use "assert", because apparently cpp won't expand it
   51  * unless it has an argument, which loses.
   52  */
   53 #ifdef PDQ_NDEBUG
   54 #define PDQ_ASSERT(e)   ((void)0)
   55 #else
   56 #ifdef __STDC__
   57 #define PDQ_ASSERT(e)   ((e) ? (void)0 :                                \
__assert("PDQ ", __FILE__, __LINE__, #e))
   59 #else
   60 #define PDQ_ASSERT(e)   ((e) ? (void)0 :                                \
__assert("PDQ ", __FILE__, __LINE__, "e"))
   62 #endif
   63 #endif
   64 #endif /* __NetBSD__ || __OpenBSD__ */
   66 #define PDQ_RING_SIZE(array)    ((sizeof(array) / sizeof(array[0])))
   67 #define PDQ_ARRAY_SIZE(array)   ((sizeof(array) / sizeof(array[0])))
   68 #define PDQ_RING_MASK(array)    (PDQ_RING_SIZE(array) - 1)
   69 #define PDQ_BITMASK(n)          (1L << (pdq_uint32_t) (n))
   71 #define PDQ_FDDI_MAX            4495
   72 #define PDQ_FDDI_LLC_MIN        20
   73 #define PDQ_FDDI_SMT_MIN        37
   75 #define PDQ_FDDI_SMT            0x40
   76 #define PDQ_FDDI_LLC_ASYNC      0x50
   77 #define PDQ_FDDI_LLC_SYNC       0xD0
   78 #define PDQ_FDDI_IMP_ASYNC      0x60
   79 #define PDQ_FDDI_IMP_SYNC       0xE0
   81 #define PDQ_FDDIFC_C            0x80
   82 #define PDQ_FDDIFC_L            0x40
   83 #define PDQ_FDDIFC_F            0x30
   84 #define PDQ_FDDIFC_Z            0x0F
   86 #define PDQ_FDDI_PH0            0x20
   87 #define PDQ_FDDI_PH1            0x38
   88 #define PDQ_FDDI_PH2            0x00
   90 typedef pdq_uint32_t pdq_physaddr_t;
   92 struct _pdq_lanaddr_t {
pdq_uint8_t lanaddr_bytes[8];
   94 };
   96 typedef struct {
pdq_uint8_t fwrev_bytes[4];
   98 } pdq_fwrev_t;
  100 enum _pdq_state_t {
PDQS_RESET=0,
PDQS_UPGRADE=1,
PDQS_DMA_UNAVAILABLE=2,
PDQS_DMA_AVAILABLE=3,
PDQS_LINK_AVAILABLE=4,
PDQS_LINK_UNAVAILABLE=5,
PDQS_HALTED=6,
PDQS_RING_MEMBER=7
  109 };
  111 struct _pdq_csrs_t {
pdq_bus_memoffset_t csr_port_reset;                 /* 0x00 [RW] */
pdq_bus_memoffset_t csr_host_data;                  /* 0x04 [R]  */
pdq_bus_memoffset_t csr_port_control;               /* 0x08 [RW] */
pdq_bus_memoffset_t csr_port_data_a;                /* 0x0C [RW] */
pdq_bus_memoffset_t csr_port_data_b;                /* 0x10 [RW] */
pdq_bus_memoffset_t csr_port_status;                /* 0x14 [R]  */
pdq_bus_memoffset_t csr_host_int_type_0;            /* 0x18 [RW] */
pdq_bus_memoffset_t csr_host_int_enable;            /* 0x1C [RW] */
pdq_bus_memoffset_t csr_type_2_producer;            /* 0x20 [RW] */
pdq_bus_memoffset_t csr_cmd_response_producer;      /* 0x28 [RW] */
pdq_bus_memoffset_t csr_cmd_request_producer;       /* 0x2C [RW] */
pdq_bus_memoffset_t csr_host_smt_producer;          /* 0x30 [RW] */
pdq_bus_memoffset_t csr_unsolicited_producer;       /* 0x34 [RW] */
pdq_bus_t csr_bus;
pdq_bus_memaddr_t csr_base;
  127 };
  129 struct _pdq_pci_csrs_t {
pdq_bus_memoffset_t csr_pfi_mode_control;           /* 0x40 [RW] */
pdq_bus_memoffset_t csr_pfi_status;                 /* 0x44 [RW] */
pdq_bus_memoffset_t csr_fifo_write;                 /* 0x48 [RW] */
pdq_bus_memoffset_t csr_fifo_read;                  /* 0x4C [RW] */
pdq_bus_t csr_bus;
pdq_bus_memaddr_t csr_base;
  136 };
  138 #define PDQ_PFI_MODE_DMA_ENABLE         0x01    /* DMA Enable */
  139 #define PDQ_PFI_MODE_PFI_PCI_INTR       0x02    /* PFI-to-PCI Int Enable */
  140 #define PDQ_PFI_MODE_PDQ_PCI_INTR       0x04    /* PDQ-to-PCI Int Enable */
  142 #define PDQ_PFI_STATUS_PDQ_INTR         0x10    /* PDQ Int received */
  143 #define PDQ_PFI_STATUS_DMA_ABORT        0x08    /* PDQ DMA Abort asserted */
  145 #define PDQ_EISA_BURST_HOLDOFF                  0x0040
  146 #define PDQ_EISA_SLOT_ID                        0x0C80
  147 #define PDQ_EISA_SLOT_CTRL                      0x0C84
  148 #define PDQ_EISA_MEM_ADD_CMP_0                  0x0C85
  149 #define PDQ_EISA_MEM_ADD_CMP_1                  0x0C86
  150 #define PDQ_EISA_MEM_ADD_CMP_2                  0x0C87
  151 #define PDQ_EISA_MEM_ADD_HI_CMP_0               0x0C88
  152 #define PDQ_EISA_MEM_ADD_HI_CMP_1               0x0C89
  153 #define PDQ_EISA_MEM_ADD_HI_CMP_2               0x0C8A
  154 #define PDQ_EISA_MEM_ADD_MASK_0                 0x0C8B
  155 #define PDQ_EISA_MEM_ADD_MASK_1                 0x0C8C
  156 #define PDQ_EISA_MEM_ADD_MASK_2                 0x0C8D
  157 #define PDQ_EISA_MEM_ADD_LO_CMP_0               0x0C8E
  158 #define PDQ_EISA_MEM_ADD_LO_CMP_1               0x0C8F
  159 #define PDQ_EISA_MEM_ADD_LO_CMP_2               0x0C90
  160 #define PDQ_EISA_IO_CMP_0_0                     0x0C91
  161 #define PDQ_EISA_IO_CMP_0_1                     0x0C92
  162 #define PDQ_EISA_IO_CMP_1_0                     0x0C93
  163 #define PDQ_EISA_IO_CMP_1_1                     0x0C94
  164 #define PDQ_EISA_IO_CMP_2_0                     0x0C95
  165 #define PDQ_EISA_IO_CMP_2_1                     0x0C96
  166 #define PDQ_EISA_IO_CMP_3_0                     0x0C97
  167 #define PDQ_EISA_IO_CMP_3_1                     0x0C98
  168 #define PDQ_EISA_IO_ADD_MASK_0_0                0x0C99
  169 #define PDQ_EISA_IO_ADD_MASK_0_1                0x0C9A
  170 #define PDQ_EISA_IO_ADD_MASK_1_0                0x0C9B
  171 #define PDQ_EISA_IO_ADD_MASK_1_1                0x0C9C
  172 #define PDQ_EISA_IO_ADD_MASK_2_0                0x0C9D
  173 #define PDQ_EISA_IO_ADD_MASK_2_1                0x0C9E
  174 #define PDQ_EISA_IO_ADD_MASK_3_0                0x0C9F
  175 #define PDQ_EISA_IO_ADD_MASK_3_1                0x0CA0
  176 #define PDQ_EISA_MOD_CONFIG_1                   0x0CA1
  177 #define PDQ_EISA_MOD_CONFIG_2                   0x0CA2
  178 #define PDQ_EISA_MOD_CONFIG_3                   0x0CA3
  179 #define PDQ_EISA_MOD_CONFIG_4                   0x0CA4
  180 #define PDQ_EISA_MOD_CONFIG_5                   0x0CA5
  181 #define PDQ_EISA_MOD_CONFIG_6                   0x0CA6
  182 #define PDQ_EISA_MOD_CONFIG_7                   0x0CA7
  183 #define PDQ_EISA_DIP_SWITCH                     0x0CA8
  184 #define PDQ_EISA_IO_CONFIG_STAT_0               0x0CA9
  185 #define PDQ_EISA_IO_CONFIG_STAT_1               0x0CAA
  186 #define PDQ_EISA_DMA_CONFIG                     0x0CAB
  187 #define PDQ_EISA_INPUT_PORT                     0x0CAC
  188 #define PDQ_EISA_OUTPUT_PORT                    0x0CAD
  189 #define PDQ_EISA_FUNCTION_CTRL                  0x0CAE
  191 #define PDQ_TC_CSR_OFFSET                       0x00100000
  192 #define PDQ_TC_CSR_SPACE                        0x0040
  193 #define PDQ_FBUS_CSR_OFFSET                     0x00200000
  194 #define PDQ_FBUS_CSR_SPACE                      0x0080
  196 /*
  197  * Port Reset Data A Definitions
  198  */
  199 #define PDQ_PRESET_SKIP_SELFTEST        0x0004
  200 #define PDQ_PRESET_SOFT_RESET           0x0002
  201 #define PDQ_PRESET_UPGRADE              0x0001
  202 /*
  203  * Port Control Register Definitions
  204  */
  205 #define PDQ_PCTL_CMD_ERROR              0x8000
  206 #define PDQ_PCTL_FLASH_BLAST            0x4000
  207 #define PDQ_PCTL_HALT                   0x2000
  208 #define PDQ_PCTL_COPY_DATA              0x1000
  209 #define PDQ_PCTL_ERROR_LOG_START        0x0800
  210 #define PDQ_PCTL_ERROR_LOG_READ         0x0400
  211 #define PDQ_PCTL_XMT_DATA_FLUSH_DONE    0x0200
  212 #define PDQ_PCTL_DMA_INIT               0x0100
  213 #define PDQ_DMA_INIT_LW_BSWAP_DATA      0x02
  214 #define PDQ_DMA_INIT_LW_BSWAP_LITERAL   0x01
  215 #define PDQ_PCTL_INIT_START             0x0080
  216 #define PDQ_PCTL_CONSUMER_BLOCK         0x0040
  217 #define PDQ_PCTL_DMA_UNINIT             0x0020
  218 #define PDQ_PCTL_RING_MEMBER            0x0010
  219 #define PDQ_PCTL_MLA_READ               0x0008
  220 #define PDQ_PCTL_FW_REV_READ            0x0004
  221 #define PDQ_PCTL_DEVICE_SPECIFIC        0x0002
  222 #define PDQ_PCTL_SUB_CMD                0x0001
  224 typedef enum {
PDQ_SUB_CMD_LINK_UNINIT=1,
PDQ_SUB_CMD_DMA_BURST_SIZE_SET=2,
PDQ_SUB_CMD_PDQ_REV_GET=4
  228 } pdq_sub_cmd_t;
  230 typedef enum {
  231     PDQ_DMA_BURST_4LW=0,
PDQ_DMA_BURST_8LW=1,
PDQ_DMA_BURST_16LW=2,
  234     PDQ_DMA_BURST_32LW=3
  235 } pdq_dma_burst_size_t;
  237 typedef enum {
PDQ_CHIP_REV_A_B_OR_C=0,
PDQ_CHIP_REV_D=2,
PDQ_CHIP_REV_E=4
  241 } pdq_chip_rev_t;
  242 /*
  243  * Port Status Register Definitions
  244  */
  245 #define PDQ_PSTS_RCV_DATA_PENDING       0x80000000ul
  246 #define PDQ_PSTS_XMT_DATA_PENDING       0x40000000ul
  247 #define PDQ_PSTS_HOST_SMT_PENDING       0x20000000ul
  248 #define PDQ_PSTS_UNSOL_PENDING          0x10000000ul
  249 #define PDQ_PSTS_CMD_RSP_PENDING        0x08000000ul
  250 #define PDQ_PSTS_CMD_REQ_PENDING        0x04000000ul
  251 #define PDQ_PSTS_TYPE_0_PENDING         0x02000000ul
  252 #define PDQ_PSTS_INTR_PENDING           0xFE000000ul
  253 #define PDQ_PSTS_ADAPTER_STATE(sts)     ((pdq_state_t) (((sts) >> 8) & 0x07))
  254 #define PDQ_PSTS_HALT_ID(sts)           ((pdq_halt_code_t) ((sts) & 0xFF))
  255 /*
  256  * Host Interrupt Register Definitions
  257  */
  258 #define PDQ_HOST_INT_TX_ENABLE                  0x80000000ul
  259 #define PDQ_HOST_INT_RX_ENABLE                  0x40000000ul
  260 #define PDQ_HOST_INT_UNSOL_ENABLE               0x20000000ul
  261 #define PDQ_HOST_INT_HOST_SMT_ENABLE            0x10000000ul
  262 #define PDQ_HOST_INT_CMD_RSP_ENABLE             0x08000000ul
  263 #define PDQ_HOST_INT_CMD_RQST_ENABLE            0x04000000ul
  265 #define PDQ_HOST_INT_1MS                        0x80
  266 #define PDQ_HOST_INT_20MS                       0x40
  267 #define PDQ_HOST_INT_CSR_CMD_DONE               0x20
  268 #define PDQ_HOST_INT_STATE_CHANGE               0x10
  269 #define PDQ_HOST_INT_XMT_DATA_FLUSH             0x08
  270 #define PDQ_HOST_INT_NXM                        0x04
  271 #define PDQ_HOST_INT_PM_PARITY_ERROR            0x02
  272 #define PDQ_HOST_INT_HOST_BUS_PARITY_ERROR      0x01
  273 #define PDQ_HOST_INT_FATAL_ERROR                0x07
  275 typedef enum {
  276     PDQH_SELFTEST_TIMEOUT=0,
  277     PDQH_HOST_BUS_PARITY_ERROR=1,
  278     PDQH_HOST_DIRECTED_HALT=2,
  279     PDQH_SOFTWARE_FAULT=3,
  280     PDQH_HARDWARE_FAULT=4,
  281     PDQH_PC_TRACE_PATH_TEST=5,
PDQH_DMA_ERROR=6,
  283     PDQH_IMAGE_CRC_ERROR=7,
  284     PDQH_ADAPTER_PROCESSOR_ERROR=8,
  285     PDQH_MAX=9
  286 } pdq_halt_code_t;
  288 typedef struct {
pdq_uint16_t pdqcb_receives;
pdq_uint16_t pdqcb_transmits;
pdq_uint32_t pdqcb__filler1;
pdq_uint32_t pdqcb_host_smt;
pdq_uint32_t pdqcb__filler2;
pdq_uint32_t pdqcb_unsolicited_event;
pdq_uint32_t pdqcb__filler3;
pdq_uint32_t pdqcb_command_response;
pdq_uint32_t pdqcb__filler4;
pdq_uint32_t pdqcb_command_request;
pdq_uint32_t pdqcb__filler5[7];
  300 } pdq_consumer_block_t;
  302 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
  303 #define PDQ_BITFIELD2(a, b)                      b, a
  304 #define PDQ_BITFIELD3(a, b, c)                c, b, a
  305 #define PDQ_BITFIELD4(a, b, c, d)          d, c, b, a
  306 #define PDQ_BITFIELD5(a, b, c, d, e)    e, d, c, b, a
  307 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l)      \
l, k, j, i, h, g, f, e, d, c, b, a
  309 #else
  310 #define PDQ_BITFIELD2(a, b)             a, b
  311 #define PDQ_BITFIELD3(a, b, c)          a, b, c
  312 #define PDQ_BITFIELD4(a, b, c, d)       a, b, c, d
  313 #define PDQ_BITFIELD5(a, b, c, d, e)    a, b, c, d, e
  314 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l)      \
a, b, c, d, e, f, g, h, i, j, k, l
  316 #endif
  318 typedef struct {
pdq_uint32_t PDQ_BITFIELD5(rxd_pa_hi : 16,
rxd_seg_cnt : 4,
rxd_seg_len_hi : 9,
rxd_seg_len_lo : 2,
rxd_sop : 1);
pdq_uint32_t rxd_pa_lo;
  325 } pdq_rxdesc_t;
  327 typedef union {
pdq_uint32_t rxs_status;
pdq_uint32_t PDQ_BITFIELD12(rxs_len : 13,
rxs_rcc_ss : 2,
rxs_rcc_dd : 2,
rxs_rcc_reason : 3,
rxs_rcc_badcrc : 1,
rxs_rcc_badpdu : 1,
rxs_fsb__reserved : 2,
rxs_fsb_c : 1,
rxs_fsb_a : 1,
rxs_fsb_e : 1,
rxs_fsc : 3,
rxs__reserved : 2);
  341 } pdq_rxstatus_t;
  343 typedef struct {
pdq_uint32_t PDQ_BITFIELD5(txd_pa_hi : 16,
txd_seg_len : 13,
txd_mbz : 1,
txd_eop : 1,
txd_sop : 1);
pdq_uint32_t txd_pa_lo;
  350 } pdq_txdesc_t;
  352 typedef struct {
pdq_rxdesc_t pdqdb_receives[256];           /* 2048;        0x0000..0x07FF */
pdq_txdesc_t pdqdb_transmits[256];          /* 2048;        0x0800..0x0FFF */
pdq_rxdesc_t pdqdb_host_smt[64];            /*  512;        0x1000..0x11FF */
pdq_rxdesc_t pdqdb_unsolicited_events[16];  /*  128;        0x1200..0x127F */
pdq_rxdesc_t pdqdb_command_responses[16];   /*  128;        0x1280..0x12FF */
pdq_txdesc_t pdqdb_command_requests[16];    /*  128;        0x1300..0x137F */
  359     /*
  360      * The rest of the descriptor block is unused.
  361      * As such we could use it for other things.
  362      */
pdq_consumer_block_t pdqdb_consumer;        /*   64;        0x1380..0x13BF */
  364     void *pdqdb_receive_buffers[256];           /* 1024/2048;   0x13C0..0x17BF 0x13C0..0x1BBF */
  365     void *pdqdb_host_smt_buffers[64];           /*  256/ 512;   0x17C0..0x18BF 0x1BC0..0x1DBF */
  366     /*
  367      * The maximum command size is 512 so as long as thes
  368      * command is at least that long all will be fine.
  369      */
  370 #if defined(__alpha) || defined(__alpha__)
pdq_uint32_t pdqdb_command_pool[144];
  372 #else
pdq_uint32_t pdqdb_command_pool[464];
  374 #endif
  375 } pdq_descriptor_block_t;
  377 typedef struct {
  378     /*
  379      * These value manage the available space in command/response
  380      * buffer area.
  381      */
pdq_physaddr_t ci_pa_bufstart;
pdq_uint8_t *ci_bufstart;
  384     /*
  385      * Bitmask of commands to sent to the PDQ
  386      */
pdq_uint32_t ci_pending_commands;
  388     /*
  389      * Variables to maintain the PDQ queues.
  390      */
pdq_uint32_t ci_command_active;
pdq_uint32_t ci_request_producer;
pdq_uint32_t ci_response_producer;
pdq_uint32_t ci_request_completion;
pdq_uint32_t ci_response_completion;
  396 } pdq_command_info_t;
  398 #define PDQ_SIZE_UNSOLICITED_EVENT      512
  399 #define PDQ_NUM_UNSOLICITED_EVENTS      (PDQ_OS_PAGESIZE / PDQ_SIZE_UNSOLICITED_EVENT)
  401 typedef struct _pdq_unsolicited_event_t pdq_unsolicited_event_t;
  403 typedef struct {
pdq_physaddr_t ui_pa_bufstart;
pdq_unsolicited_event_t *ui_events;
pdq_uint32_t ui_free;
pdq_uint32_t ui_producer;
pdq_uint32_t ui_completion;
  410 } pdq_unsolicited_info_t;
  412 #define PDQ_RX_FC_OFFSET        (sizeof(pdq_rxstatus_t) + 3)
  413 #define PDQ_RX_SEGCNT           ((PDQ_FDDI_MAX + PDQ_OS_DATABUF_SIZE - 1) / PDQ_OS_DATABUF_SIZE)
  414 #define PDQ_DO_TYPE2_PRODUCER(pdq) \
PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_type_2_producer, \
  416           ((pdq)->pdq_rx_info.rx_producer << 0) \
  417         | ((pdq)->pdq_tx_info.tx_producer << 8) \
  418         | ((pdq)->pdq_rx_info.rx_completion << 16) \
  419         | ((pdq)->pdq_tx_info.tx_completion << 24))
  421 #define PDQ_DO_HOST_SMT_PRODUCER(pdq) \
PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_host_smt_producer, \
  423           ((pdq)->pdq_host_smt_info.rx_producer   << 0) \
  424         | ((pdq)->pdq_host_smt_info.rx_completion << 8))\
  426 #define PDQ_ADVANCE(n, a, m)    ((n) = ((n) + (a)) & (m))
  428 typedef struct {
  429     void *q_head;
  430     void *q_tail;
  431 } pdq_databuf_queue_t;
  433 typedef struct {
  434     void *rx_buffers;
pdq_uint32_t rx_target;
pdq_uint32_t rx_free;
pdq_uint32_t rx_producer;
pdq_uint32_t rx_completion;
  440 } pdq_rx_info_t;
  442 typedef struct {
pdq_databuf_queue_t tx_txq;
pdq_txdesc_t tx_hdrdesc;
pdq_uint8_t tx_descriptor_count[256];
pdq_uint32_t tx_free;
pdq_uint32_t tx_producer;
pdq_uint32_t tx_completion;
  450 } pdq_tx_info_t;
  452 struct _pdq_t {
pdq_csrs_t pdq_csrs;
pdq_pci_csrs_t pdq_pci_csrs;
pdq_type_t pdq_type;
pdq_chip_rev_t pdq_chip_rev;
pdq_lanaddr_t pdq_hwaddr;
pdq_fwrev_t pdq_fwrev;
pdq_descriptor_block_t *pdq_dbp;
  460     volatile pdq_consumer_block_t *pdq_cbp;
pdq_uint32_t pdq_flags;
  462 #define PDQ_PROMISC     0x0001
  463 #define PDQ_ALLMULTI    0x0002
  464 #define PDQ_PASS_SMT    0x0004
  465 #define PDQ_RUNNING     0x0008
  466 #define PDQ_PRINTCHARS  0x0010
  467 #define PDQ_TXOK        0x0020
  468     const char *pdq_os_name;
  469     void *pdq_os_ctx;
pdq_uint32_t pdq_unit;
pdq_command_info_t pdq_command_info;
pdq_unsolicited_info_t pdq_unsolicited_info;
pdq_tx_info_t pdq_tx_info;
pdq_rx_info_t pdq_rx_info;
pdq_rx_info_t pdq_host_smt_info;
pdq_uint8_t pdq_tx_hdr[3];
  477 };
  479 typedef enum {
PDQC_START=0,
PDQC_FILTER_SET=1,
  482     PDQC_FILTER_GET=2,
  483     PDQC_CHARS_SET=3,
PDQC_STATUS_CHARS_GET=4,
  485     PDQC_COUNTERS_GET=5,
  486     PDQC_COUNTERS_SET=6,
PDQC_ADDR_FILTER_SET=7,
  488     PDQC_ADDR_FILTER_GET=8,
  489     PDQC_ERROR_LOG_CLEAR=9,
  490     PDQC_ERROR_LOG_GET=10,
  491     PDQC_FDDI_MIB_GET=11,
  492     PDQC_DEC_EXT_MIB_GET=12,
  493     PDQC_DEV_SPECIFIC_GET=13,
  494     PDQC_SNMP_SET=14,
  495     PDQC_SMT_MIB_GET=16,
PDQC_SMT_MIB_SET=17
  497 } pdq_cmd_code_t;
  499 typedef enum {
PDQR_SUCCESS=0,
  501     PDQR_FAILURE=1,
  502     PDQR_WARNING=2,
  503     PDQR_LOOP_MODE_BAD=3,
  504     PDQR_ITEM_CODE_BAD=4,
  505     PDQR_TVX_BAD=5,
  506     PDQR_TREQ_BAD=6,
  507     PDQR_RESTRICTED_TOKEN_BAD=7,
  508     PDQR_NO_EOL=12,
  509     PDQR_FILTER_STATE_BAD=13,
  510     PDQR_CMD_TYPE_BAD=14,
  511     PDQR_ADAPTER_STATE_BAD=15,
  512     PDQR_RING_PURGER_BAD=16,
  513     PDQR_LEM_THRESHOLD_BAD=17,
  514     PDQR_LOOP_NOT_SUPPORTED=18,
  515     PDQR_FLUSH_TIME_BAD=19,
  516     PDQR_NOT_YET_IMPLEMENTED=20,
  517     PDQR_CONFIG_POLICY_BAD=21,
  518     PDQR_STATION_ACTION_BAD=22,
  519     PDQR_MAC_ACTION_BAD=23,
  520     PDQR_CON_POLICIES_BAD=24,
  521     PDQR_MAC_LOOP_TIME_BAD=25,
  522     PDQR_TB_MAX_BAD=26,
  523     PDQR_LER_CUTOFF_BAD=27,
  524     PDQR_LER_ALARM_BAD=28,
  525     PDQR_MAC_PATHS_REQ_BAD=29,
  526     PDQR_MAC_T_REQ_BAD=30,
  527     PDQR_EMAC_RING_PURGER_BAD=31,
  528     PDQR_EMAC_RTOKEN_TIMOUT_AD=32,
  529     PDQR_NO_SUCH_ENTRY=33,
  530     PDQR_T_NOTIFY_BAD=34,
  531     PDQR_TR_MAX_EXP_BAD=35,
  532     PDQR_FRAME_ERR_THRESHOLD_BAD=36,
  533     PDQR_MAX_TREQ_BAD=37,
  534     PDQR_FULL_DUPLEX_ENABLE_BAD=38,
  535     PDQR_ITEM_INDEX_BAD=39
  536 } pdq_response_code_t;
  538 typedef enum {
PDQI_EOL=0,
  540     PDQI_T_REQ=1,
  541     PDQI_TVX=2,
  542     PDQI_RESTRICTED_TOKEN=3,
  543     PDQI_LEM_THRESHOLD=4,
  544     PDQI_RING_PURGER=5,
  545     PDQI_COUNTER_INTERVAL=6,
PDQI_IND_GROUP_PROM=7,
PDQI_GROUP_PROM=8,
  548     PDQI_BROADCAST=9,
PDQI_SMT_PROM=10,
PDQI_SMT_USER=11,
  551     PDQI_RESERVED=12,
  552     PDQI_IMPLEMENTOR=13,
  553     PDQI_LOOPBACK_MODE=14,
  554     PDQI_SMT_CONFIG_POLICY=16,
  555     PDQI_SMT_CONNECTION_POLICY=17,
  556     PDQI_SMT_T_NOTIFY=18,
  557     PDQI_SMT_STATION_ACTION=19,
  558     PDQI_MAC_PATHS_REQUESTED=21,
  559     PDQI_MAC_ACTION=23,
  560     PDQI_PORT_CONNECTION_POLICIES=24,
  561     PDQI_PORT_PATHS_REQUESTED=25,
  562     PDQI_PORT_MAC_LOOP_TIME=26,
  563     PDQI_PORT_TB_MAX=27,
  564     PDQI_PORT_LER_CUTOFF=28,
  565     PDQI_PORT_LER_ALARM=29,
  566     PDQI_PORT_ACTION=30,
  567     PDQI_FLUSH_TIME=32,
  568     PDQI_SMT_USER_DATA=33,
  569     PDQI_SMT_STATUS_REPORT_POLICY=34,
  570     PDQI_SMT_TRACE_MAX_EXPIRATION=35,
  571     PDQI_MAC_FRAME_ERR_THRESHOLD=36,
  572     PDQI_MAC_UNIT_DATA_ENABLE=37,
  573     PDQI_PATH_TVX_LOWER_BOUND=38,
  574     PDQI_PATH_TMAX_LOWER_BOUND=39,
  575     PDQI_PATH_MAX_TREQ=40,
  576     PDQI_MAC_TREQ=41,
  577     PDQI_EMAC_RING_PURGER=42,
  578     PDQI_EMAC_RTOKEN_TIMEOUT=43,
  579     PDQI_FULL_DUPLEX_ENABLE=44
  580 } pdq_item_code_t;
  582 enum _pdq_boolean_t {
PDQ_FALSE=0,
PDQ_TRUE=1
  585 };
  587 typedef enum {
PDQ_FILTER_BLOCK=0,
PDQ_FILTER_PASS=1
  590 } pdq_filter_state_t;
  592 typedef enum {
  593     PDQ_STATION_TYPE_SAS=0,
  594     PDQ_STATION_TYPE_DAC=1,
  595     PDQ_STATION_TYPE_SAC=2,
  596     PDQ_STATION_TYPE_NAC=3,
PDQ_STATION_TYPE_DAS=4
  598 } pdq_station_type_t;
  600 typedef enum {
  601     PDQ_STATION_STATE_OFF=0,
  602     PDQ_STATION_STATE_ON=1,
  603     PDQ_STATION_STATE_LOOPBACK=2
  604 } pdq_station_state_t;
  606 typedef enum {
  607     PDQ_LINK_STATE_OFF_READY=1,
  608     PDQ_LINK_STATE_OFF_FAULT_RECOVERY=2,
  609     PDQ_LINK_STATE_ON_RING_INIT=3,
  610     PDQ_LINK_STATE_ON_RING_RUN=4,
  611     PDQ_LINK_STATE_BROKEN=5
  612 } pdq_link_state_t;
  614 typedef enum {
  615     PDQ_DA_TEST_STATE_UNKNOWN=0,
  616     PDQ_DA_TEST_STATE_SUCCESS=1,
  617     PDQ_DA_TEST_STATE_DUPLICATE=2
  618 } pdq_da_test_state_t;
  620 typedef enum {
  621     PDQ_RING_PURGER_STATE_OFF=0,
  622     PDQ_RING_PURGER_STATE_CANDIDATE=1,
  623     PDQ_RING_PURGER_STATE_NON_PURGER=2,
  624     PDQ_RING_PURGER_STATE_PURGER=3
  625 } pdq_ring_purger_state_t;
  627 typedef enum {
  628     PDQ_FRAME_STRING_MODE_SA_MATCH=0,
  629     PDQ_FRAME_STRING_MODE_FCI_STRIP=1
  630 } pdq_frame_strip_mode_t;
  632 typedef enum {
  633     PDQ_RING_ERROR_REASON_NO_ERROR=0,
  634     PDQ_RING_ERROR_REASON_RING_INIT_INITIATED=5,
  635     PDQ_RING_ERROR_REASON_RING_INIT_RECEIVED=6,
  636     PDQ_RING_ERROR_REASON_RING_BEACONING_INITIATED=7,
  637     PDQ_RING_ERROR_REASON_DUPLICATE_ADDRESS_DETECTED=8,
  638     PDQ_RING_ERROR_REASON_DUPLICATE_TOKEN_DETECTED=9,
  639     PDQ_RING_ERROR_REASON_RING_PURGER_ERROR=10,
  640     PDQ_RING_ERROR_REASON_FCI_STRIP_ERROR=11,
  641     PDQ_RING_ERROR_REASON_RING_OP_OSCILLATION=12,
  642     PDQ_RING_ERROR_REASON_DIRECTED_BEACON_RECEVIED=13,
  643     PDQ_RING_ERROR_REASON_PC_TRACE_INITIATED=14,
  644     PDQ_RING_ERROR_REASON_PC_TRACE_RECEVIED=15
  645 } pdq_ring_error_reason_t;
  647 typedef enum {
  648     PDQ_STATION_MODE_NORMAL=0,
  649     PDQ_STATION_MODE_INTERNAL_LOOPBACK=1
  650 } pdq_station_mode_t;
  652 typedef enum {
  653     PDQ_PHY_TYPE_A=0,
  654     PDQ_PHY_TYPE_B=1,
  655     PDQ_PHY_TYPE_S=2,
  656     PDQ_PHY_TYPE_M=3,
  657     PDQ_PHY_TYPE_UNKNOWN=4
  658 } pdq_phy_type_t;
  660 typedef enum {
  661     PDQ_PMD_TYPE_ANSI_MUTLI_MODE=0,
  662     PDQ_PMD_TYPE_ANSI_SINGLE_MODE_TYPE_1=1,
  663     PDQ_PMD_TYPE_ANSI_SIGNLE_MODE_TYPE_2=2,
  664     PDQ_PMD_TYPE_ANSI_SONET=3,
  665     PDQ_PMD_TYPE_LOW_POWER=100,
  666     PDQ_PMD_TYPE_THINWIRE=101,
  667     PDQ_PMD_TYPE_SHIELDED_TWISTED_PAIR=102,
  668     PDQ_PMD_TYPE_UNSHIELDED_TWISTED_PAIR=103
  669 } pdq_pmd_type_t;
  671 typedef enum {
  672     PDQ_PMD_CLASS_ANSI_MULTI_MODE=0,
  673     PDQ_PMD_CLASS_SINGLE_MODE_TYPE_1=1,
  674     PDQ_PMD_CLASS_SINGLE_MODE_TYPE_2=2,
  675     PDQ_PMD_CLASS_SONET=3,
  676     PDQ_PMD_CLASS_LOW_COST_POWER_FIBER=4,
  677     PDQ_PMD_CLASS_TWISTED_PAIR=5,
  678     PDQ_PMD_CLASS_UNKNOWN=6,
  679     PDQ_PMD_CLASS_UNSPECIFIED=7
  680 } pdq_pmd_class_t;
  682 typedef enum {
  683     PDQ_PHY_STATE_INTERNAL_LOOPBACK=0,
  684     PDQ_PHY_STATE_BROKEN=1,
  685     PDQ_PHY_STATE_OFF_READY=2,
  686     PDQ_PHY_STATE_WAITING=3,
  687     PDQ_PHY_STATE_STARTING=4,
  688     PDQ_PHY_STATE_FAILED=5,
  689     PDQ_PHY_STATE_WATCH=6,
  690     PDQ_PHY_STATE_INUSE=7
  691 } pdq_phy_state_t;
  693 typedef enum {
  694     PDQ_REJECT_REASON_NONE=0,
  695     PDQ_REJECT_REASON_LOCAL_LCT=1,
  696     PDQ_REJECT_REASON_REMOTE_LCT=2,
  697     PDQ_REJECT_REASON_LCT_BOTH_SIDES=3,
  698     PDQ_REJECT_REASON_LEM_REJECT=4,
  699     PDQ_REJECT_REASON_TOPOLOGY_ERROR=5,
  700     PDQ_REJECT_REASON_NOISE_REJECT=6,
  701     PDQ_REJECT_REASON_REMOTE_REJECT=7,
  702     PDQ_REJECT_REASON_TRACE_IN_PROGRESS=8,
  703     PDQ_REJECT_REASON_TRACE_RECEIVED_DISABLED=9,
  704     PDQ_REJECT_REASON_STANDBY=10,
  705     PDQ_REJECT_REASON_LCT_PROTOCOL_ERROR=11
  706 } pdq_reject_reason_t;
  708 typedef enum {
  709     PDQ_BROKEN_REASON_NONE=0
  710 } pdq_broken_reason_t;
  712 typedef enum {
  713     PDQ_RI_REASON_TVX_EXPIRED=0,
  714     PDQ_RI_REASON_TRT_EXPIRED=1,
  715     PDQ_RI_REASON_RING_PURGER_ELECTION_ATTEMPT_LIMIT_EXCEEDED=2,
  716     PDQ_RI_REASON_PURGE_ERROR_LIMIT_EXCEEDED=3,
  717     PDQ_RI_REASON_RESTRICTED_TOKEN_TIMEOUT=4
  718 } pdq_ri_reason_t;
  720 typedef enum {
  721     PDQ_LCT_DIRECTION_LOCAL_LCT=0,
  722     PDQ_LCT_DIRECTION_REMOTE_LCT=1,
  723     PDQ_LCT_DIRECTION_LCT_BOTH_SIDES=2
  724 } pdq_lct_direction_t;
  726 typedef enum {
  727     PDQ_PORT_A=0,
  728     PDQ_PORT_B=1
  729 } pdq_port_type_t;
  731 typedef struct {
pdq_uint8_t station_id_bytes[8];
  733 } pdq_station_id_t;
  735 typedef pdq_uint32_t pdq_fdditimer_t;
  736 /*
  737  * Command format for Start, Filter_Get, ... commands
  738  */
  739 typedef struct {
pdq_cmd_code_t generic_op;
  741 } pdq_cmd_generic_t;
  743 /*
  744  * Response format for Start, Filter_Set, ... commands
  745  */
  746 typedef struct {
pdq_uint32_t generic_reserved;
pdq_cmd_code_t generic_op;
pdq_response_code_t generic_status;
  750 } pdq_response_generic_t;
  752 /*
  753  * Command format for Filter_Set command
  754  */
  755 typedef struct {
pdq_cmd_code_t filter_set_op;
  757     struct {
pdq_item_code_t item_code;
pdq_filter_state_t filter_state;
  760     } filter_set_items[7];
pdq_item_code_t filter_set_eol_item_code;
  762 } pdq_cmd_filter_set_t;
  764 /*
  765  * Response format for Filter_Get command.
  766  */
  767 typedef struct {
pdq_uint32_t filter_get_reserved;
pdq_cmd_code_t filter_get_op;
pdq_response_code_t filter_get_status;
pdq_filter_state_t filter_get_ind_group_prom;
pdq_filter_state_t filter_get_group_prom;
pdq_filter_state_t filter_get_broadcast_all;
pdq_filter_state_t filter_get_smt_prom;
pdq_filter_state_t filter_get_smt_user;
pdq_filter_state_t filter_get_reserved_all;
pdq_filter_state_t filter_get_implementor_all;
  778 } pdq_response_filter_get_t;
  780 #define PDQ_SIZE_RESPONSE_FILTER_GET    0x28
  782 typedef struct {
pdq_cmd_code_t chars_set_op;
  784     struct {
pdq_item_code_t item_code;
pdq_uint32_t item_value;
pdq_port_type_t item_port;
  788     } chars_set_items[1];
pdq_item_code_t chars_set_eol_item_code;
  790 } pdq_cmd_chars_set_t;
  792 typedef struct {
pdq_cmd_code_t addr_filter_set_op;
pdq_lanaddr_t addr_filter_set_addresses[62];
  795 } pdq_cmd_addr_filter_set_t;
  797 #define PDQ_SIZE_CMD_ADDR_FILTER_SET    0x1F4
  799 typedef struct {
pdq_uint32_t addr_filter_get_reserved;
pdq_cmd_code_t addr_filter_get_op;
pdq_response_code_t addr_filter_get_status;
pdq_lanaddr_t addr_filter_get_addresses[62];
  804 } pdq_response_addr_filter_get_t;
  806 #define PDQ_SIZE_RESPONSE_ADDR_FILTER_GET       0x1FC
  808 typedef struct {
pdq_uint32_t status_chars_get_reserved;
pdq_cmd_code_t status_chars_get_op;
pdq_response_code_t status_chars_get_status;
  812     struct {
  813         /* Station Characteristic Attributes */
pdq_station_id_t station_id;
pdq_station_type_t station_type;
pdq_uint32_t smt_version_id;
pdq_uint32_t smt_max_version_id;
pdq_uint32_t smt_min_version_id;
  819         /* Station Status Attributes */
pdq_station_state_t station_state;
  821         /* Link Characteristic Attributes */
pdq_lanaddr_t link_address;
pdq_fdditimer_t t_req;
pdq_fdditimer_t tvx;
pdq_fdditimer_t restricted_token_timeout;
pdq_boolean_t ring_purger_enable;
pdq_link_state_t link_state;
pdq_fdditimer_t negotiated_trt;
pdq_da_test_state_t dup_addr_flag;
  830         /* Link Status Attributes */
pdq_lanaddr_t upstream_neighbor;
pdq_lanaddr_t old_upstream_neighbor;
pdq_boolean_t upstream_neighbor_dup_addr_flag;
pdq_lanaddr_t downstream_neighbor;
pdq_lanaddr_t old_downstream_neighbor;
pdq_ring_purger_state_t ring_purger_state;
pdq_frame_strip_mode_t frame_strip_mode;
pdq_ring_error_reason_t ring_error_reason;
pdq_boolean_t loopback;
pdq_fdditimer_t ring_latency;
pdq_lanaddr_t last_dir_beacon_sa;
pdq_lanaddr_t last_dir_beacon_una;
  843         /* Phy Characteristic Attributes */
pdq_phy_type_t phy_type[2];
pdq_pmd_type_t pmd_type[2];
pdq_uint32_t lem_threshold[2];
  847         /* Phy Status Attributes */
pdq_phy_state_t phy_state[2];
pdq_phy_type_t neighbor_phy_type[2];
pdq_uint32_t link_error_estimate[2];
pdq_broken_reason_t broken_reason[2];
pdq_reject_reason_t reject_reason[2];
  853         /* Miscellaneous */
pdq_uint32_t counter_interval;
pdq_fwrev_t module_rev;
pdq_fwrev_t firmware_rev;
pdq_uint32_t mop_device_type;
pdq_uint32_t fddi_led[2];
pdq_uint32_t flush;
  860     } status_chars_get;
  861 } pdq_response_status_chars_get_t;
  863 #define PDQ_SIZE_RESPONSE_STATUS_CHARS_GET      0xF0
  865 typedef struct {
pdq_uint32_t fddi_mib_get_reserved;
pdq_cmd_code_t fddi_mib_get_op;
pdq_response_code_t fddi_mib_get_status;
  869     struct {
  870         /* SMT Objects */
pdq_station_id_t smt_station_id;
pdq_uint32_t smt_op_version_id;
pdq_uint32_t smt_hi_version_id;
pdq_uint32_t smt_lo_version_id;
pdq_uint32_t smt_mac_ct;
pdq_uint32_t smt_non_master_ct;
pdq_uint32_t smt_master_ct;
pdq_uint32_t smt_paths_available;
pdq_uint32_t smt_config_capabilities;
pdq_uint32_t smt_config_policy;
pdq_uint32_t smt_connection_policy;
pdq_uint32_t smt_t_notify;
pdq_uint32_t smt_status_reporting;
pdq_uint32_t smt_ecm_state;
pdq_uint32_t smt_cf_state;
pdq_uint32_t smt_hold_state;
pdq_uint32_t smt_remote_disconnect_flag;
pdq_uint32_t smt_station_action;
  889         /* MAC Objects */
pdq_uint32_t mac_frame_status_capabilities;
pdq_uint32_t mac_t_max_greatest_lower_bound;
pdq_uint32_t mac_tvx_greatest_lower_bound;
pdq_uint32_t mac_paths_available;
pdq_uint32_t mac_current_path;
pdq_lanaddr_t mac_upstream_neighbor;
pdq_lanaddr_t mac_old_upstream_neighbor;
pdq_uint32_t mac_dup_addr_test;
pdq_uint32_t mac_paths_requested;
pdq_uint32_t mac_downstream_port_type;
pdq_lanaddr_t mac_smt_address;
pdq_uint32_t mac_t_req;
pdq_uint32_t mac_t_neg;
pdq_uint32_t mac_t_max;
pdq_uint32_t mac_tvx_value;
pdq_uint32_t mac_t_min;
pdq_uint32_t mac_current_frame_status;
pdq_uint32_t mac_frame_error_threshold;
pdq_uint32_t mac_frame_error_ratio;
pdq_uint32_t mac_rmt_state;
pdq_uint32_t mac_da_flag;
pdq_uint32_t mac_una_da_flag;
pdq_uint32_t mac_frame_condition;
pdq_uint32_t mac_chip_set;
pdq_uint32_t mac_action;
  915         /* Port Objects */
pdq_uint32_t port_pc_type[2];
pdq_uint32_t port_pc_neighbor[2];
pdq_uint32_t port_connection_policies[2];
pdq_uint32_t port_remote_mac_indicated[2];
pdq_uint32_t port_ce_state[2];
pdq_uint32_t port_paths_requested[2];
pdq_uint32_t port_mac_placement[2];
pdq_uint32_t port_available_paths[2];
pdq_uint32_t port_mac_loop_time[2];
pdq_uint32_t port_tb_max[2];
pdq_uint32_t port_bs_flag[2];
pdq_uint32_t port_ler_estimate[2];
pdq_uint32_t port_ler_cutoff[2];
pdq_uint32_t port_ler_alarm[2];
pdq_uint32_t port_connect_state[2];
pdq_uint32_t port_pcm_state[2];
pdq_uint32_t port_pc_withhold[2];
pdq_uint32_t port_ler_condition[2];
pdq_uint32_t port_chip_set[2];
pdq_uint32_t port_action[2];
  936         /* Attachment Objects */
pdq_uint32_t attachment_class;
pdq_uint32_t attachment_optical_bypass_present;
pdq_uint32_t attachment_imax_expiration;
pdq_uint32_t attachment_inserted_status;
pdq_uint32_t attachment_insert_policy;
  942     } fddi_mib_get;
  943 } pdq_response_fddi_mib_get_t;
  945 #define PDQ_SIZE_RESPONSE_FDDI_MIB_GET  0x17C
  947 typedef enum {
  948     PDQ_FDX_STATE_IDLE=0,
  949     PDQ_FDX_STATE_REQUEST=1,
  950     PDQ_FDX_STATE_CONFIRM=2,
  951     PDQ_FDX_STATE_OPERATION=3
  952 } pdq_fdx_state_t;
  954 typedef struct {
pdq_uint32_t dec_ext_mib_get_reserved;
pdq_cmd_code_t dec_ext_mib_get_op;
pdq_response_code_t dec_ext_mib_get_response;
  958     struct {
  959         /* SMT Objects */
pdq_uint32_t esmt_station_type;
  961         /* MAC Objects */
pdq_uint32_t emac_link_state;
pdq_uint32_t emac_ring_purger_state;
pdq_uint32_t emac_ring_purger_enable;
pdq_uint32_t emac_frame_strip_mode;
pdq_uint32_t emac_ring_error_reason;
pdq_uint32_t emac_upstream_nbr_dupl_address_flag;
pdq_uint32_t emac_restricted_token_timeout;
  969         /* Port Objects */
pdq_uint32_t eport_pmd_type[2];
pdq_uint32_t eport_phy_state[2];
pdq_uint32_t eport_reject_reason[2];
  973         /* Full Duplex Objects */
pdq_boolean_t fdx_enable;
pdq_boolean_t fdx_operational;
pdq_fdx_state_t fdx_state;
  977     } dec_ext_mib_get;
  978 } pdq_response_dec_ext_mib_get_t;
  980 #define PDQ_SIZE_RESPONSE_DEC_EXT_MIB_GET       0x50
  982 typedef enum {
  983     PDQ_CALLER_ID_NONE=0,
  984     PDQ_CALLER_ID_SELFTEST=1,
  985     PDQ_CALLER_ID_MFG=2,
  986     PDQ_CALLER_ID_FIRMWARE=5,
  987     PDQ_CALLER_ID_CONSOLE=8
  988 } pdq_caller_id_t;
  990 typedef struct {
pdq_uint32_t error_log_get__reserved;
pdq_cmd_code_t error_log_get_op;
pdq_response_code_t error_log_get_status;
  994     /* Error Header */
pdq_uint32_t error_log_get_event_status;
  996     /* Event Information Block */
pdq_caller_id_t error_log_get_caller_id;
pdq_uint32_t error_log_get_timestamp[2];
pdq_uint32_t error_log_get_write_count;
 1000     /* Diagnostic Information */
pdq_uint32_t error_log_get_fru_implication_mask;
pdq_uint32_t error_log_get_test_id;
pdq_uint32_t error_log_get_diag_reserved[6];
 1004     /* Firmware Information */
pdq_uint32_t error_log_get_fw_reserved[112];
 1006 } pdq_response_error_log_get_t;
 1009 /*
 1010  * Definitions for the Unsolicited Event Queue.
 1011  */
 1012 typedef enum {
PDQ_UNSOLICITED_EVENT=0,
PDQ_UNSOLICITED_COUNTERS=1
 1015 } pdq_event_t;
 1017 typedef enum {
 1018     PDQ_ENTITY_STATION=0,
 1019     PDQ_ENTITY_LINK=1,
PDQ_ENTITY_PHY_PORT=2
 1021 } pdq_entity_t;
 1023 typedef enum {
 1024     PDQ_STATION_EVENT_TRACE_RECEIVED=1
 1025 } pdq_station_event_t;
 1027 typedef enum {
 1028     PDQ_STATION_EVENT_ARGUMENT_REASON=0,        /* pdq_uint32_t */
 1029     PDQ_STATION_EVENT_ARGUMENT_EOL=0xFF
 1030 } pdq_station_event_argument_t;
 1032 typedef enum {
 1033     PDQ_LINK_EVENT_TRANSMIT_UNDERRUN=0,
 1034     PDQ_LINK_EVENT_TRANSMIT_FAILED=1,
 1035     PDQ_LINK_EVENT_BLOCK_CHECK_ERROR=2,
 1036     PDQ_LINK_EVENT_FRAME_STATUS_ERROR=3,
 1037     PDQ_LINK_EVENT_PDU_LENGTH_ERROR=4,
 1038     PDQ_LINK_EVENT_RECEIVE_DATA_OVERRUN=7,
 1039     PDQ_LINK_EVENT_NO_USER_BUFFER=9,
 1040     PDQ_LINK_EVENT_RING_INITIALIZATION_INITIATED=10,
 1041     PDQ_LINK_EVENT_RING_INITIALIZATION_RECEIVED=11,
 1042     PDQ_LINK_EVENT_RING_BEACON_INITIATED=12,
 1043     PDQ_LINK_EVENT_DUPLICATE_ADDRESS_FAILURE=13,
 1044     PDQ_LINK_EVENT_DUPLICATE_TOKEN_DETECTED=14,
 1045     PDQ_LINK_EVENT_RING_PURGE_ERROR=15,
 1046     PDQ_LINK_EVENT_FCI_STRIP_ERROR=16,
 1047     PDQ_LINK_EVENT_TRACE_INITIATED=17,
 1048     PDQ_LINK_EVENT_DIRECTED_BEACON_RECEIVED=18
 1049 } pdq_link_event_t;
 1051 typedef enum {
 1052     PDQ_LINK_EVENT_ARGUMENT_REASON=0,           /* pdq_rireason_t */
 1053     PDQ_LINK_EVENT_ARGUMENT_DATA_LINK_HEADER=1, /* pdq_dlhdr_t */
 1054     PDQ_LINK_EVENT_ARGUMENT_SOURCE=2,           /* pdq_lanaddr_t */
 1055     PDQ_LINK_EVENT_ARGUMENT_UPSTREAM_NEIGHBOR=3,/* pdq_lanaddr_t */     
 1056     PDQ_LINK_EVENT_ARGUMENT_EOL=0xFF
 1057 } pdq_link_event_argument_t;
 1059 typedef enum {
 1060     PDQ_PHY_EVENT_LEM_ERROR_MONITOR_REJECT=0,
 1061     PDQ_PHY_EVENT_ELASTICITY_BUFFER_ERROR=1,
 1062     PDQ_PHY_EVENT_LINK_CONFIDENCE_TEST_REJECT=2
 1063 } pdq_phy_event_t;
 1065 typedef enum {
 1066     PDQ_PHY_EVENT_ARGUMENT_DIRECTION=0,         /* pdq_lct_direction_t */
 1067     PDQ_PHY_EVENT_ARGUMENT_EOL=0xFF
 1068 } pdq_phy_event_arguments;
 1070 struct _pdq_unsolicited_event_t {
pdq_uint32_t rvent_reserved;
pdq_event_t event_type;
pdq_entity_t event_entity;
pdq_uint32_t event_index;
 1075     union {
pdq_station_event_t station_event;
pdq_link_event_t link_event;
pdq_phy_event_t phy_event;
pdq_uint32_t value;
 1080     } event_code;
 1081     /*
 1082      * The remainder of this event is an argument list.
 1083      */
pdq_uint32_t event__filler[123];
 1085 };
 1087 #endif /* _PDQREG_H */