root/dev/pci/if_nge.c

DEFINITIONS

1. nge_delay
2. nge_eeprom_idle
3. nge_eeprom_putbyte
4. nge_eeprom_getword
5. nge_read_eeprom
6. nge_mii_sync
7. nge_mii_send
8. nge_mii_readreg
9. nge_mii_writereg
10. nge_miibus_readreg
11. nge_miibus_writereg
12. nge_miibus_statchg
13. nge_setmulti
14. nge_reset
15. nge_probe
16. nge_attach
17. nge_list_tx_init
18. nge_list_rx_init
19. nge_newbuf
20. nge_alloc_jumbo_mem
21. nge_jalloc
22. nge_jfree
23. nge_rxeof
24. nge_txeof
25. nge_tick
26. nge_intr
27. nge_encap
28. nge_start
29. nge_init
30. nge_ifmedia_mii_upd
31. nge_ifmedia_mii_sts
32. nge_ifmedia_tbi_upd
33. nge_ifmedia_tbi_sts
34. nge_ioctl
35. nge_watchdog
36. nge_stop
37. nge_shutdown

    1 /*      $OpenBSD: if_nge.c,v 1.56 2006/10/25 02:37:50 brad Exp $        */
    2 /*
    3  * Copyright (c) 2001 Wind River Systems
    4  * Copyright (c) 1997, 1998, 1999, 2000, 2001
    5  *      Bill Paul <wpaul@bsdi.com>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  *
   34  * $FreeBSD: if_nge.c,v 1.35 2002/08/08 18:33:28 ambrisko Exp $
   35  */
   37 /*
   38  * National Semiconductor DP83820/DP83821 gigabit ethernet driver
   39  * for FreeBSD. Datasheets are available from:
   40  *
   41  * http://www.national.com/ds/DP/DP83820.pdf
   42  * http://www.national.com/ds/DP/DP83821.pdf
   43  *
   44  * These chips are used on several low cost gigabit ethernet NICs
   45  * sold by D-Link, Addtron, SMC and Asante. Both parts are
   46  * virtually the same, except the 83820 is a 64-bit/32-bit part,
   47  * while the 83821 is 32-bit only.
   48  *
   49  * Many cards also use National gigE transceivers, such as the
   50  * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
   51  * contains a full register description that applies to all of these
   52  * components:
   53  *
   54  * http://www.national.com/ds/DP/DP83861.pdf
   55  *
   56  * Written by Bill Paul <wpaul@bsdi.com>
   57  * BSDi Open Source Solutions
   58  */
   60 /*
   61  * The NatSemi DP83820 and 83821 controllers are enhanced versions
   62  * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
   63  * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
   64  * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
   65  * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
   66  * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
   67  * matching buffers, one perfect address filter buffer and interrupt
   68  * moderation. The 83820 supports both 64-bit and 32-bit addressing
   69  * and data transfers: the 64-bit support can be toggled on or off
   70  * via software. This affects the size of certain fields in the DMA
   71  * descriptors.
   72  *
   73  * There are two bugs/misfeatures in the 83820/83821 that I have
   74  * discovered so far:
   75  *
   76  * - Receive buffers must be aligned on 64-bit boundaries, which means
   77  *   you must resort to copying data in order to fix up the payload
   78  *   alignment.
   79  *
   80  * - In order to transmit jumbo frames larger than 8170 bytes, you have
   81  *   to turn off transmit checksum offloading, because the chip can't
   82  *   compute the checksum on an outgoing frame unless it fits entirely
   83  *   within the TX FIFO, which is only 8192 bytes in size. If you have
   84  *   TX checksum offload enabled and you transmit attempt to transmit a
   85  *   frame larger than 8170 bytes, the transmitter will wedge.
   86  *
   87  * To work around the latter problem, TX checksum offload is disabled
   88  * if the user selects an MTU larger than 8152 (8170 - 18).
   89  */
   91 #include "bpfilter.h"
   92 #include "vlan.h"
   94 #include <sys/param.h>
   95 #include <sys/systm.h>
   96 #include <sys/sockio.h>
   97 #include <sys/mbuf.h>
   98 #include <sys/malloc.h>
   99 #include <sys/kernel.h>
  100 #include <sys/device.h>
  101 #include <sys/socket.h>
  103 #include <net/if.h>
  104 #include <net/if_dl.h>
  105 #include <net/if_media.h>
  107 #ifdef INET
  108 #include <netinet/in.h>
  109 #include <netinet/in_systm.h>
  110 #include <netinet/in_var.h>
  111 #include <netinet/ip.h>
  112 #include <netinet/if_ether.h>
  113 #endif
  115 #if NVLAN > 0
  116 #include <net/if_types.h>
  117 #include <net/if_vlan_var.h>
  118 #endif
  120 #if NBPFILTER > 0
  121 #include <net/bpf.h>
  122 #endif
  124 #include <uvm/uvm_extern.h>              /* for vtophys */
  125 #define VTOPHYS(v)      vtophys((vaddr_t)(v))
  127 #include <dev/pci/pcireg.h>
  128 #include <dev/pci/pcivar.h>
  129 #include <dev/pci/pcidevs.h>
  131 #include <dev/mii/mii.h>
  132 #include <dev/mii/miivar.h>
  134 #define NGE_USEIOSPACE
  136 #include <dev/pci/if_ngereg.h>
  138 int nge_probe(struct device *, void *, void *);
  139 void nge_attach(struct device *, struct device *, void *);
  141 int nge_alloc_jumbo_mem(struct nge_softc *);
  142 void *nge_jalloc(struct nge_softc *);
  143 void nge_jfree(caddr_t, u_int, void *);
  145 int nge_newbuf(struct nge_softc *, struct nge_desc *,
  146                              struct mbuf *);
  147 int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *);
  148 void nge_rxeof(struct nge_softc *);
  149 void nge_txeof(struct nge_softc *);
  150 int nge_intr(void *);
  151 void nge_tick(void *);
  152 void nge_start(struct ifnet *);
  153 int nge_ioctl(struct ifnet *, u_long, caddr_t);
  154 void nge_init(void *);
  155 void nge_stop(struct nge_softc *);
  156 void nge_watchdog(struct ifnet *);
  157 void nge_shutdown(void *);
  158 int nge_ifmedia_mii_upd(struct ifnet *);
  159 void nge_ifmedia_mii_sts(struct ifnet *, struct ifmediareq *);
  160 int nge_ifmedia_tbi_upd(struct ifnet *);
  161 void nge_ifmedia_tbi_sts(struct ifnet *, struct ifmediareq *);
  163 void nge_delay(struct nge_softc *);
  164 void nge_eeprom_idle(struct nge_softc *);
  165 void nge_eeprom_putbyte(struct nge_softc *, int);
  166 void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *);
  167 void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int);
  169 void nge_mii_sync(struct nge_softc *);
  170 void nge_mii_send(struct nge_softc *, u_int32_t, int);
  171 int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
  172 int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
  174 int nge_miibus_readreg(struct device *, int, int);
  175 void nge_miibus_writereg(struct device *, int, int, int);
  176 void nge_miibus_statchg(struct device *);
  178 void nge_setmulti(struct nge_softc *);
  179 void nge_reset(struct nge_softc *);
  180 int nge_list_rx_init(struct nge_softc *);
  181 int nge_list_tx_init(struct nge_softc *);
  183 #ifdef NGE_USEIOSPACE
  184 #define NGE_RES                 SYS_RES_IOPORT
  185 #define NGE_RID                 NGE_PCI_LOIO
  186 #else
  187 #define NGE_RES                 SYS_RES_MEMORY
  188 #define NGE_RID                 NGE_PCI_LOMEM
  189 #endif
  191 #ifdef NGE_DEBUG
  192 #define DPRINTF(x)      if (ngedebug) printf x
  193 #define DPRINTFN(n,x)   if (ngedebug >= (n)) printf x
  194 int     ngedebug = 0;
  195 #else
  196 #define DPRINTF(x)
  197 #define DPRINTFN(n,x)
  198 #endif
  200 #define NGE_SETBIT(sc, reg, x)                          \
CSR_WRITE_4(sc, reg,                            \
CSR_READ_4(sc, reg) | (x))
  204 #define NGE_CLRBIT(sc, reg, x)                          \
CSR_WRITE_4(sc, reg,                            \
CSR_READ_4(sc, reg) & ~(x))
  208 #define SIO_SET(x)                                      \
CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
  211 #define SIO_CLR(x)                                      \
CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
  214 void
nge_delay(sc)
  216         struct nge_softc        *sc;
  217 {
  218         int                     idx;
  220         for (idx = (300 / 33) + 1; idx > 0; idx--)
CSR_READ_4(sc, NGE_CSR);
  222 }
  224 void
nge_eeprom_idle(sc)
  226         struct nge_softc        *sc;
  227 {
  228         int             i;
SIO_SET(NGE_MEAR_EE_CSEL);
nge_delay(sc);
SIO_SET(NGE_MEAR_EE_CLK);
nge_delay(sc);
  235         for (i = 0; i < 25; i++) {
SIO_CLR(NGE_MEAR_EE_CLK);
nge_delay(sc);
SIO_SET(NGE_MEAR_EE_CLK);
nge_delay(sc);
  240         }
SIO_CLR(NGE_MEAR_EE_CLK);
nge_delay(sc);
SIO_CLR(NGE_MEAR_EE_CSEL);
nge_delay(sc);
CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
  247 }
  249 /*
  250  * Send a read command and address to the EEPROM, check for ACK.
  251  */
  252 void
nge_eeprom_putbyte(sc, addr)
  254         struct nge_softc        *sc;
  255         int                     addr;
  256 {
  257         int                     d, i;
d = addr | NGE_EECMD_READ;
  261         /*
  262          * Feed in each bit and strobe the clock.
  263          */
  264         for (i = 0x400; i; i >>= 1) {
  265                 if (d & i) {
SIO_SET(NGE_MEAR_EE_DIN);
  267                 } else {
SIO_CLR(NGE_MEAR_EE_DIN);
  269                 }
nge_delay(sc);
SIO_SET(NGE_MEAR_EE_CLK);
nge_delay(sc);
SIO_CLR(NGE_MEAR_EE_CLK);
nge_delay(sc);
  275         }
  276 }
  278 /*
  279  * Read a word of data stored in the EEPROM at address 'addr.'
  280  */
  281 void
nge_eeprom_getword(sc, addr, dest)
  283         struct nge_softc        *sc;
  284         int                     addr;
u_int16_t               *dest;
  286 {
  287         int                     i;
u_int16_t               word = 0;
  290         /* Force EEPROM to idle state. */
nge_eeprom_idle(sc);
  293         /* Enter EEPROM access mode. */
nge_delay(sc);
SIO_CLR(NGE_MEAR_EE_CLK);
nge_delay(sc);
SIO_SET(NGE_MEAR_EE_CSEL);
nge_delay(sc);
  300         /*
  301          * Send address of word we want to read.
  302          */
nge_eeprom_putbyte(sc, addr);
  305         /*
  306          * Start reading bits from EEPROM.
  307          */
  308         for (i = 0x8000; i; i >>= 1) {
SIO_SET(NGE_MEAR_EE_CLK);
nge_delay(sc);
  311                 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
word |= i;
nge_delay(sc);
SIO_CLR(NGE_MEAR_EE_CLK);
nge_delay(sc);
  316         }
  318         /* Turn off EEPROM access mode. */
nge_eeprom_idle(sc);
  321         *dest = word;
  322 }
  324 /*
  325  * Read a sequence of words from the EEPROM.
  326  */
  327 void
nge_read_eeprom(sc, dest, off, cnt, swap)
  329         struct nge_softc        *sc;
caddr_t                 dest;
  331         int                     off;
  332         int                     cnt;
  333         int                     swap;
  334 {
  335         int                     i;
u_int16_t               word = 0, *ptr;
  338         for (i = 0; i < cnt; i++) {
nge_eeprom_getword(sc, off + i, &word);
ptr = (u_int16_t *)(dest + (i * 2));
  341                 if (swap)
  342                         *ptr = ntohs(word);
  343                 else
  344                         *ptr = word;
  345         }
  346 }
  348 /*
  349  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  350  */
  351 void
nge_mii_sync(sc)
  353         struct nge_softc                *sc;
  354 {
  355         int                     i;
SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA);
  359         for (i = 0; i < 32; i++) {
SIO_SET(NGE_MEAR_MII_CLK);
DELAY(1);
SIO_CLR(NGE_MEAR_MII_CLK);
DELAY(1);
  364         }
  365 }
  367 /*
  368  * Clock a series of bits through the MII.
  369  */
  370 void
nge_mii_send(sc, bits, cnt)
  372         struct nge_softc                *sc;
u_int32_t               bits;
  374         int                     cnt;
  375 {
  376         int                     i;
SIO_CLR(NGE_MEAR_MII_CLK);
  380         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  381                 if (bits & i) {
SIO_SET(NGE_MEAR_MII_DATA);
  383                 } else {
SIO_CLR(NGE_MEAR_MII_DATA);
  385                 }
DELAY(1);
SIO_CLR(NGE_MEAR_MII_CLK);
DELAY(1);
SIO_SET(NGE_MEAR_MII_CLK);
  390         }
  391 }
  393 /*
  394  * Read an PHY register through the MII.
  395  */
  396 int
nge_mii_readreg(sc, frame)
  398         struct nge_softc                *sc;
  399         struct nge_mii_frame    *frame;
  400 {
  401         int                     i, ack, s;
s = splnet();
  405         /*
  406          * Set up frame for RX.
  407          */
frame->mii_stdelim = NGE_MII_STARTDELIM;
frame->mii_opcode = NGE_MII_READOP;
frame->mii_turnaround = 0;
frame->mii_data = 0;
CSR_WRITE_4(sc, NGE_MEAR, 0);
  415         /*
  416          * Turn on data xmit.
  417          */
SIO_SET(NGE_MEAR_MII_DIR);
nge_mii_sync(sc);
  422         /*
  423          * Send command/address info.
  424          */
nge_mii_send(sc, frame->mii_stdelim, 2);
nge_mii_send(sc, frame->mii_opcode, 2);
nge_mii_send(sc, frame->mii_phyaddr, 5);
nge_mii_send(sc, frame->mii_regaddr, 5);
  430         /* Idle bit */
SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA));
DELAY(1);
SIO_SET(NGE_MEAR_MII_CLK);
DELAY(1);
  436         /* Turn off xmit. */
SIO_CLR(NGE_MEAR_MII_DIR);
  438         /* Check for ack */
SIO_CLR(NGE_MEAR_MII_CLK);
DELAY(1);
ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
SIO_SET(NGE_MEAR_MII_CLK);
DELAY(1);
  445         /*
  446          * Now try reading data bits. If the ack failed, we still
  447          * need to clock through 16 cycles to keep the PHY(s) in sync.
  448          */
  449         if (ack) {
  450                 for(i = 0; i < 16; i++) {
SIO_CLR(NGE_MEAR_MII_CLK);
DELAY(1);
SIO_SET(NGE_MEAR_MII_CLK);
DELAY(1);
  455                 }
  456                 goto fail;
  457         }
  459         for (i = 0x8000; i; i >>= 1) {
SIO_CLR(NGE_MEAR_MII_CLK);
DELAY(1);
  462                 if (!ack) {
  463                         if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
frame->mii_data |= i;
DELAY(1);
  466                 }
SIO_SET(NGE_MEAR_MII_CLK);
DELAY(1);
  469         }
fail:
SIO_CLR(NGE_MEAR_MII_CLK);
DELAY(1);
SIO_SET(NGE_MEAR_MII_CLK);
DELAY(1);
splx(s);
  480         if (ack)
  481                 return(1);
  482         return(0);
  483 }
  485 /*
  486  * Write to a PHY register through the MII.
  487  */
  488 int
nge_mii_writereg(sc, frame)
  490         struct nge_softc                *sc;
  491         struct nge_mii_frame    *frame;
  492 {
  493         int                     s;
s = splnet();
  496         /*
  497          * Set up frame for TX.
  498          */
frame->mii_stdelim = NGE_MII_STARTDELIM;
frame->mii_opcode = NGE_MII_WRITEOP;
frame->mii_turnaround = NGE_MII_TURNAROUND;
  504         /*
  505          * Turn on data output.
  506          */
SIO_SET(NGE_MEAR_MII_DIR);
nge_mii_sync(sc);
nge_mii_send(sc, frame->mii_stdelim, 2);
nge_mii_send(sc, frame->mii_opcode, 2);
nge_mii_send(sc, frame->mii_phyaddr, 5);
nge_mii_send(sc, frame->mii_regaddr, 5);
nge_mii_send(sc, frame->mii_turnaround, 2);
nge_mii_send(sc, frame->mii_data, 16);
  518         /* Idle bit. */
SIO_SET(NGE_MEAR_MII_CLK);
DELAY(1);
SIO_CLR(NGE_MEAR_MII_CLK);
DELAY(1);
  524         /*
  525          * Turn off xmit.
  526          */
SIO_CLR(NGE_MEAR_MII_DIR);
splx(s);
  531         return(0);
  532 }
  534 int
nge_miibus_readreg(dev, phy, reg)
  536         struct device           *dev;
  537         int                     phy, reg;
  538 {
  539         struct nge_softc        *sc = (struct nge_softc *)dev;
  540         struct nge_mii_frame    frame;
DPRINTFN(9, ("%s: nge_miibus_readreg\n", sc->sc_dv.dv_xname));
bzero((char *)&frame, sizeof(frame));
frame.mii_phyaddr = phy;
frame.mii_regaddr = reg;
nge_mii_readreg(sc, &frame);
  550         return(frame.mii_data);
  551 }
  553 void
nge_miibus_writereg(dev, phy, reg, data)
  555         struct device           *dev;
  556         int                     phy, reg, data;
  557 {
  558         struct nge_softc        *sc = (struct nge_softc *)dev;
  559         struct nge_mii_frame    frame;
DPRINTFN(9, ("%s: nge_miibus_writereg\n", sc->sc_dv.dv_xname));
bzero((char *)&frame, sizeof(frame));
frame.mii_phyaddr = phy;
frame.mii_regaddr = reg;
frame.mii_data = data;
nge_mii_writereg(sc, &frame);
  570 }
  572 void
nge_miibus_statchg(dev)
  574         struct device           *dev;
  575 {
  576         struct nge_softc        *sc = (struct nge_softc *)dev;
  577         struct mii_data         *mii = &sc->nge_mii;
u_int32_t               txcfg, rxcfg;
txcfg = CSR_READ_4(sc, NGE_TX_CFG);
rxcfg = CSR_READ_4(sc, NGE_RX_CFG);
DPRINTFN(4, ("%s: nge_miibus_statchg txcfg=%#x, rxcfg=%#x\n",
sc->sc_dv.dv_xname, txcfg, rxcfg));
  586         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
txcfg |= (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR);
rxcfg |= (NGE_RXCFG_RX_FDX);
  589         } else {
txcfg &= ~(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR);
rxcfg &= ~(NGE_RXCFG_RX_FDX);
  592         }
txcfg |= NGE_TXCFG_AUTOPAD;
CSR_WRITE_4(sc, NGE_TX_CFG, txcfg);
CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg);
  599         /* If we have a 1000Mbps link, set the mode_1000 bit. */
  600         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
  602         else
NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
  604 }
  606 void
nge_setmulti(sc)
  608         struct nge_softc        *sc;
  609 {
  610         struct arpcom           *ac = &sc->arpcom;
  611         struct ifnet            *ifp = &ac->ac_if;
  612         struct ether_multi      *enm;
  613         struct ether_multistep  step;
u_int32_t               h = 0, i, filtsave;
  615         int                     bit, index;
allmulti:
  618         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
NGE_CLRBIT(sc, NGE_RXFILT_CTL,
NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH);
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
  622                 return;
  623         }
  625         /*
  626          * We have to explicitly enable the multicast hash table
  627          * on the NatSemi chip if we want to use it, which we do.
  628          * We also have to tell it that we don't want to use the
  629          * hash table for matching unicast addresses.
  630          */
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
NGE_CLRBIT(sc, NGE_RXFILT_CTL,
NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH);
filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
  637         /* first, zot all the existing hash bits */
  638         for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
  641         }
  643         /*
  644          * From the 11 bits returned by the crc routine, the top 7
  645          * bits represent the 16-bit word in the mcast hash table
  646          * that needs to be updated, and the lower 4 bits represent
  647          * which bit within that byte needs to be set.
  648          */
ETHER_FIRST_MULTI(step, ac, enm);
  650         while (enm != NULL) {
  651                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
ifp->if_flags |= IFF_ALLMULTI;
  653                         goto allmulti;
  654                 }
h = (ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 21) &
  656                     0x00000FFF;
index = (h >> 4) & 0x7F;
bit = h & 0xF;
CSR_WRITE_4(sc, NGE_RXFILT_CTL,
NGE_FILTADDR_MCAST_LO + (index * 2));
NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
ETHER_NEXT_MULTI(step, enm);
  663         }
CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
  666 }
  668 void
nge_reset(sc)
  670         struct nge_softc        *sc;
  671 {
  672         int                     i;
NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
  676         for (i = 0; i < NGE_TIMEOUT; i++) {
  677                 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
  678                         break;
  679         }
  681         if (i == NGE_TIMEOUT)
printf("%s: reset never completed\n", sc->sc_dv.dv_xname);
  684         /* Wait a little while for the chip to get its brains in order. */
DELAY(1000);
  687         /*
  688          * If this is a NetSemi chip, make sure to clear
  689          * PME mode.
  690          */
CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
CSR_WRITE_4(sc, NGE_CLKRUN, 0);
  693 }
  695 /*
  696  * Probe for an NatSemi chip. Check the PCI vendor and device
  697  * IDs against our list and return a device name if we find a match.
  698  */
  699 int
nge_probe(parent, match, aux)
  701         struct device *parent;
  702         void *match;
  703         void *aux;
  704 {
  705         struct pci_attach_args *pa = (struct pci_attach_args *)aux;
  707         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_DP83820)
  709                 return (1);
  711         return (0);
  712 }
  714 /*
  715  * Attach the interface. Allocate softc structures, do ifmedia
  716  * setup and ethernet/BPF attach.
  717  */
  718 void
nge_attach(parent, self, aux)
  720         struct device *parent, *self;
  721         void *aux;
  722 {
  723         struct nge_softc        *sc = (struct nge_softc *)self;
  724         struct pci_attach_args  *pa = aux;
pci_chipset_tag_t       pc = pa->pa_pc;
pci_intr_handle_t       ih;
  727         const char              *intrstr = NULL;
bus_size_t              size;
bus_dma_segment_t       seg;
bus_dmamap_t            dmamap;
  731         int                     rseg;
u_char                  eaddr[ETHER_ADDR_LEN];
pcireg_t                command;
  734 #ifndef NGE_USEIOSPACE
pcireg_t                memtype;
  736 #endif
  737         struct ifnet            *ifp;
caddr_t                 kva;
  740         /*
  741          * Handle power management nonsense.
  742          */
DPRINTFN(5, ("%s: preparing for conf read\n", sc->sc_dv.dv_xname));
command = pci_conf_read(pc, pa->pa_tag, NGE_PCI_CAPID) & 0x000000FF;
  745         if (command == 0x01) {
command = pci_conf_read(pc, pa->pa_tag, NGE_PCI_PWRMGMTCTRL);
  747                 if (command & NGE_PSTATE_MASK) {
pcireg_t        iobase, membase, irq;
  750                         /* Save important PCI config data. */
iobase = pci_conf_read(pc, pa->pa_tag, NGE_PCI_LOIO);
membase = pci_conf_read(pc, pa->pa_tag, NGE_PCI_LOMEM);
irq = pci_conf_read(pc, pa->pa_tag, NGE_PCI_INTLINE);
  755                         /* Reset the power state. */
printf("%s: chip is in D%d power mode "
  757                                "-- setting to D0\n", sc->sc_dv.dv_xname,
command & NGE_PSTATE_MASK);
command &= 0xFFFFFFFC;
pci_conf_write(pc, pa->pa_tag,
NGE_PCI_PWRMGMTCTRL, command);
  763                         /* Restore PCI config data. */
pci_conf_write(pc, pa->pa_tag, NGE_PCI_LOIO, iobase);
pci_conf_write(pc, pa->pa_tag, NGE_PCI_LOMEM, membase);
pci_conf_write(pc, pa->pa_tag, NGE_PCI_INTLINE, irq);
  767                 }
  768         }
  770         /*
  771          * Map control/status registers.
  772          */
DPRINTFN(5, ("%s: map control/status regs\n", sc->sc_dv.dv_xname));
  775 #ifdef NGE_USEIOSPACE
DPRINTFN(5, ("%s: pci_mapreg_map\n", sc->sc_dv.dv_xname));
  777         if (pci_mapreg_map(pa, NGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
  778             &sc->nge_btag, &sc->nge_bhandle, NULL, &size, 0)) {
printf(": can't map i/o space\n");
  780                 return;
  781         }
  782 #else
DPRINTFN(5, ("%s: pci_mapreg_map\n", sc->sc_dv.dv_xname));
memtype = pci_mapreg_type(pc, pa->pa_tag, NGE_PCI_LOMEM);
  785         switch (memtype) {
  786         case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
  787         case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
  788                 if (pci_mapreg_map(pa, NGE_PCI_LOMEM,
memtype, 0, &sc->nge_btag, &sc->nge_bhandle,
NULL, &size, 0) == 0)
  791                         break;
  792         default:
printf(": can't map mem space\n");
  794                 return;
  795         }
  796 #endif
  798         /* Disable all interrupts */
CSR_WRITE_4(sc, NGE_IER, 0);
DPRINTFN(5, ("%s: pci_intr_map\n", sc->sc_dv.dv_xname));
  802         if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
  804                 goto fail_1;
  805         }
DPRINTFN(5, ("%s: pci_intr_string\n", sc->sc_dv.dv_xname));
intrstr = pci_intr_string(pc, ih);
DPRINTFN(5, ("%s: pci_intr_establish\n", sc->sc_dv.dv_xname));
sc->nge_intrhand = pci_intr_establish(pc, ih, IPL_NET, nge_intr, sc,
sc->sc_dv.dv_xname);
  812         if (sc->nge_intrhand == NULL) {
printf(": couldn't establish interrupt");
  814                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
  817                 goto fail_1;
  818         }
printf(": %s", intrstr);
  821         /* Reset the adapter. */
DPRINTFN(5, ("%s: nge_reset\n", sc->sc_dv.dv_xname));
nge_reset(sc);
  825         /*
  826          * Get station address from the EEPROM.
  827          */
DPRINTFN(5, ("%s: nge_read_eeprom\n", sc->sc_dv.dv_xname));
nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0);
nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0);
nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0);
  833         /*
  834          * A NatSemi chip was detected. Inform the world.
  835          */
printf(", address %s\n", ether_sprintf(eaddr));
bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
sc->sc_dmatag = pa->pa_dmat;
DPRINTFN(5, ("%s: bus_dmamem_alloc\n", sc->sc_dv.dv_xname));
  842         if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct nge_list_data),
PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname);
  845                 goto fail_2;
  846         }
DPRINTFN(5, ("%s: bus_dmamem_map\n", sc->sc_dv.dv_xname));
  848         if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg,
  849                            sizeof(struct nge_list_data), &kva,
BUS_DMA_NOWAIT)) {
printf("%s: can't map dma buffers (%d bytes)\n",
sc->sc_dv.dv_xname, sizeof(struct nge_list_data));
  853                 goto fail_3;
  854         }
DPRINTFN(5, ("%s: bus_dmamem_create\n", sc->sc_dv.dv_xname));
  856         if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct nge_list_data), 1,
  857                               sizeof(struct nge_list_data), 0,
BUS_DMA_NOWAIT, &dmamap)) {
printf("%s: can't create dma map\n", sc->sc_dv.dv_xname);
  860                 goto fail_4;
  861         }
DPRINTFN(5, ("%s: bus_dmamem_load\n", sc->sc_dv.dv_xname));
  863         if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva,
  864                             sizeof(struct nge_list_data), NULL,
BUS_DMA_NOWAIT)) {
  866                 goto fail_5;
  867         }
DPRINTFN(5, ("%s: bzero\n", sc->sc_dv.dv_xname));
sc->nge_ldata = (struct nge_list_data *)kva;
bzero(sc->nge_ldata, sizeof(struct nge_list_data));
  873         /* Try to allocate memory for jumbo buffers. */
DPRINTFN(5, ("%s: nge_alloc_jumbo_mem\n", sc->sc_dv.dv_xname));
  875         if (nge_alloc_jumbo_mem(sc)) {
printf("%s: jumbo buffer allocation failed\n",
sc->sc_dv.dv_xname);
  878                 goto fail_5;
  879         }
ifp = &sc->arpcom.ac_if;
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = nge_ioctl;
ifp->if_start = nge_start;
ifp->if_watchdog = nge_watchdog;
ifp->if_baudrate = 1000000000;
ifp->if_hardmtu = NGE_JUMBO_MTU;
IFQ_SET_MAXLEN(&ifp->if_snd, NGE_TX_LIST_CNT - 1);
IFQ_SET_READY(&ifp->if_snd);
DPRINTFN(5, ("%s: bcopy\n", sc->sc_dv.dv_xname));
bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ);
ifp->if_capabilities = IFCAP_VLAN_MTU;
  896 #ifdef NGE_VLAN
ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
  898 #endif
  900         /*
  901          * Do MII setup.
  902          */
DPRINTFN(5, ("%s: mii setup\n", sc->sc_dv.dv_xname));
  904         if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
DPRINTFN(5, ("%s: TBI mode\n", sc->sc_dv.dv_xname));
sc->nge_tbi = 1;
ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_tbi_upd, 
nge_ifmedia_tbi_sts);
ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_NONE, 0, NULL),
ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX,
  914                             0, NULL);
ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
ifmedia_set(&sc->nge_ifmedia, IFM_ETHER|IFM_AUTO);
CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
  920                             | NGE_GPIO_GP4_OUT 
  921                             | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 
  922                             | NGE_GPIO_GP3_OUTENB | NGE_GPIO_GP4_OUTENB
  923                             | NGE_GPIO_GP5_OUTENB);
NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
  926         } else {
sc->nge_mii.mii_ifp = ifp;
sc->nge_mii.mii_readreg = nge_miibus_readreg;
sc->nge_mii.mii_writereg = nge_miibus_writereg;
sc->nge_mii.mii_statchg = nge_miibus_statchg;
ifmedia_init(&sc->nge_mii.mii_media, 0, nge_ifmedia_mii_upd,
nge_ifmedia_mii_sts);
mii_attach(&sc->sc_dv, &sc->nge_mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, 0);
  937                 if (LIST_FIRST(&sc->nge_mii.mii_phys) == NULL) {
printf("%s: no PHY found!\n", sc->sc_dv.dv_xname);
ifmedia_add(&sc->nge_mii.mii_media,
IFM_ETHER|IFM_MANUAL, 0, NULL);
ifmedia_set(&sc->nge_mii.mii_media,
IFM_ETHER|IFM_MANUAL);
  944                 }
  945                 else
ifmedia_set(&sc->nge_mii.mii_media,
IFM_ETHER|IFM_AUTO);
  948         }
  950         /*
  951          * Call MI attach routine.
  952          */
DPRINTFN(5, ("%s: if_attach\n", sc->sc_dv.dv_xname));
if_attach(ifp);
DPRINTFN(5, ("%s: ether_ifattach\n", sc->sc_dv.dv_xname));
ether_ifattach(ifp);
DPRINTFN(5, ("%s: timeout_set\n", sc->sc_dv.dv_xname));
timeout_set(&sc->nge_timeout, nge_tick, sc);
timeout_add(&sc->nge_timeout, hz);
  960         return;
fail_5:
bus_dmamap_destroy(sc->sc_dmatag, dmamap);
fail_4:
bus_dmamem_unmap(sc->sc_dmatag, kva,
  967             sizeof(struct nge_list_data));
fail_3:
bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
fail_2:
pci_intr_disestablish(pc, sc->nge_intrhand);
fail_1:
bus_space_unmap(sc->nge_btag, sc->nge_bhandle, size);
  977 }
  979 /*
  980  * Initialize the transmit descriptors.
  981  */
  982 int
nge_list_tx_init(sc)
  984         struct nge_softc        *sc;
  985 {
  986         struct nge_list_data    *ld;
  987         struct nge_ring_data    *cd;
  988         int                     i;
cd = &sc->nge_cdata;
ld = sc->nge_ldata;
  993         for (i = 0; i < NGE_TX_LIST_CNT; i++) {
  994                 if (i == (NGE_TX_LIST_CNT - 1)) {
ld->nge_tx_list[i].nge_nextdesc =
  996                             &ld->nge_tx_list[0];
ld->nge_tx_list[i].nge_next =
VTOPHYS(&ld->nge_tx_list[0]);
  999                 } else {
ld->nge_tx_list[i].nge_nextdesc =
 1001                             &ld->nge_tx_list[i + 1];
ld->nge_tx_list[i].nge_next =
VTOPHYS(&ld->nge_tx_list[i + 1]);
 1004                 }
ld->nge_tx_list[i].nge_mbuf = NULL;
ld->nge_tx_list[i].nge_ptr = 0;
ld->nge_tx_list[i].nge_ctl = 0;
 1008         }
cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
 1012         return(0);
 1013 }
 1016 /*
 1017  * Initialize the RX descriptors and allocate mbufs for them. Note that
 1018  * we arrange the descriptors in a closed ring, so that the last descriptor
 1019  * points back to the first.
 1020  */
 1021 int
nge_list_rx_init(sc)
 1023         struct nge_softc        *sc;
 1024 {
 1025         struct nge_list_data    *ld;
 1026         struct nge_ring_data    *cd;
 1027         int                     i;
ld = sc->nge_ldata;
cd = &sc->nge_cdata;
 1032         for (i = 0; i < NGE_RX_LIST_CNT; i++) {
 1033                 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
 1034                         return(ENOBUFS);
 1035                 if (i == (NGE_RX_LIST_CNT - 1)) {
ld->nge_rx_list[i].nge_nextdesc =
 1037                             &ld->nge_rx_list[0];
ld->nge_rx_list[i].nge_next =
VTOPHYS(&ld->nge_rx_list[0]);
 1040                 } else {
ld->nge_rx_list[i].nge_nextdesc =
 1042                             &ld->nge_rx_list[i + 1];
ld->nge_rx_list[i].nge_next =
VTOPHYS(&ld->nge_rx_list[i + 1]);
 1045                 }
 1046         }
cd->nge_rx_prod = 0;
 1050         return(0);
 1051 }
 1053 /*
 1054  * Initialize an RX descriptor and attach an MBUF cluster.
 1055  */
 1056 int
nge_newbuf(sc, c, m)
 1058         struct nge_softc        *sc;
 1059         struct nge_desc         *c;
 1060         struct mbuf             *m;
 1061 {
 1062         struct mbuf             *m_new = NULL;
 1064         if (m == NULL) {
caddr_t buf = NULL;
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1068                 if (m_new == NULL)
 1069                         return (ENOBUFS);
 1071                 /* Allocate the jumbo buffer */
buf = nge_jalloc(sc);
 1073                 if (buf == NULL) {
m_freem(m_new);
 1075                         return (ENOBUFS);
 1076                 }
 1078                 /* Attach the buffer to the mbuf */
m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES;
MEXTADD(m_new, buf, NGE_MCLBYTES, 0, nge_jfree, sc);
 1081         } else {
 1082                 /*
 1083                  * We're re-using a previously allocated mbuf;
 1084                  * be sure to re-init pointers and lengths to
 1085                  * default values.
 1086                  */
m_new = m;
m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES;
m_new->m_data = m_new->m_ext.ext_buf;
 1090         }
m_adj(m_new, sizeof(u_int64_t));
c->nge_mbuf = m_new;
c->nge_ptr = VTOPHYS(mtod(m_new, caddr_t));
DPRINTFN(7,("%s: c->nge_ptr=%#x\n", sc->sc_dv.dv_xname,
c->nge_ptr));
c->nge_ctl = m_new->m_len;
c->nge_extsts = 0;
 1101         return(0);
 1102 }
 1104 int
nge_alloc_jumbo_mem(sc)
 1106         struct nge_softc        *sc;
 1107 {
caddr_t                 ptr, kva;
bus_dma_segment_t       seg;
bus_dmamap_t            dmamap;
 1111         int                     i, rseg, state, error;
 1112         struct nge_jpool_entry  *entry;
state = error = 0;
 1116         if (bus_dmamem_alloc(sc->sc_dmatag, NGE_JMEM, PAGE_SIZE, 0,
 1117                              &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname);
 1119                 return (ENOBUFS);
 1120         }
state = 1;
 1123         if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, NGE_JMEM, &kva,
BUS_DMA_NOWAIT)) {
printf("%s: can't map dma buffers (%d bytes)\n",
sc->sc_dv.dv_xname, NGE_JMEM);
error = ENOBUFS;
 1128                 goto out;
 1129         }
state = 2;
 1132         if (bus_dmamap_create(sc->sc_dmatag, NGE_JMEM, 1,
NGE_JMEM, 0, BUS_DMA_NOWAIT, &dmamap)) {
printf("%s: can't create dma map\n", sc->sc_dv.dv_xname);
error = ENOBUFS;
 1136                 goto out;
 1137         }
state = 3;
 1140         if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, NGE_JMEM,
NULL, BUS_DMA_NOWAIT)) {
printf("%s: can't load dma map\n", sc->sc_dv.dv_xname);
error = ENOBUFS;
 1144                 goto out;
 1145         }
state = 4;
sc->nge_cdata.nge_jumbo_buf = (caddr_t)kva;
DPRINTFN(1,("%s: nge_jumbo_buf=%#x, NGE_MCLBYTES=%#x\n",
sc->sc_dv.dv_xname , sc->nge_cdata.nge_jumbo_buf,
NGE_MCLBYTES));
LIST_INIT(&sc->nge_jfree_listhead);
LIST_INIT(&sc->nge_jinuse_listhead);
 1156         /*
 1157          * Now divide it up into 9K pieces and save the addresses
 1158          * in an array. Note that we play an evil trick here by using
 1159          * the first few bytes in the buffer to hold the address
 1160          * of the softc structure for this interface. This is because
 1161          * nge_jfree() needs it, but it is called by the mbuf management
 1162          * code which will not pass it to us explicitly.
 1163          */
ptr = sc->nge_cdata.nge_jumbo_buf;
 1165         for (i = 0; i < NGE_JSLOTS; i++) {
sc->nge_cdata.nge_jslots[i].nge_buf = ptr;
sc->nge_cdata.nge_jslots[i].nge_inuse = 0;
ptr += NGE_MCLBYTES;
entry = malloc(sizeof(struct nge_jpool_entry),
M_DEVBUF, M_NOWAIT);
 1171                 if (entry == NULL) {
sc->nge_cdata.nge_jumbo_buf = NULL;
printf("%s: no memory for jumbo buffer queue!\n",
sc->sc_dv.dv_xname);
error = ENOBUFS;
 1176                         goto out;
 1177                 }
entry->slot = i;
LIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry,
jpool_entries);
 1181         }
out:
 1183         if (error != 0) {
 1184                 switch (state) {
 1185                 case 4:
bus_dmamap_unload(sc->sc_dmatag, dmamap);
 1187                 case 3:
bus_dmamap_destroy(sc->sc_dmatag, dmamap);
 1189                 case 2:
bus_dmamem_unmap(sc->sc_dmatag, kva, NGE_JMEM);
 1191                 case 1:
bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
 1193                         break;
 1194                 default:
 1195                         break;
 1196                 }
 1197         }
 1199         return (error);
 1200 }
 1202 /*
 1203  * Allocate a jumbo buffer.
 1204  */
 1205 void *
nge_jalloc(sc)
 1207         struct nge_softc        *sc;
 1208 {
 1209         struct nge_jpool_entry   *entry;
entry = LIST_FIRST(&sc->nge_jfree_listhead);
 1213         if (entry == NULL)
 1214                 return (NULL);
LIST_REMOVE(entry, jpool_entries);
LIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries);
sc->nge_cdata.nge_jslots[entry->slot].nge_inuse = 1;
 1219         return(sc->nge_cdata.nge_jslots[entry->slot].nge_buf);
 1220 }
 1222 /*
 1223  * Release a jumbo buffer.
 1224  */
 1225 void
nge_jfree(buf, size, arg)
caddr_t         buf;
u_int           size;
 1229         void            *arg;
 1230 {
 1231         struct nge_softc        *sc;
 1232         int                     i;
 1233         struct nge_jpool_entry *entry;
 1235         /* Extract the softc struct pointer. */
sc = (struct nge_softc *)arg;
 1238         if (sc == NULL)
panic("nge_jfree: can't find softc pointer!");
 1241         /* calculate the slot this buffer belongs to */
i = ((vaddr_t)buf - (vaddr_t)sc->nge_cdata.nge_jumbo_buf)
 1244           / NGE_MCLBYTES;
 1246         if ((i < 0) || (i >= NGE_JSLOTS))
panic("nge_jfree: asked to free buffer that we don't manage!");
 1248         else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0)
panic("nge_jfree: buffer already free!");
 1250         else {
sc->nge_cdata.nge_jslots[i].nge_inuse--;
 1252                 if(sc->nge_cdata.nge_jslots[i].nge_inuse == 0) {
entry = LIST_FIRST(&sc->nge_jinuse_listhead);
 1254                         if (entry == NULL)
panic("nge_jfree: buffer not in use!");
entry->slot = i;
LIST_REMOVE(entry, jpool_entries);
LIST_INSERT_HEAD(&sc->nge_jfree_listhead,
entry, jpool_entries);
 1260                 }
 1261         }
 1262 }
 1264 /*
 1265  * A frame has been uploaded: pass the resulting mbuf chain up to
 1266  * the higher level protocols.
 1267  */
 1268 void
nge_rxeof(sc)
 1270         struct nge_softc        *sc;
 1271 {
 1272         struct mbuf             *m;
 1273         struct ifnet            *ifp;
 1274         struct nge_desc         *cur_rx;
 1275         int                     i, total_len = 0;
u_int32_t               rxstat;
ifp = &sc->arpcom.ac_if;
i = sc->nge_cdata.nge_rx_prod;
 1281         while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
 1282                 struct mbuf             *m0 = NULL;
u_int32_t               extsts;
cur_rx = &sc->nge_ldata->nge_rx_list[i];
rxstat = cur_rx->nge_rxstat;
extsts = cur_rx->nge_extsts;
m = cur_rx->nge_mbuf;
cur_rx->nge_mbuf = NULL;
total_len = NGE_RXBYTES(cur_rx);
NGE_INC(i, NGE_RX_LIST_CNT);
 1293                 /*
 1294                  * If an error occurs, update stats, clear the
 1295                  * status word and leave the mbuf cluster in place:
 1296                  * it should simply get re-used next time this descriptor
 1297                  * comes up in the ring.
 1298                  */
 1299                 if (!(rxstat & NGE_CMDSTS_PKT_OK)) {
ifp->if_ierrors++;
nge_newbuf(sc, cur_rx, m);
 1302                         continue;
 1303                 }
 1305                 /*
 1306                  * Ok. NatSemi really screwed up here. This is the
 1307                  * only gigE chip I know of with alignment constraints
 1308                  * on receive buffers. RX buffers must be 64-bit aligned.
 1309                  */
 1310 #ifndef __STRICT_ALIGNMENT
 1311                 /*
 1312                  * By popular demand, ignore the alignment problems
 1313                  * on the Intel x86 platform. The performance hit
 1314                  * incurred due to unaligned accesses is much smaller
 1315                  * than the hit produced by forcing buffer copies all
 1316                  * the time, especially with jumbo frames. We still
 1317                  * need to fix up the alignment everywhere else though.
 1318                  */
 1319                 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
 1320 #endif
m0 = m_devget(mtod(m, char *), total_len,
ETHER_ALIGN, ifp, NULL);
nge_newbuf(sc, cur_rx, m);
 1324                         if (m0 == NULL) {
ifp->if_ierrors++;
 1326                                 continue;
 1327                         }
m_adj(m0, ETHER_ALIGN);
m = m0;
 1330 #ifndef __STRICT_ALIGNMENT
 1331                 } else {
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = m->m_len = total_len;
 1334                 }
 1335 #endif
ifp->if_ipackets++;
 1339 #if NBPFILTER > 0
 1340                 /*
 1341                  * Handle BPF listeners. Let the BPF user see the packet.
 1342                  */
 1343                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
 1345 #endif
 1347                 /* Do IP checksum checking. */
 1348                 if (extsts & NGE_RXEXTSTS_IPPKT) {
 1349                         if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK;
 1351                         if ((extsts & NGE_RXEXTSTS_TCPPKT) &&
 1352                             (!(extsts & NGE_RXEXTSTS_TCPCSUMERR)))
m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK;
 1354                         else if ((extsts & NGE_RXEXTSTS_UDPPKT) &&
 1355                                  (!(extsts & NGE_RXEXTSTS_UDPCSUMERR)))
m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK;
 1357                 }
ether_input_mbuf(ifp, m);
 1360         }
sc->nge_cdata.nge_rx_prod = i;
 1363 }
 1365 /*
 1366  * A frame was downloaded to the chip. It's safe for us to clean up
 1367  * the list buffers.
 1368  */
 1370 void
nge_txeof(sc)
 1372         struct nge_softc        *sc;
 1373 {
 1374         struct nge_desc         *cur_tx;
 1375         struct ifnet            *ifp;
u_int32_t               idx;
ifp = &sc->arpcom.ac_if;
 1380         /*
 1381          * Go through our tx list and free mbufs for those
 1382          * frames that have been transmitted.
 1383          */
idx = sc->nge_cdata.nge_tx_cons;
 1385         while (idx != sc->nge_cdata.nge_tx_prod) {
cur_tx = &sc->nge_ldata->nge_tx_list[idx];
 1388                 if (NGE_OWNDESC(cur_tx))
 1389                         break;
 1391                 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
sc->nge_cdata.nge_tx_cnt--;
NGE_INC(idx, NGE_TX_LIST_CNT);
 1394                         continue;
 1395                 }
 1397                 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
ifp->if_oerrors++;
 1399                         if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
ifp->if_collisions++;
 1401                         if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
ifp->if_collisions++;
 1403                 }
ifp->if_collisions +=
 1406                     (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
ifp->if_opackets++;
 1409                 if (cur_tx->nge_mbuf != NULL) {
m_freem(cur_tx->nge_mbuf);
cur_tx->nge_mbuf = NULL;
ifp->if_flags &= ~IFF_OACTIVE;
 1413                 }
sc->nge_cdata.nge_tx_cnt--;
NGE_INC(idx, NGE_TX_LIST_CNT);
 1417         }
sc->nge_cdata.nge_tx_cons = idx;
 1421         if (idx == sc->nge_cdata.nge_tx_prod)
ifp->if_timer = 0;
 1423 }
 1425 void
nge_tick(xsc)
 1427         void                    *xsc;
 1428 {
 1429         struct nge_softc        *sc = xsc;
 1430         struct mii_data         *mii = &sc->nge_mii;
 1431         struct ifnet            *ifp = &sc->arpcom.ac_if;
 1432         int                     s;
s = splnet();
DPRINTFN(10, ("%s: nge_tick: link=%d\n", sc->sc_dv.dv_xname,
sc->nge_link));
timeout_add(&sc->nge_timeout, hz);
 1440         if (sc->nge_link) {
splx(s);
 1442                 return;
 1443         }
 1445         if (sc->nge_tbi) {
 1446                 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
 1447                     == IFM_AUTO) {
u_int32_t bmsr, anlpar, txcfg, rxcfg;
bmsr = CSR_READ_4(sc, NGE_TBI_BMSR);
DPRINTFN(2, ("%s: nge_tick: bmsr=%#x\n",
sc->sc_dv.dv_xname, bmsr));
 1454                         if (!(bmsr & NGE_TBIBMSR_ANEG_DONE)) {
CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
splx(s);
 1458                                 return;
 1459                         }
anlpar = CSR_READ_4(sc, NGE_TBI_ANLPAR);
txcfg = CSR_READ_4(sc, NGE_TX_CFG);
rxcfg = CSR_READ_4(sc, NGE_RX_CFG);
DPRINTFN(2, ("%s: nge_tick: anlpar=%#x, txcfg=%#x, "
 1466                                      "rxcfg=%#x\n", sc->sc_dv.dv_xname, anlpar,
txcfg, rxcfg));
 1469                         if (anlpar == 0 || anlpar & NGE_TBIANAR_FDX) {
txcfg |= (NGE_TXCFG_IGN_HBEAT|
NGE_TXCFG_IGN_CARR);
rxcfg |= NGE_RXCFG_RX_FDX;
 1473                         } else {
txcfg &= ~(NGE_TXCFG_IGN_HBEAT|
NGE_TXCFG_IGN_CARR);
rxcfg &= ~(NGE_RXCFG_RX_FDX);
 1477                         }
txcfg |= NGE_TXCFG_AUTOPAD;
CSR_WRITE_4(sc, NGE_TX_CFG, txcfg);
CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg);
 1481                 }
DPRINTF(("%s: gigabit link up\n", sc->sc_dv.dv_xname));
sc->nge_link++;
 1485                 if (!IFQ_IS_EMPTY(&ifp->if_snd))
nge_start(ifp);
 1487         } else {
mii_tick(mii);
 1489                 if (mii->mii_media_status & IFM_ACTIVE &&
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
sc->nge_link++;
 1492                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
DPRINTF(("%s: gigabit link up\n",
sc->sc_dv.dv_xname));
 1495                         if (!IFQ_IS_EMPTY(&ifp->if_snd))
nge_start(ifp);
 1497                 }
 1499         }
splx(s);
 1502 }
 1504 int
nge_intr(arg)
 1506         void                    *arg;
 1507 {
 1508         struct nge_softc        *sc;
 1509         struct ifnet            *ifp;
u_int32_t               status;
 1511         int                     claimed = 0;
sc = arg;
ifp = &sc->arpcom.ac_if;
 1516         /* Supress unwanted interrupts */
 1517         if (!(ifp->if_flags & IFF_UP)) {
nge_stop(sc);
 1519                 return (0);
 1520         }
 1522         /* Disable interrupts. */
CSR_WRITE_4(sc, NGE_IER, 0);
 1525         /* Data LED on for TBI mode */
 1526         if(sc->nge_tbi)
CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
 1528                              | NGE_GPIO_GP3_OUT);
 1530         for (;;) {
 1531                 /* Reading the ISR register clears all interrupts. */
status = CSR_READ_4(sc, NGE_ISR);
 1534                 if ((status & NGE_INTRS) == 0)
 1535                         break;
claimed = 1;
 1539                 if ((status & NGE_ISR_TX_DESC_OK) ||
 1540                     (status & NGE_ISR_TX_ERR) ||
 1541                     (status & NGE_ISR_TX_OK) ||
 1542                     (status & NGE_ISR_TX_IDLE))
nge_txeof(sc);
 1545                 if ((status & NGE_ISR_RX_DESC_OK) ||
 1546                     (status & NGE_ISR_RX_ERR) ||
 1547                     (status & NGE_ISR_RX_OFLOW) ||
 1548                     (status & NGE_ISR_RX_FIFO_OFLOW) ||
 1549                     (status & NGE_ISR_RX_IDLE) ||
 1550                     (status & NGE_ISR_RX_OK))
nge_rxeof(sc);
 1553                 if ((status & NGE_ISR_RX_IDLE))
NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
 1556                 if (status & NGE_ISR_SYSERR) {
nge_reset(sc);
ifp->if_flags &= ~IFF_RUNNING;
nge_init(sc);
 1560                 }
 1562 #if 0
 1563                 /* 
 1564                  * XXX: nge_tick() is not ready to be called this way
 1565                  * it screws up the aneg timeout because mii_tick() is
 1566                  * only to be called once per second.
 1567                  */
 1568                 if (status & NGE_IMR_PHY_INTR) {
sc->nge_link = 0;
nge_tick(sc);
 1571                 }
 1572 #endif
 1573         }
 1575         /* Re-enable interrupts. */
CSR_WRITE_4(sc, NGE_IER, 1);
 1578         if (!IFQ_IS_EMPTY(&ifp->if_snd))
nge_start(ifp);
 1581         /* Data LED off for TBI mode */
 1582         if(sc->nge_tbi)
CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
 1584                             & ~NGE_GPIO_GP3_OUT);
 1586         return claimed;
 1587 }
 1589 /*
 1590  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
 1591  * pointers to the fragment pointers.
 1592  */
 1593 int
nge_encap(sc, m_head, txidx)
 1595         struct nge_softc        *sc;
 1596         struct mbuf             *m_head;
u_int32_t               *txidx;
 1598 {
 1599         struct nge_desc         *f = NULL;
 1600         struct mbuf             *m;
 1601         int                     frag, cur, cnt = 0;
 1602 #if NVLAN > 0
 1603         struct ifvlan           *ifv = NULL;
 1605         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
m_head->m_pkthdr.rcvif != NULL)
ifv = m_head->m_pkthdr.rcvif->if_softc;
 1608 #endif
 1610         /*
 1611          * Start packing the mbufs in this chain into
 1612          * the fragment pointers. Stop when we run out
 1613          * of fragments or hit the end of the mbuf chain.
 1614          */
m = m_head;
cur = frag = *txidx;
 1618         for (m = m_head; m != NULL; m = m->m_next) {
 1619                 if (m->m_len != 0) {
 1620                         if ((NGE_TX_LIST_CNT -
 1621                             (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
 1622                                 return(ENOBUFS);
f = &sc->nge_ldata->nge_tx_list[frag];
f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
f->nge_ptr = VTOPHYS(mtod(m, vaddr_t));
DPRINTFN(7,("%s: f->nge_ptr=%#x\n",
sc->sc_dv.dv_xname, f->nge_ptr));
 1628                         if (cnt != 0)
f->nge_ctl |= NGE_CMDSTS_OWN;
cur = frag;
NGE_INC(frag, NGE_TX_LIST_CNT);
cnt++;
 1633                 }
 1634         }
 1636         if (m != NULL)
 1637                 return(ENOBUFS);
sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
 1641 #if NVLAN > 0
 1642         if (ifv != NULL) {
sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
 1644                         (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag);
 1645         }
 1646 #endif
sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
sc->nge_cdata.nge_tx_cnt += cnt;
 1652         *txidx = frag;
 1654         return(0);
 1655 }
 1657 /*
 1658  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 1659  * to the mbuf data regions directly in the transmit lists. We also save a
 1660  * copy of the pointers since the transmit list fragment pointers are
 1661  * physical addresses.
 1662  */
 1664 void
nge_start(ifp)
 1666         struct ifnet            *ifp;
 1667 {
 1668         struct nge_softc        *sc;
 1669         struct mbuf             *m_head = NULL;
u_int32_t               idx;
 1671         int                     pkts = 0;
sc = ifp->if_softc;
 1675         if (!sc->nge_link)
 1676                 return;
idx = sc->nge_cdata.nge_tx_prod;
 1680         if (ifp->if_flags & IFF_OACTIVE)
 1681                 return;
 1683         while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
IFQ_POLL(&ifp->if_snd, m_head);
 1685                 if (m_head == NULL)
 1686                         break;
 1688                 if (nge_encap(sc, m_head, &idx)) {
ifp->if_flags |= IFF_OACTIVE;
 1690                         break;
 1691                 }
 1693                 /* now we are committed to transmit the packet */
IFQ_DEQUEUE(&ifp->if_snd, m_head);
pkts++;
 1697 #if NBPFILTER > 0
 1698                 /*
 1699                  * If there's a BPF listener, bounce a copy of this frame
 1700                  * to him.
 1701                  */
 1702                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT);
 1704 #endif
 1705         }
 1706         if (pkts == 0)
 1707                 return;
 1709         /* Transmit */
sc->nge_cdata.nge_tx_prod = idx;
NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
 1713         /*
 1714          * Set a timeout in case the chip goes out to lunch.
 1715          */
ifp->if_timer = 5;
 1717 }
 1719 void
nge_init(xsc)
 1721         void                    *xsc;
 1722 {
 1723         struct nge_softc        *sc = xsc;
 1724         struct ifnet            *ifp = &sc->arpcom.ac_if;
 1725         struct mii_data         *mii;
u_int32_t               txcfg, rxcfg;
 1727         int                     s, media;
 1729         if (ifp->if_flags & IFF_RUNNING)
 1730                 return;
s = splnet();
 1734         /*
 1735          * Cancel pending I/O and free all RX/TX buffers.
 1736          */
nge_stop(sc);
mii = sc->nge_tbi ? NULL: &sc->nge_mii;
 1741         /* Set MAC address */
CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
CSR_WRITE_4(sc, NGE_RXFILT_DATA,
 1744             ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
CSR_WRITE_4(sc, NGE_RXFILT_DATA,
 1747             ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
CSR_WRITE_4(sc, NGE_RXFILT_DATA,
 1750             ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
 1752         /* Init circular RX list. */
 1753         if (nge_list_rx_init(sc) == ENOBUFS) {
printf("%s: initialization failed: no "
 1755                         "memory for rx buffers\n", sc->sc_dv.dv_xname);
nge_stop(sc);
splx(s);
 1758                 return;
 1759         }
 1761         /*
 1762          * Init tx descriptors.
 1763          */
nge_list_tx_init(sc);
 1766         /*
 1767          * For the NatSemi chip, we have to explicitly enable the
 1768          * reception of ARP frames, as well as turn on the 'perfect
 1769          * match' filter where we store the station address, otherwise
 1770          * we won't receive unicasts meant for this host.
 1771          */
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
 1775          /* If we want promiscuous mode, set the allframes bit. */
 1776         if (ifp->if_flags & IFF_PROMISC)
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
 1778         else
NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
 1781         /*
 1782          * Set the capture broadcast bit to capture broadcast frames.
 1783          */
 1784         if (ifp->if_flags & IFF_BROADCAST)
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
 1786         else
NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
 1789         /*
 1790          * Load the multicast filter.
 1791          */
nge_setmulti(sc);
 1794         /* Turn the receive filter on */
NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
 1797         /*
 1798          * Load the address of the RX and TX lists.
 1799          */
CSR_WRITE_4(sc, NGE_RX_LISTPTR,
VTOPHYS(&sc->nge_ldata->nge_rx_list[0]));
CSR_WRITE_4(sc, NGE_TX_LISTPTR,
VTOPHYS(&sc->nge_ldata->nge_tx_list[0]));
 1805         /* Set RX configuration */
CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
 1808         /*
 1809          * Enable hardware checksum validation for all IPv4
 1810          * packets, do not reject packets with bad checksums.
 1811          */
CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
 1814         /* Set TX configuration */
CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
 1817 #if NVLAN > 0
 1818         /*
 1819          * If VLAN support is enabled, tell the chip to insert
 1820          * VLAN tags on a per-packet basis as dictated by the
 1821          * code in the frame encapsulation routine.
 1822          */
 1823         if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)
NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
 1825 #endif
 1827         /* Set full/half duplex mode. */
 1828         if (sc->nge_tbi)
media = sc->nge_ifmedia.ifm_cur->ifm_media;
 1830         else
media = mii->mii_media_active;
txcfg = CSR_READ_4(sc, NGE_TX_CFG);
rxcfg = CSR_READ_4(sc, NGE_RX_CFG);
DPRINTFN(4, ("%s: nge_init txcfg=%#x, rxcfg=%#x\n",
sc->sc_dv.dv_xname, txcfg, rxcfg));
 1839         if ((media & IFM_GMASK) == IFM_FDX) {
txcfg |= (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR);
rxcfg |= (NGE_RXCFG_RX_FDX);
 1842         } else {
txcfg &= ~(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR);
rxcfg &= ~(NGE_RXCFG_RX_FDX);
 1845         }
txcfg |= NGE_TXCFG_AUTOPAD;
CSR_WRITE_4(sc, NGE_TX_CFG, txcfg);
CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg);
nge_tick(sc);
 1854         /*
 1855          * Enable the delivery of PHY interrupts based on
 1856          * link/speed/duplex status changes and enable return
 1857          * of extended status information in the DMA descriptors,
 1858          * required for checksum offloading.
 1859          */
NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|NGE_CFG_PHYINTR_LNK|
NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB);
DPRINTFN(1, ("%s: nge_init: config=%#x\n", sc->sc_dv.dv_xname,
CSR_READ_4(sc, NGE_CFG)));
 1866         /*
 1867          * Configure interrupt holdoff (moderation). We can
 1868          * have the chip delay interrupt delivery for a certain
 1869          * period. Units are in 100us, and the max setting
 1870          * is 25500us (0xFF x 100us). Default is a 100us holdoff.
 1871          */
CSR_WRITE_4(sc, NGE_IHR, 0x01);
 1874         /*
 1875          * Enable interrupts.
 1876          */
CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
CSR_WRITE_4(sc, NGE_IER, 1);
 1880         /* Enable receiver and transmitter. */
NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
 1884         if (sc->nge_tbi)
nge_ifmedia_tbi_upd(ifp);
 1886         else
nge_ifmedia_mii_upd(ifp);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
splx(s);
 1893 }
 1895 /*
 1896  * Set mii media options.
 1897  */
 1898 int
nge_ifmedia_mii_upd(ifp)
 1900         struct ifnet            *ifp;
 1901 {
 1902         struct nge_softc        *sc = ifp->if_softc;
 1903         struct mii_data         *mii = &sc->nge_mii;
DPRINTFN(2, ("%s: nge_ifmedia_mii_upd\n", sc->sc_dv.dv_xname));
sc->nge_link = 0;
 1909         if (mii->mii_instance) {
 1910                 struct mii_softc *miisc;
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
mii_phy_reset(miisc);
 1913         }
mii_mediachg(mii);
 1916         return(0);
 1917 }
 1919 /*
 1920  * Report current mii media status.
 1921  */
 1922 void
nge_ifmedia_mii_sts(ifp, ifmr)
 1924         struct ifnet            *ifp;
 1925         struct ifmediareq       *ifmr;
 1926 {
 1927         struct nge_softc        *sc = ifp->if_softc;
 1928         struct mii_data *mii = &sc->nge_mii;
DPRINTFN(2, ("%s: nge_ifmedia_mii_sts\n", sc->sc_dv.dv_xname));
mii_pollstat(mii);
ifmr->ifm_active = mii->mii_media_active;
ifmr->ifm_status = mii->mii_media_status;
 1935 }
 1937 /*
 1938  * Set mii media options.
 1939  */
 1940 int
nge_ifmedia_tbi_upd(ifp)
 1942         struct ifnet            *ifp;
 1943 {
 1944         struct nge_softc        *sc = ifp->if_softc;
DPRINTFN(2, ("%s: nge_ifmedia_tbi_upd\n", sc->sc_dv.dv_xname));
sc->nge_link = 0;
 1950         if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 
 1951             == IFM_AUTO) {
u_int32_t anar, bmcr;
anar = CSR_READ_4(sc, NGE_TBI_ANAR);
anar |= (NGE_TBIANAR_HDX | NGE_TBIANAR_FDX);
CSR_WRITE_4(sc, NGE_TBI_ANAR, anar);
bmcr = CSR_READ_4(sc, NGE_TBI_BMCR);
bmcr |= (NGE_TBIBMCR_ENABLE_ANEG|NGE_TBIBMCR_RESTART_ANEG);
CSR_WRITE_4(sc, NGE_TBI_BMCR, bmcr);
bmcr &= ~(NGE_TBIBMCR_RESTART_ANEG);
CSR_WRITE_4(sc, NGE_TBI_BMCR, bmcr);
 1963         } else {
u_int32_t txcfg, rxcfg;
txcfg = CSR_READ_4(sc, NGE_TX_CFG);
rxcfg = CSR_READ_4(sc, NGE_RX_CFG);
 1968                 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
 1969                     == IFM_FDX) {
txcfg |= NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR;
rxcfg |= NGE_RXCFG_RX_FDX;
 1972                 } else {
txcfg &= ~(NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR);
rxcfg &= ~(NGE_RXCFG_RX_FDX);
 1975                 }
txcfg |= NGE_TXCFG_AUTOPAD;
CSR_WRITE_4(sc, NGE_TX_CFG, txcfg);
CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg);
 1980         }
NGE_CLRBIT(sc, NGE_GPIO, NGE_GPIO_GP3_OUT);
 1984         return(0);
 1985 }
 1987 /*
 1988  * Report current tbi media status.
 1989  */
 1990 void
nge_ifmedia_tbi_sts(ifp, ifmr)
 1992         struct ifnet            *ifp;
 1993         struct ifmediareq       *ifmr;
 1994 {
 1995         struct nge_softc        *sc = ifp->if_softc;
u_int32_t               bmcr;
bmcr = CSR_READ_4(sc, NGE_TBI_BMCR);
 2000         if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) == IFM_AUTO) {
u_int32_t bmsr = CSR_READ_4(sc, NGE_TBI_BMSR);
DPRINTFN(2, ("%s: nge_ifmedia_tbi_sts bmsr=%#x, bmcr=%#x\n",
sc->sc_dv.dv_xname, bmsr, bmcr));
 2005                 if (!(bmsr & NGE_TBIBMSR_ANEG_DONE)) {
ifmr->ifm_active = IFM_ETHER|IFM_NONE;
ifmr->ifm_status = IFM_AVALID;
 2008                         return;
 2009                 }
 2010         } else {
DPRINTFN(2, ("%s: nge_ifmedia_tbi_sts bmcr=%#x\n",
sc->sc_dv.dv_xname, bmcr));
 2013         }
ifmr->ifm_status = IFM_AVALID|IFM_ACTIVE;
ifmr->ifm_active = IFM_ETHER|IFM_1000_SX;
 2018         if (bmcr & NGE_TBIBMCR_LOOPBACK)
ifmr->ifm_active |= IFM_LOOP;
 2021         if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) == IFM_AUTO) {
u_int32_t anlpar = CSR_READ_4(sc, NGE_TBI_ANLPAR);
DPRINTFN(2, ("%s: nge_ifmedia_tbi_sts anlpar=%#x\n",
sc->sc_dv.dv_xname, anlpar));
ifmr->ifm_active |= IFM_AUTO;
 2027                 if (anlpar & NGE_TBIANLPAR_FDX) {
ifmr->ifm_active |= IFM_FDX;
 2029                 } else if (anlpar & NGE_TBIANLPAR_HDX) {
ifmr->ifm_active |= IFM_HDX;
 2031                 } else
ifmr->ifm_active |= IFM_FDX;
 2034         } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) == IFM_FDX)
ifmr->ifm_active |= IFM_FDX;
 2036         else
ifmr->ifm_active |= IFM_HDX;
 2039 }
 2041 int
nge_ioctl(ifp, command, data)
 2043         struct ifnet            *ifp;
u_long                  command;
caddr_t                 data;
 2046 {
 2047         struct nge_softc        *sc = ifp->if_softc;
 2048         struct ifreq            *ifr = (struct ifreq *) data;
 2049         struct ifaddr           *ifa = (struct ifaddr *)data;
 2050         struct mii_data         *mii;
 2051         int                     s, error = 0;
s = splnet();
 2055         if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) {
splx(s);
 2057                 return (error);
 2058         }
 2060         switch(command) {
 2061         case SIOCSIFMTU:
 2062                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
error = EINVAL;
 2064                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
 2066                 break;
 2067         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
 2069                 switch (ifa->ifa_addr->sa_family) {
 2070 #ifdef INET
 2071                 case AF_INET:
nge_init(sc);
arp_ifinit(&sc->arpcom, ifa);
 2074                         break;
 2075 #endif /* INET */
 2076                 default:
nge_init(sc);
 2078                         break;
 2079                 }
 2080                 break;
 2081         case SIOCSIFFLAGS:
 2082                 if (ifp->if_flags & IFF_UP) {
 2083                         if (ifp->if_flags & IFF_RUNNING &&
ifp->if_flags & IFF_PROMISC &&
 2085                             !(sc->nge_if_flags & IFF_PROMISC)) {
NGE_SETBIT(sc, NGE_RXFILT_CTL,
NGE_RXFILTCTL_ALLPHYS|
NGE_RXFILTCTL_ALLMULTI);
 2089                         } else if (ifp->if_flags & IFF_RUNNING &&
 2090                             !(ifp->if_flags & IFF_PROMISC) &&
sc->nge_if_flags & IFF_PROMISC) {
NGE_CLRBIT(sc, NGE_RXFILT_CTL,
NGE_RXFILTCTL_ALLPHYS);
 2094                                 if (!(ifp->if_flags & IFF_ALLMULTI))
NGE_CLRBIT(sc, NGE_RXFILT_CTL,
NGE_RXFILTCTL_ALLMULTI);
 2097                         } else {
ifp->if_flags &= ~IFF_RUNNING;
nge_init(sc);
 2100                         }
 2101                 } else {
 2102                         if (ifp->if_flags & IFF_RUNNING)
nge_stop(sc);
 2104                 }
sc->nge_if_flags = ifp->if_flags;
error = 0;
 2107                 break;
 2108         case SIOCADDMULTI:
 2109         case SIOCDELMULTI:
error = (command == SIOCADDMULTI)
 2111                         ? ether_addmulti(ifr, &sc->arpcom)
 2112                         : ether_delmulti(ifr, &sc->arpcom);
 2114                 if (error == ENETRESET) {
 2115                         if (ifp->if_flags & IFF_RUNNING)
nge_setmulti(sc);
error = 0;
 2118                 }
 2119                 break;
 2120         case SIOCGIFMEDIA:
 2121         case SIOCSIFMEDIA:
 2122                 if (sc->nge_tbi) {
error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 
command);
 2125                 } else {
mii = &sc->nge_mii;
error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
command);
 2129                 }
 2130                 break;
 2131         default:
error = ENOTTY;
 2133                 break;
 2134         }
splx(s);
 2138         return(error);
 2139 }
 2141 void
nge_watchdog(ifp)
 2143         struct ifnet            *ifp;
 2144 {
 2145         struct nge_softc        *sc;
sc = ifp->if_softc;
ifp->if_oerrors++;
printf("%s: watchdog timeout\n", sc->sc_dv.dv_xname);
nge_stop(sc);
nge_reset(sc);
ifp->if_flags &= ~IFF_RUNNING;
nge_init(sc);
 2157         if (!IFQ_IS_EMPTY(&ifp->if_snd))
nge_start(ifp);
 2159 }
 2161 /*
 2162  * Stop the adapter and free any mbufs allocated to the
 2163  * RX and TX lists.
 2164  */
 2165 void
nge_stop(sc)
 2167         struct nge_softc        *sc;
 2168 {
 2169         int                     i;
 2170         struct ifnet            *ifp;
 2171         struct mii_data         *mii;
ifp = &sc->arpcom.ac_if;
ifp->if_timer = 0;
 2175         if (sc->nge_tbi) {
mii = NULL;
 2177         } else {
mii = &sc->nge_mii;
 2179         }
timeout_del(&sc->nge_timeout);
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
CSR_WRITE_4(sc, NGE_IER, 0);
CSR_WRITE_4(sc, NGE_IMR, 0);
NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
DELAY(1000);
CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
 2192         if (!sc->nge_tbi)
mii_down(mii);
sc->nge_link = 0;
 2197         /*
 2198          * Free data in the RX lists.
 2199          */
 2200         for (i = 0; i < NGE_RX_LIST_CNT; i++) {
 2201                 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
 2204                 }
 2205         }
bzero((char *)&sc->nge_ldata->nge_rx_list,
 2207                 sizeof(sc->nge_ldata->nge_rx_list));
 2209         /*
 2210          * Free the TX list buffers.
 2211          */
 2212         for (i = 0; i < NGE_TX_LIST_CNT; i++) {
 2213                 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
 2216                 }
 2217         }
bzero((char *)&sc->nge_ldata->nge_tx_list,
 2220                 sizeof(sc->nge_ldata->nge_tx_list));
 2221 }
 2223 /*
 2224  * Stop all chip I/O so that the kernel's probe routines don't
 2225  * get confused by errant DMAs when rebooting.
 2226  */
 2227 void
nge_shutdown(xsc)
 2229         void *xsc;
 2230 {
 2231         struct nge_softc *sc = (struct nge_softc *)xsc;
nge_reset(sc);
nge_stop(sc);
 2235 }
 2237 struct cfattach nge_ca = {
 2238         sizeof(struct nge_softc), nge_probe, nge_attach
 2239 };
 2241 struct cfdriver nge_cd = {
 2242         0, "nge", DV_IFNET
 2243 };