root/dev/ic/i82365.c

DEFINITIONS

1. pcic_ident_ok
2. pcic_vendor
3. pcic_attach
4. pcic_attach_sockets
5. pcic_attach_socket
6. pcic_create_event_thread
7. pcic_event_thread
8. pcic_event_process
9. pcic_init_socket
10. pcic_submatch
11. pcic_print
12. pcic_intr
13. pcic_poll_intr
14. pcic_intr_socket
15. pcic_queue_event
16. pcic_attach_card
17. pcic_detach_card
18. pcic_deactivate_card
19. pcic_power
20. pcic_chip_mem_alloc
21. pcic_chip_mem_free
22. pcic_chip_do_mem_map
23. pcic_chip_mem_map
24. pcic_chip_mem_unmap
25. pcic_chip_io_alloc
26. pcic_chip_io_free
27. pcic_chip_do_io_map
28. pcic_chip_io_map
29. pcic_chip_io_unmap
30. pcic_wait_ready
31. pcic_chip_socket_enable
32. pcic_chip_socket_disable
33. st_pcic_read
34. st_pcic_write

    1 /*      $OpenBSD: i82365.c,v 1.25 2005/11/23 11:39:37 mickey Exp $      */
    2 /*      $NetBSD: i82365.c,v 1.10 1998/06/09 07:36:55 thorpej Exp $      */
    4 /*
    5  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Marc Horowitz.
   18  * 4. The name of the author may not be used to endorse or promote products
   19  *    derived from this software without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   31  */
   33 #include <sys/types.h>
   34 #include <sys/param.h>
   35 #include <sys/systm.h>
   36 #include <sys/device.h>
   37 #include <sys/extent.h>
   38 #include <sys/kernel.h>
   39 #include <sys/malloc.h>
   40 #include <sys/kthread.h>
   42 #include <uvm/uvm_extern.h>
   44 #include <machine/bus.h>
   45 #include <machine/intr.h>
   47 #include <dev/pcmcia/pcmciareg.h>
   48 #include <dev/pcmcia/pcmciavar.h>
   50 #include <dev/ic/i82365reg.h>
   51 #include <dev/ic/i82365var.h>
   53 #ifdef PCICDEBUG
   54 #define DPRINTF(arg)    printf arg;
   55 #else
   56 #define DPRINTF(arg)
   57 #endif
   59 #define PCIC_VENDOR_UNKNOWN             0
   60 #define PCIC_VENDOR_I82365SLR0          1
   61 #define PCIC_VENDOR_I82365SLR1          2
   62 #define PCIC_VENDOR_I82365SLR2          3
   63 #define PCIC_VENDOR_CIRRUS_PD6710       4
   64 #define PCIC_VENDOR_CIRRUS_PD672X       5
   65 #define PCIC_VENDOR_VADEM_VG468         6
   66 #define PCIC_VENDOR_VADEM_VG469         7
   68 static char *pcic_vendor_to_string[] = {
   69         "Unknown",
   70         "Intel 82365SL rev 0",
   71         "Intel 82365SL rev 1",
   72         "Intel 82365SL rev 2",
   73         "Cirrus PD6710",
   74         "Cirrus PD672X",
   75         "Vadem VG468",
   76         "Vadem VG469",
   77 };
   79 /*
   80  * Individual drivers will allocate their own memory and io regions. Memory
   81  * regions must be a multiple of 4k, aligned on a 4k boundary.
   82  */
   84 #define PCIC_MEM_ALIGN  PCIC_MEM_PAGESIZE
   86 void    pcic_attach_socket(struct pcic_handle *);
   87 void    pcic_init_socket(struct pcic_handle *);
   89 int     pcic_submatch(struct device *, void *, void *);
   90 int     pcic_print(void *arg, const char *pnp);
   91 int     pcic_intr_socket(struct pcic_handle *);
   93 void    pcic_attach_card(struct pcic_handle *);
   94 void    pcic_detach_card(struct pcic_handle *, int);
   95 void    pcic_deactivate_card(struct pcic_handle *);
   97 void    pcic_chip_do_mem_map(struct pcic_handle *, int);
   98 void    pcic_chip_do_io_map(struct pcic_handle *, int);
  100 void    pcic_create_event_thread(void *);
  101 void    pcic_event_thread(void *);
  102 void    pcic_event_process(struct pcic_handle *, struct pcic_event *);
  103 void    pcic_queue_event(struct pcic_handle *, int);
  105 void    pcic_wait_ready(struct pcic_handle *);
u_int8_t st_pcic_read(struct pcic_handle *, int);
  108 void    st_pcic_write(struct pcic_handle *, int, int);
  110 struct cfdriver pcic_cd = {
NULL, "pcic", DV_DULL
  112 };
  114 int
pcic_ident_ok(ident)
  116         int ident;
  117 {
  118         /* this is very empirical and heuristic */
  120         if (ident == 0 || ident == 0xff || (ident & PCIC_IDENT_ZERO))
  121                 return (0);
  123         if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) {
  124 #ifdef DIAGNOSTIC
printf("pcic: does not support memory and I/O cards, "
  126                     "ignored (ident=%0x)\n", ident);
  127 #endif
  128                 return (0);
  129         }
  130         return (1);
  131 }
  133 int
pcic_vendor(h)
  135         struct pcic_handle *h;
  136 {
  137         int vendor, reg;
  139         /*
  140          * the chip_id of the cirrus toggles between 11 and 00 after a write.
  141          * weird.
  142          */
pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0);
reg = pcic_read(h, -1);
  147         if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) ==
PCIC_CIRRUS_CHIP_INFO_CHIP_ID) {
reg = pcic_read(h, -1);
  150                 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) {
  151                         if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS)
  152                                 return (PCIC_VENDOR_CIRRUS_PD672X);
  153                         else
  154                                 return (PCIC_VENDOR_CIRRUS_PD6710);
  155                 }
  156         }
reg = pcic_read(h, PCIC_IDENT);
  160         switch (reg) {
  161         case PCIC_IDENT_REV_I82365SLR0:
vendor = PCIC_VENDOR_I82365SLR0;
  163                 break;
  164         case PCIC_IDENT_REV_I82365SLR1:
vendor = PCIC_VENDOR_I82365SLR1;
  166                 break;
  167         case PCIC_IDENT_REV_I82365SLR2:
vendor = PCIC_VENDOR_I82365SLR2;
  169                 break;
  170         default:
vendor = PCIC_VENDOR_UNKNOWN;
  172                 break;
  173         }
pcic_write(h, 0x0e, -1);
pcic_write(h, 0x37, -1);
reg = pcic_read(h, PCIC_VG468_MISC);
reg |= PCIC_VG468_MISC_VADEMREV;
pcic_write(h, PCIC_VG468_MISC, reg);
reg = pcic_read(h, PCIC_IDENT);
  184         if (reg & PCIC_IDENT_VADEM_MASK) {
  185                 if ((reg & 7) >= 4)
vendor = PCIC_VENDOR_VADEM_VG469;
  187                 else
vendor = PCIC_VENDOR_VADEM_VG468;
reg = pcic_read(h, PCIC_VG468_MISC);
reg &= ~PCIC_VG468_MISC_VADEMREV;
pcic_write(h, PCIC_VG468_MISC, reg);
  193         }
  195         return (vendor);
  196 }
  198 void
pcic_attach(sc)
  200         struct pcic_softc *sc;
  201 {
  202         int vendor, count, i, reg;
  204         /* now check for each controller/socket */
  206         /*
  207          * this could be done with a loop, but it would violate the
  208          * abstraction
  209          */
count = 0;
DPRINTF(("pcic ident regs:"));
sc->handle[0].ph_parent = (struct device *)sc;
sc->handle[0].sock = C0SA;
  217         /* initialise pcic_read and pcic_write functions */
sc->handle[0].ph_read = st_pcic_read;
sc->handle[0].ph_write = st_pcic_write;
sc->handle[0].ph_bus_t = sc->iot;
sc->handle[0].ph_bus_h = sc->ioh;
  222         if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) {
sc->handle[0].flags = PCIC_FLAG_SOCKETP;
count++;
  225         } else {
sc->handle[0].flags = 0;
  227         }
sc->handle[0].laststate = PCIC_LASTSTATE_EMPTY;
DPRINTF((" 0x%02x", reg));
sc->handle[1].ph_parent = (struct device *)sc;
sc->handle[1].sock = C0SB;
  234         /* initialise pcic_read and pcic_write functions */
sc->handle[1].ph_read = st_pcic_read;
sc->handle[1].ph_write = st_pcic_write;
sc->handle[1].ph_bus_t = sc->iot;
sc->handle[1].ph_bus_h = sc->ioh;
  239         if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) {
sc->handle[1].flags = PCIC_FLAG_SOCKETP;
count++;
  242         } else {
sc->handle[1].flags = 0;
  244         }
sc->handle[1].laststate = PCIC_LASTSTATE_EMPTY;
DPRINTF((" 0x%02x", reg));
  249         /*
  250          * The CL-PD6729 has only one controller and always returns 0
  251          * if you try to read from the second one. Maybe pcic_ident_ok
  252          * shouldn't accept 0?
  253          */
sc->handle[2].ph_parent = (struct device *)sc;
sc->handle[2].sock = C1SA;
  256         /* initialise pcic_read and pcic_write functions */
sc->handle[2].ph_read = st_pcic_read;
sc->handle[2].ph_write = st_pcic_write;
sc->handle[2].ph_bus_t = sc->iot;
sc->handle[2].ph_bus_h = sc->ioh;
  261         if (pcic_vendor(&sc->handle[0]) != PCIC_VENDOR_CIRRUS_PD672X ||
pcic_read(&sc->handle[2], PCIC_IDENT) != 0) {
  263                 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2],
PCIC_IDENT))) {
sc->handle[2].flags = PCIC_FLAG_SOCKETP;
count++;
  267                 } else {
sc->handle[2].flags = 0;
  269                 }
sc->handle[2].laststate = PCIC_LASTSTATE_EMPTY;
DPRINTF((" 0x%02x", reg));
sc->handle[3].ph_parent = (struct device *)sc;
sc->handle[3].sock = C1SB;
  276                 /* initialise pcic_read and pcic_write functions */
sc->handle[3].ph_read = st_pcic_read;
sc->handle[3].ph_write = st_pcic_write;
sc->handle[3].ph_bus_t = sc->iot;
sc->handle[3].ph_bus_h = sc->ioh;
  281                 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3],
PCIC_IDENT))) {
sc->handle[3].flags = PCIC_FLAG_SOCKETP;
count++;
  285                 } else {
sc->handle[3].flags = 0;
  287                 }
sc->handle[3].laststate = PCIC_LASTSTATE_EMPTY;
DPRINTF((" 0x%02x\n", reg));
  291         } else {
sc->handle[2].flags = 0;
sc->handle[3].flags = 0;
  294         }
  296         if (count == 0)
  297                 return;
  299         /* establish the interrupt */
  301         /* XXX block interrupts? */
  303         for (i = 0; i < PCIC_NSLOTS; i++) {
  304                 /*
  305                  * this should work, but w/o it, setting tty flags hangs at
  306                  * boot time.
  307                  */
  308                 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) {
SIMPLEQ_INIT(&sc->handle[i].events);
pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0);
pcic_read(&sc->handle[i], PCIC_CSC);
  312                 }
  313         }
  315         for (i = 0; i < PCIC_NSLOTS; i += 2) {
  316                 if ((sc->handle[i+0].flags & PCIC_FLAG_SOCKETP) ||
  317                     (sc->handle[i+1].flags & PCIC_FLAG_SOCKETP)) {
vendor = pcic_vendor(&sc->handle[i]);
printf("%s controller %d: <%s> has socket",
sc->dev.dv_xname, i/2,
pcic_vendor_to_string[vendor]);
  324                         if ((sc->handle[i+0].flags & PCIC_FLAG_SOCKETP) &&
  325                             (sc->handle[i+1].flags & PCIC_FLAG_SOCKETP))
printf("s A and B\n");
  327                         else if (sc->handle[i+0].flags & PCIC_FLAG_SOCKETP)
printf(" A only\n");
  329                         else
printf(" B only\n");
  332                         if (sc->handle[i+0].flags & PCIC_FLAG_SOCKETP)
sc->handle[i+0].vendor = vendor;
  334                         if (sc->handle[i+1].flags & PCIC_FLAG_SOCKETP)
sc->handle[i+1].vendor = vendor;
  336                 }
  337         }
  338 }
  340 void
pcic_attach_sockets(sc)
  342         struct pcic_softc *sc;
  343 {
  344         int i;
  346         for (i = 0; i < PCIC_NSLOTS; i++)
  347                 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
pcic_attach_socket(&sc->handle[i]);
  349 }
  351 void
pcic_attach_socket(h)
  353         struct pcic_handle *h;
  354 {
  355         struct pcmciabus_attach_args paa;
  356         struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
  358         /* initialize the rest of the handle */
h->shutdown = 0;
h->memalloc = 0;
h->ioalloc = 0;
h->ih_irq = 0;
  365         /* now, config one pcmcia device per socket */
paa.paa_busname = "pcmcia";
paa.pct = (pcmcia_chipset_tag_t) sc->pct;
paa.pch = (pcmcia_chipset_handle_t) h;
paa.iobase = sc->iobase;
paa.iosize = sc->iosize;
h->pcmcia = config_found_sm(&sc->dev, &paa, pcic_print,
pcic_submatch);
  376         /* if there's actually a pcmcia device attached, initialize the slot */
  378         if (h->pcmcia)
pcic_init_socket(h);
  380         else
h->flags &= ~PCIC_FLAG_SOCKETP;
  382 }
  384 void
pcic_create_event_thread(arg)
  386         void *arg;
  387 {
  388         struct pcic_handle *h = arg;
  389         const char *cs;
  391         switch (h->sock) {
  392         case C0SA:
cs = "0,0";
  394                 break;
  395         case C0SB:
cs = "0,1";
  397                 break;
  398         case C1SA:
cs = "1,0";
  400                 break;
  401         case C1SB:
cs = "1,1";
  403                 break;
  404         default:
panic("pcic_create_event_thread: unknown pcic socket");
  406         }
  408         if (kthread_create(pcic_event_thread, h, &h->event_thread,
  409             "%s,%s", h->ph_parent->dv_xname, cs)) {
printf("%s: unable to create event thread for sock 0x%02x\n",
h->ph_parent->dv_xname, h->sock);
panic("pcic_create_event_thread");
  413         }
  414 }
  416 void
pcic_event_thread(arg)
  418         void *arg;
  419 {
  420         struct pcic_handle *h = arg;
  421         struct pcic_event *pe;
  422         int s;
  423         struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
  425         while (h->shutdown == 0) {
s = splhigh();
  427                 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) {
splx(s);
  429                         (void) tsleep(&h->events, PWAIT, "pcicev", 0);
  430                         continue;
  431                 } else {
splx(s);
  433                         /* sleep .25s to be enqueued chatterling interrupts */
  434                         (void) tsleep((caddr_t)pcic_event_thread, PWAIT,
  435                             "pcicss", hz/4);
  436                 }
pcic_event_process(h, pe);
  438         }
h->event_thread = NULL;
  442         /* In case parent is waiting for us to exit. */
wakeup(sc);
kthread_exit(0);
  446 }
  448 void
pcic_event_process(h, pe)
  450         struct pcic_handle *h;
  451         struct pcic_event *pe;
  452 {
  453         int s;
s = splhigh();
SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
splx(s);
  459         switch (pe->pe_type) {
  460         case PCIC_EVENT_INSERTION:
s = splhigh();
  462                 while (1) {
  463                         struct pcic_event *pe1, *pe2;
  465                         if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL)
  466                                 break;
  467                         if (pe1->pe_type != PCIC_EVENT_REMOVAL)
  468                                 break;
  469                         if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL)
  470                                 break;
  471                         if (pe2->pe_type == PCIC_EVENT_INSERTION) {
SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
free(pe1, M_TEMP);
SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
free(pe2, M_TEMP);
  476                         }
  477                 }
splx(s);
DPRINTF(("%s: insertion event\n", h->ph_parent->dv_xname));
pcic_attach_card(h);
  482                 break;
  484         case PCIC_EVENT_REMOVAL:
s = splhigh();
  486                 while (1) {
  487                         struct pcic_event *pe1, *pe2;
  489                         if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL)
  490                                 break;
  491                         if (pe1->pe_type != PCIC_EVENT_INSERTION)
  492                                 break;
  493                         if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL)
  494                                 break;
  495                         if (pe2->pe_type == PCIC_EVENT_REMOVAL) {
SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
free(pe1, M_TEMP);
SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
free(pe2, M_TEMP);
  500                         }
  501                 }
splx(s);
DPRINTF(("%s: removal event\n", h->ph_parent->dv_xname));
pcic_detach_card(h, DETACH_FORCE);
  506                 break;
  508         default:
panic("pcic_event_thread: unknown event %d", pe->pe_type);
  510         }
free(pe, M_TEMP);
  512 }
  514 void
pcic_init_socket(h)
  516         struct pcic_handle *h;
  517 {
  518         int reg;
  519         struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
  521         /*
  522          * queue creation of a kernel thread to handle insert/removal events.
  523          */
  524 #ifdef DIAGNOSTIC
  525         if (h->event_thread != NULL)
panic("pcic_attach_socket: event thread");
  527 #endif
kthread_create_deferred(pcic_create_event_thread, h);
  530         /* set up the card to interrupt on card detect */
pcic_write(h, PCIC_CSC_INTR, (sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) |
PCIC_CSC_INTR_CD_ENABLE);
pcic_write(h, PCIC_INTR, 0);
pcic_read(h, PCIC_CSC);
  537         /* unsleep the cirrus controller */
  539         if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) ||
  540             (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) {
reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2);
  542                 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) {
DPRINTF(("%s: socket %02x was suspended\n",
h->ph_parent->dv_xname, h->sock));
reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND;
pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg);
  547                 }
  548         }
  549         /* if there's a card there, then attach it. */
reg = pcic_read(h, PCIC_IF_STATUS);
  553         if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) ==
PCIC_IF_STATUS_CARDDETECT_PRESENT) {
pcic_attach_card(h);
h->laststate = PCIC_LASTSTATE_PRESENT;
  557         } else
h->laststate = PCIC_LASTSTATE_EMPTY;
  559 }
  561 int
pcic_submatch(parent, match, aux)
  563         struct device *parent;
  564         void *match, *aux;
  565 {
  566         struct cfdata *cf = match;
  567         struct pcmciabus_attach_args *paa = aux;
  568         struct pcic_handle *h = (struct pcic_handle *) paa->pch;
  570         switch (h->sock) {
  571         case C0SA:
  572                 if (cf->cf_loc[0 /* PCICCF_CONTROLLER */] !=
  573                     -1 /* PCICCF_CONTROLLER_DEFAULT */ &&
cf->cf_loc[0 /* PCICCF_CONTROLLER */] != 0)
  575                         return 0;
  576                 if (cf->cf_loc[1 /* PCICCF_SOCKET */] !=
  577                     -1 /* PCICCF_SOCKET_DEFAULT */ &&
cf->cf_loc[1 /* PCICCF_SOCKET */] != 0)
  579                         return 0;
  581                 break;
  582         case C0SB:
  583                 if (cf->cf_loc[0 /* PCICCF_CONTROLLER */] !=
  584                     -1 /* PCICCF_CONTROLLER_DEFAULT */ &&
cf->cf_loc[0 /* PCICCF_CONTROLLER */] != 0)
  586                         return 0;
  587                 if (cf->cf_loc[1 /* PCICCF_SOCKET */] !=
  588                     -1 /* PCICCF_SOCKET_DEFAULT */ &&
cf->cf_loc[1 /* PCICCF_SOCKET */] != 1)
  590                         return 0;
  592                 break;
  593         case C1SA:
  594                 if (cf->cf_loc[0 /* PCICCF_CONTROLLER */] !=
  595                     -1 /* PCICCF_CONTROLLER_DEFAULT */ &&
cf->cf_loc[0 /* PCICCF_CONTROLLER */] != 1)
  597                         return 0;
  598                 if (cf->cf_loc[1 /* PCICCF_SOCKET */] !=
  599                     -1 /* PCICCF_SOCKET_DEFAULT */ &&
cf->cf_loc[1 /* PCICCF_SOCKET */] != 0)
  601                         return 0;
  603                 break;
  604         case C1SB:
  605                 if (cf->cf_loc[0 /* PCICCF_CONTROLLER */] !=
  606                     -1 /* PCICCF_CONTROLLER_DEFAULT */ &&
cf->cf_loc[0 /* PCICCF_CONTROLLER */] != 1)
  608                         return 0;
  609                 if (cf->cf_loc[1 /* PCICCF_SOCKET */] !=
  610                     -1 /* PCICCF_SOCKET_DEFAULT */ &&
cf->cf_loc[1 /* PCICCF_SOCKET */] != 1)
  612                         return 0;
  614                 break;
  615         default:
panic("unknown pcic socket");
  617         }
  619         return ((*cf->cf_attach->ca_match)(parent, cf, aux));
  620 }
  622 int
pcic_print(arg, pnp)
  624         void *arg;
  625         const char *pnp;
  626 {
  627         struct pcmciabus_attach_args *paa = arg;
  628         struct pcic_handle *h = (struct pcic_handle *) paa->pch;
  630         /* Only "pcmcia"s can attach to "pcic"s... easy. */
  631         if (pnp)
printf("pcmcia at %s", pnp);
  634         switch (h->sock) {
  635         case C0SA:
printf(" controller 0 socket 0");
  637                 break;
  638         case C0SB:
printf(" controller 0 socket 1");
  640                 break;
  641         case C1SA:
printf(" controller 1 socket 0");
  643                 break;
  644         case C1SB:
printf(" controller 1 socket 1");
  646                 break;
  647         default:
panic("unknown pcic socket");
  649         }
  651         return (UNCONF);
  652 }
  654 int
pcic_intr(arg)
  656         void *arg;
  657 {
  658         struct pcic_softc *sc = arg;
  659         int i, ret = 0;
DPRINTF(("%s: intr\n", sc->dev.dv_xname));
  663         for (i = 0; i < PCIC_NSLOTS; i++)
  664                 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
ret += pcic_intr_socket(&sc->handle[i]);
  667         return (ret ? 1 : 0);
  668 }
  670 void
pcic_poll_intr(arg)
  672         void *arg;
  673 {
  674         struct pcic_softc *sc = arg;
  675         int i, s;
  677         /*
  678          * Since we're polling, we aren't in interrupt context, so block any
  679          * actual interrupts coming from the pcic.
  680          */
s = spltty();
  683         for (i = 0; i < PCIC_NSLOTS; i++)
  684                 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
pcic_intr_socket(&sc->handle[i]);
timeout_add(&sc->poll_timeout, hz / 2);
splx(s);
  690 }
  692 int
pcic_intr_socket(h)
  694         struct pcic_handle *h;
  695 {
  696         int cscreg;
cscreg = pcic_read(h, PCIC_CSC);
cscreg &= (PCIC_CSC_GPI |
PCIC_CSC_CD |
PCIC_CSC_READY |
PCIC_CSC_BATTWARN |
PCIC_CSC_BATTDEAD);
  706         if (cscreg & PCIC_CSC_GPI) {
DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock));
  708         }
  709         if (cscreg & PCIC_CSC_CD) {
  710                 int statreg;
statreg = pcic_read(h, PCIC_IF_STATUS);
DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock,
statreg));
  717                 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) ==
PCIC_IF_STATUS_CARDDETECT_PRESENT) {
  719                         if (h->laststate != PCIC_LASTSTATE_PRESENT) {
DPRINTF(("%s: enqueing INSERTION event\n",
h->ph_parent->dv_xname));
pcic_queue_event(h, PCIC_EVENT_INSERTION);
  723                         }
h->laststate = PCIC_LASTSTATE_PRESENT;
  725                 } else {
  726                         if (h->laststate == PCIC_LASTSTATE_PRESENT) {
  727                                 /* Deactivate the card now. */
DPRINTF(("%s: deactivating card\n",
h->ph_parent->dv_xname));
pcic_deactivate_card(h);
DPRINTF(("%s: enqueing REMOVAL event\n",
h->ph_parent->dv_xname));
pcic_queue_event(h, PCIC_EVENT_REMOVAL);
  735                         }
h->laststate =
  737                             ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 0)
  738                             ? PCIC_LASTSTATE_EMPTY : PCIC_LASTSTATE_HALF;
  739                 }
  740         }
  741         if (cscreg & PCIC_CSC_READY) {
DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock));
  743                 /* shouldn't happen */
  744         }
  745         if (cscreg & PCIC_CSC_BATTWARN) {
DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname,
h->sock));
  748         }
  749         if (cscreg & PCIC_CSC_BATTDEAD) {
DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname,
h->sock));
  752         }
  753         return (cscreg ? 1 : 0);
  754 }
  756 void
pcic_queue_event(h, event)
  758         struct pcic_handle *h;
  759         int event;
  760 {
  761         struct pcic_event *pe;
  762         int s;
pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT);
  765         if (pe == NULL)
panic("pcic_queue_event: can't allocate event");
pe->pe_type = event;
s = splhigh();
SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q);
splx(s);
wakeup(&h->events);
  773 }
  775 void
pcic_attach_card(h)
  777         struct pcic_handle *h;
  778 {
  779         if (h->flags & PCIC_FLAG_CARDP)
panic("pcic_attach_card: already attached");
  782         /* call the MI attach function */
pcmcia_card_attach(h->pcmcia);
h->flags |= PCIC_FLAG_CARDP;
  786 }
  788 void
pcic_detach_card(h, flags)
  790         struct pcic_handle *h;
  791         int flags;              /* DETACH_* */
  792 {
  794         if (h->flags & PCIC_FLAG_CARDP) {
h->flags &= ~PCIC_FLAG_CARDP;
  797                 /* call the MI detach function */
pcmcia_card_detach(h->pcmcia, flags);
  799         } else {
DPRINTF(("pcic_detach_card: already detached"));
  801         }
  802 }
  804 void
pcic_deactivate_card(h)
  806         struct pcic_handle *h;
  807 {
  808         struct device *dev = (struct device *)h->pcmcia;
  810         /*
  811          * At suspend, apm deactivates any connected cards. If we've woken up
  812          * to find a previously-connected device missing, and we're detaching
  813          * it, we don't want to deactivate it again.
  814          */
  815         if (dev->dv_flags & DVF_ACTIVE)
pcmcia_card_deactivate(h->pcmcia);
  818         /* power down the socket */
pcic_write(h, PCIC_PWRCTL, 0);
  821         /* reset the socket */
pcic_write(h, PCIC_INTR, 0);
  823 }
  825 /*
  826  * The pcic_power() function must execute BEFORE the pcmcia_power() hooks.
  827  * During suspend, a card may have been ejected. If so, we must detach it
  828  * completely before pcmcia_power() tries to activate it. Attempting to
  829  * activate a card that isn't there is bad news.
  830  */
  831 void
pcic_power(why, arg)
  833         int why;
  834         void *arg;
  835 {
  836         struct pcic_handle *h = (struct pcic_handle *)arg;
  837         struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent;
  838         struct pcic_event *pe;
  840         if (why != PWR_RESUME) {
  841                 if (timeout_pending(&sc->poll_timeout))
timeout_del(&sc->poll_timeout);
  843         }
  844         else {
pcic_intr_socket(h);
  847                 while ((pe = SIMPLEQ_FIRST(&h->events)))
pcic_event_process(h, pe);
timeout_add(&sc->poll_timeout, hz / 2);
  851         }
  852 }
  854 int 
pcic_chip_mem_alloc(pch, size, pcmhp)
pcmcia_chipset_handle_t pch;
bus_size_t size;
  858         struct pcmcia_mem_handle *pcmhp;
  859 {
  860         struct pcic_handle *h = (struct pcic_handle *) pch;
bus_space_handle_t memh;
bus_addr_t addr;
bus_size_t sizepg;
  864         int i, mask, mhandle;
  865         struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
  867         /* out of sc->memh, allocate as many pages as necessary */
  869         /* convert size to PCIC pages */
sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN;
  871         if (sizepg > PCIC_MAX_MEM_PAGES)
  872                 return (1);
mask = (1 << sizepg) - 1;
addr = 0;               /* XXX gcc -Wuninitialized */
mhandle = 0;            /* XXX gcc -Wuninitialized */
  879         for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) {
  880                 if ((sc->subregionmask & (mask << i)) == (mask << i)) {
  881                         if (bus_space_subregion(sc->memt, sc->memh,
i * PCIC_MEM_PAGESIZE,
sizepg * PCIC_MEM_PAGESIZE, &memh))
  884                                 return (1);
mhandle = mask << i;
addr = sc->membase + (i * PCIC_MEM_PAGESIZE);
sc->subregionmask &= ~(mhandle);
pcmhp->memt = sc->memt;
pcmhp->memh = memh;
pcmhp->addr = addr;
pcmhp->size = size;
pcmhp->mhandle = mhandle;
pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE;
DPRINTF(("pcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n",
  896                             (u_long) addr, (u_long) size));
  898                         return (0);
  899                 }
  900         }
  902         return (1);
  903 }
  905 void 
pcic_chip_mem_free(pch, pcmhp)
pcmcia_chipset_handle_t pch;
  908         struct pcmcia_mem_handle *pcmhp;
  909 {
  910         struct pcic_handle *h = (struct pcic_handle *) pch;
  911         struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
sc->subregionmask |= pcmhp->mhandle;
  914 }
  916 static struct mem_map_index_st {
  917         int     sysmem_start_lsb;
  918         int     sysmem_start_msb;
  919         int     sysmem_stop_lsb;
  920         int     sysmem_stop_msb;
  921         int     cardmem_lsb;
  922         int     cardmem_msb;
  923         int     memenable;
  924 } mem_map_index[] = {
  925         {
PCIC_SYSMEM_ADDR0_START_LSB,
PCIC_SYSMEM_ADDR0_START_MSB,
PCIC_SYSMEM_ADDR0_STOP_LSB,
PCIC_SYSMEM_ADDR0_STOP_MSB,
PCIC_CARDMEM_ADDR0_LSB,
PCIC_CARDMEM_ADDR0_MSB,
PCIC_ADDRWIN_ENABLE_MEM0,
  933         },
  934         {
PCIC_SYSMEM_ADDR1_START_LSB,
PCIC_SYSMEM_ADDR1_START_MSB,
PCIC_SYSMEM_ADDR1_STOP_LSB,
PCIC_SYSMEM_ADDR1_STOP_MSB,
PCIC_CARDMEM_ADDR1_LSB,
PCIC_CARDMEM_ADDR1_MSB,
PCIC_ADDRWIN_ENABLE_MEM1,
  942         },
  943         {
PCIC_SYSMEM_ADDR2_START_LSB,
PCIC_SYSMEM_ADDR2_START_MSB,
PCIC_SYSMEM_ADDR2_STOP_LSB,
PCIC_SYSMEM_ADDR2_STOP_MSB,
PCIC_CARDMEM_ADDR2_LSB,
PCIC_CARDMEM_ADDR2_MSB,
PCIC_ADDRWIN_ENABLE_MEM2,
  951         },
  952         {
PCIC_SYSMEM_ADDR3_START_LSB,
PCIC_SYSMEM_ADDR3_START_MSB,
PCIC_SYSMEM_ADDR3_STOP_LSB,
PCIC_SYSMEM_ADDR3_STOP_MSB,
PCIC_CARDMEM_ADDR3_LSB,
PCIC_CARDMEM_ADDR3_MSB,
PCIC_ADDRWIN_ENABLE_MEM3,
  960         },
  961         {
PCIC_SYSMEM_ADDR4_START_LSB,
PCIC_SYSMEM_ADDR4_START_MSB,
PCIC_SYSMEM_ADDR4_STOP_LSB,
PCIC_SYSMEM_ADDR4_STOP_MSB,
PCIC_CARDMEM_ADDR4_LSB,
PCIC_CARDMEM_ADDR4_MSB,
PCIC_ADDRWIN_ENABLE_MEM4,
  969         },
  970 };
  972 void 
pcic_chip_do_mem_map(h, win)
  974         struct pcic_handle *h;
  975         int win;
  976 {
  977         int reg;
  978         int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK;
  979         int mem8 =
  980             (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8
  981             || (kind == PCMCIA_MEM_ATTR);
pcic_write(h, mem_map_index[win].sysmem_start_lsb,
  984             (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff);
pcic_write(h, mem_map_index[win].sysmem_start_msb,
  986             ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) &
PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) |
  988             (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT));
pcic_write(h, mem_map_index[win].sysmem_stop_lsb,
  991             ((h->mem[win].addr + h->mem[win].size) >>
PCIC_SYSMEM_ADDRX_SHIFT) & 0xff);
pcic_write(h, mem_map_index[win].sysmem_stop_msb,
  994             (((h->mem[win].addr + h->mem[win].size) >>
  995             (PCIC_SYSMEM_ADDRX_SHIFT + 8)) &
PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) |
PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2);
pcic_write(h, mem_map_index[win].cardmem_lsb,
 1000             (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff);
pcic_write(h, mem_map_index[win].cardmem_msb,
 1002             ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) &
PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) |
 1004             ((kind == PCMCIA_MEM_ATTR) ?
PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0));
reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16);
pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
 1011 #ifdef PCICDEBUG
 1012         {
 1013                 int r1, r2, r3, r4, r5, r6;
r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb);
r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb);
r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb);
r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb);
r5 = pcic_read(h, mem_map_index[win].cardmem_msb);
r6 = pcic_read(h, mem_map_index[win].cardmem_lsb);
DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x "
 1023                     "%02x%02x\n", win, r1, r2, r3, r4, r5, r6));
 1024         }
 1025 #endif
 1026 }
 1028 int 
pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp)
pcmcia_chipset_handle_t pch;
 1031         int kind;
bus_addr_t card_addr;
bus_size_t size;
 1034         struct pcmcia_mem_handle *pcmhp;
bus_size_t *offsetp;
 1036         int *windowp;
 1037 {
 1038         struct pcic_handle *h = (struct pcic_handle *) pch;
bus_addr_t busaddr;
 1040         long card_offset;
 1041         int i, win;
 1042         struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
win = -1;
 1045         for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0]));
i++) {
 1047                 if ((h->memalloc & (1 << i)) == 0) {
win = i;
h->memalloc |= (1 << i);
 1050                         break;
 1051                 }
 1052         }
 1054         if (win == -1)
 1055                 return (1);
 1057         *windowp = win;
 1059         /* XXX this is pretty gross */
 1061         if (sc->memt != pcmhp->memt)
panic("pcic_chip_mem_map memt is bogus");
busaddr = pcmhp->addr;
 1066         /*
 1067          * Compute the address offset to the pcmcia address space for the
 1068          * pcic.  This is intentionally signed.  The masks and shifts below
 1069          * will cause TRT to happen in the pcic registers.  Deal with making
 1070          * sure the address is aligned, and return the alignment offset.
 1071          */
 1073         *offsetp = card_addr % PCIC_MEM_ALIGN;
card_addr -= *offsetp;
DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr "
 1077             "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size,
 1078             (u_long) card_addr));
 1080         /*
 1081          * include the offset in the size, and decrement size by one, since
 1082          * the hw wants start/stop
 1083          */
size += *offsetp - 1;
card_offset = (((long) card_addr) - ((long) busaddr));
h->mem[win].addr = busaddr;
h->mem[win].size = size;
h->mem[win].offset = card_offset;
h->mem[win].kind = kind;
pcic_chip_do_mem_map(h, win);
 1095         return (0);
 1096 }
 1098 void 
pcic_chip_mem_unmap(pch, window)
pcmcia_chipset_handle_t pch;
 1101         int window;
 1102 {
 1103         struct pcic_handle *h = (struct pcic_handle *) pch;
 1104         int reg;
 1106         if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0])))
panic("pcic_chip_mem_unmap: window out of range");
reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
reg &= ~mem_map_index[window].memenable;
pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
h->memalloc &= ~(1 << window);
 1114 }
 1116 int 
pcic_chip_io_alloc(pch, start, size, align, pcihp)
pcmcia_chipset_handle_t pch;
bus_addr_t start;
bus_size_t size;
bus_size_t align;
 1122         struct pcmcia_io_handle *pcihp;
 1123 {
 1124         struct pcic_handle *h = (struct pcic_handle *) pch;
bus_space_tag_t iot;
bus_space_handle_t ioh;
bus_addr_t ioaddr, beg, fin;
 1128         int flags = 0;
 1129         struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
 1130         struct pcic_ranges *range;
 1132         /*
 1133          * Allocate some arbitrary I/O space.
 1134          */
iot = sc->iot;
 1138         if (start) {
ioaddr = start;
 1140                 if (bus_space_map(iot, start, size, 0, &ioh))
 1141                         return (1);
DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n",
 1143                     (u_long)ioaddr, (u_long)size));
 1144         } else if (sc->ranges) {
flags |= PCMCIA_IO_ALLOCATED;
 1147                 /*
 1148                  * In this case, we know the "size" and "align" that
 1149                  * we want.  So we need to start walking down
 1150                  * sc->ranges, searching for a similar space that
 1151                  * is (1) large enough for the size and alignment
 1152                  * (2) then we need to try to allocate
 1153                  * (3) if it fails to allocate, we try next range.
 1154                  *
 1155                  * We must also check that the start/size of each
 1156                  * allocation we are about to do is within the bounds
 1157                  * of "sc->iobase" and "sc->iosize".
 1158                  * (Some pcmcia controllers handle a 12 bits of addressing,
 1159                  * but we want to use the same range structure)
 1160                  */
 1161                 for (range = sc->ranges; range->start; range++) {
 1162                         /* Potentially trim the range because of bounds. */
beg = max(range->start, sc->iobase);
fin = min(range->start + range->len,
sc->iobase + sc->iosize);
 1167                         /* Short-circuit easy cases. */
 1168                         if (fin < beg || fin - beg < size)
 1169                                 continue;
 1171                         /*
 1172                          * This call magically fulfills our alignment
 1173                          * requirements.
 1174                          */
DPRINTF(("pcic_chip_io_alloc beg-fin %lx-%lx\n",
 1176                             (u_long)beg, (u_long)fin));
 1177                         if (bus_space_alloc(iot, beg, fin, size, align, 0, 0,
 1178                             &ioaddr, &ioh) == 0)
 1179                                 break;
 1180                 }
 1181                 if (range->start == 0)
 1182                         return (1);
DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n",
 1184                     (u_long)ioaddr, (u_long)size));
 1186         } else {
flags |= PCMCIA_IO_ALLOCATED;
 1188                 if (bus_space_alloc(iot, sc->iobase,
sc->iobase + sc->iosize, size, align, 0, 0,
 1190                     &ioaddr, &ioh))
 1191                         return (1);
DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n",
 1193                     (u_long)ioaddr, (u_long)size));
 1194         }
pcihp->iot = iot;
pcihp->ioh = ioh;
pcihp->addr = ioaddr;
pcihp->size = size;
pcihp->flags = flags;
 1202         return (0);
 1203 }
 1205 void 
pcic_chip_io_free(pch, pcihp)
pcmcia_chipset_handle_t pch;
 1208         struct pcmcia_io_handle *pcihp;
 1209 {
bus_space_tag_t iot = pcihp->iot;
bus_space_handle_t ioh = pcihp->ioh;
bus_size_t size = pcihp->size;
 1214         if (pcihp->flags & PCMCIA_IO_ALLOCATED)
bus_space_free(iot, ioh, size);
 1216         else
bus_space_unmap(iot, ioh, size);
 1218 }
 1221 static struct io_map_index_st {
 1222         int     start_lsb;
 1223         int     start_msb;
 1224         int     stop_lsb;
 1225         int     stop_msb;
 1226         int     ioenable;
 1227         int     ioctlmask;
 1228         int     ioctlbits[3];           /* indexed by PCMCIA_WIDTH_* */
 1229 }               io_map_index[] = {
 1230         {
PCIC_IOADDR0_START_LSB,
PCIC_IOADDR0_START_MSB,
PCIC_IOADDR0_STOP_LSB,
PCIC_IOADDR0_STOP_MSB,
PCIC_ADDRWIN_ENABLE_IO0,
PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT |
PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK,
 1238                 {
PCIC_IOCTL_IO0_IOCS16SRC_CARD,
PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
PCIC_IOCTL_IO0_DATASIZE_8BIT,
PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
PCIC_IOCTL_IO0_DATASIZE_16BIT,
 1244                 },
 1245         },
 1246         {
PCIC_IOADDR1_START_LSB,
PCIC_IOADDR1_START_MSB,
PCIC_IOADDR1_STOP_LSB,
PCIC_IOADDR1_STOP_MSB,
PCIC_ADDRWIN_ENABLE_IO1,
PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT |
PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK,
 1254                 {
PCIC_IOCTL_IO1_IOCS16SRC_CARD,
PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE |
PCIC_IOCTL_IO1_DATASIZE_8BIT,
PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE |
PCIC_IOCTL_IO1_DATASIZE_16BIT,
 1260                 },
 1261         },
 1262 };
 1264 void 
pcic_chip_do_io_map(h, win)
 1266         struct pcic_handle *h;
 1267         int win;
 1268 {
 1269         int reg;
DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n",
win, (long) h->io[win].addr, (long) h->io[win].size,
h->io[win].width * 8));
pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff);
pcic_write(h, io_map_index[win].start_msb,
 1277             (h->io[win].addr >> 8) & 0xff);
pcic_write(h, io_map_index[win].stop_lsb,
 1280             (h->io[win].addr + h->io[win].size - 1) & 0xff);
pcic_write(h, io_map_index[win].stop_msb,
 1282             ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff);
reg = pcic_read(h, PCIC_IOCTL);
reg &= ~io_map_index[win].ioctlmask;
reg |= io_map_index[win].ioctlbits[h->io[win].width];
pcic_write(h, PCIC_IOCTL, reg);
reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
reg |= io_map_index[win].ioenable;
pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
 1292 }
 1294 int 
pcic_chip_io_map(pch, width, offset, size, pcihp, windowp)
pcmcia_chipset_handle_t pch;
 1297         int width;
bus_addr_t offset;
bus_size_t size;
 1300         struct pcmcia_io_handle *pcihp;
 1301         int *windowp;
 1302 {
 1303         struct pcic_handle *h = (struct pcic_handle *) pch;
bus_addr_t ioaddr = pcihp->addr + offset;
 1305         int i, win;
 1306 #ifdef PCICDEBUG
 1307         static char *width_names[] = { "auto", "io8", "io16" };
 1308 #endif
 1309         struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent);
 1311         /* XXX Sanity check offset/size. */
win = -1;
 1314         for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) {
 1315                 if ((h->ioalloc & (1 << i)) == 0) {
win = i;
h->ioalloc |= (1 << i);
 1318                         break;
 1319                 }
 1320         }
 1322         if (win == -1)
 1323                 return (1);
 1325         *windowp = win;
 1327         /* XXX this is pretty gross */
 1329         if (sc->iot != pcihp->iot)
panic("pcic_chip_io_map iot is bogus");
DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n",
win, width_names[width], (u_long) ioaddr, (u_long) size));
h->io[win].addr = ioaddr;
h->io[win].size = size;
h->io[win].width = width;
pcic_chip_do_io_map(h, win);
 1341         return (0);
 1342 }
 1344 void 
pcic_chip_io_unmap(pch, window)
pcmcia_chipset_handle_t pch;
 1347         int window;
 1348 {
 1349         struct pcic_handle *h = (struct pcic_handle *) pch;
 1350         int reg;
 1352         if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0])))
panic("pcic_chip_io_unmap: window out of range");
reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
reg &= ~io_map_index[window].ioenable;
pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
h->ioalloc &= ~(1 << window);
 1360 }
 1362 void
pcic_wait_ready(h)
 1364         struct pcic_handle *h;
 1365 {
 1366         int i;
 1368         for (i = 0; i < 10000; i++) {
 1369                 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY)
 1370                         return;
delay(500);
 1372 #ifdef PCICDEBUG
 1373                         if ((i>5000) && (i%100 == 99))
printf(".");
 1375 #endif
 1376         }
 1378 #ifdef DIAGNOSTIC
printf("pcic_wait_ready: ready never happened, status = %02x\n",
pcic_read(h, PCIC_IF_STATUS));
 1381 #endif
 1382 }
 1384 void
pcic_chip_socket_enable(pch)
pcmcia_chipset_handle_t pch;
 1387 {
 1388         struct pcic_handle *h = (struct pcic_handle *) pch;
 1389         int cardtype, reg, win;
 1391         /* this bit is mostly stolen from pcic_attach_card */
 1393         /* power down the socket to reset it, clear the card reset pin */
pcic_write(h, PCIC_PWRCTL, 0);
 1397         /* 
 1398          * wait 300ms until power fails (Tpf).  Then, wait 100ms since
 1399          * we are changing Vcc (Toff).
 1400          */
delay((300 + 100) * 1000);
 1403         if (h->vendor == PCIC_VENDOR_VADEM_VG469) {
reg = pcic_read(h, PCIC_VG469_VSELECT);
reg &= ~PCIC_VG469_VSELECT_VCC;
pcic_write(h, PCIC_VG469_VSELECT, reg);
 1407         }
 1409         /* power up the socket */
pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV
 1412                            | PCIC_PWRCTL_PWR_ENABLE);
 1414         /*
 1415          * wait 100ms until power raise (Tpr) and 20ms to become
 1416          * stable (Tsu(Vcc)).
 1417          *
 1418          * some machines require some more time to be settled
 1419          * (another 200ms is added here).
 1420          */
delay((100 + 20 + 200) * 1000);
pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV |
PCIC_PWRCTL_OE | PCIC_PWRCTL_PWR_ENABLE);
pcic_write(h, PCIC_INTR, 0);
 1427         /*
 1428          * hold RESET at least 10us.
 1429          */
delay(10);
 1432         /* clear the reset flag */
pcic_write(h, PCIC_INTR, PCIC_INTR_RESET);
 1436         /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */
delay(20000);
 1440         /* wait for the chip to finish initializing */
 1442 #ifdef DIAGNOSTIC
reg = pcic_read(h, PCIC_IF_STATUS);
 1444         if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) {
printf("pcic_chip_socket_enable: status %x\n", reg);
 1446         }
 1447 #endif
pcic_wait_ready(h);
 1451         /* zero out the address windows */
pcic_write(h, PCIC_ADDRWIN_ENABLE, 0);
 1455         /* set the card type */
cardtype = pcmcia_card_gettype(h->pcmcia);
reg = pcic_read(h, PCIC_INTR);
reg &= ~PCIC_INTR_CARDTYPE_MASK;
reg |= ((cardtype == PCMCIA_IFTYPE_IO) ?
PCIC_INTR_CARDTYPE_IO :
PCIC_INTR_CARDTYPE_MEM);
reg |= h->ih_irq;
pcic_write(h, PCIC_INTR, reg);
DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n",
h->ph_parent->dv_xname, h->sock,
 1469             ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg));
 1471         /* reinstall all the memory and io mappings */
 1473         for (win = 0; win < PCIC_MEM_WINS; win++)
 1474                 if (h->memalloc & (1 << win))
pcic_chip_do_mem_map(h, win);
 1477         for (win = 0; win < PCIC_IO_WINS; win++)
 1478                 if (h->ioalloc & (1 << win))
pcic_chip_do_io_map(h, win);
 1480 }
 1482 void
pcic_chip_socket_disable(pch)
pcmcia_chipset_handle_t pch;
 1485 {
 1486         struct pcic_handle *h = (struct pcic_handle *) pch;
DPRINTF(("pcic_chip_socket_disable\n"));
 1490         /* power down the socket */
pcic_write(h, PCIC_PWRCTL, 0);
 1494         /*
 1495          * wait 300ms until power fails (Tpf).
 1496          */
delay(300 * 1000);
 1498 }
u_int8_t
st_pcic_read(h, idx)
 1502         struct pcic_handle *h;
 1503         int idx;
 1504 {
 1505         if (idx != -1)
bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX,
h->sock + idx);
 1508         return bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA);
 1509 }
 1511 void
st_pcic_write(h, idx, data)
 1513         struct pcic_handle *h;
 1514         int idx;
 1515         int data;
 1516 {
 1517         if (idx != -1)
bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX,
h->sock + idx);
 1520         if (data != -1)
bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA,
data);
 1523 }