root/dev/ic/hme.c

DEFINITIONS

1. hme_config
2. hme_tick
3. hme_reset
4. hme_stop
5. hme_meminit
6. hme_init
7. hme_start
8. hme_tint
9. hme_rxcksum
10. hme_rint
11. hme_eint
12. hme_intr
13. hme_watchdog
14. hme_mifinit
15. hme_mii_readreg
16. hme_mii_writereg
17. hme_mii_statchg
18. hme_mediachange
19. hme_mediastatus
20. hme_ioctl
21. hme_shutdown
22. hme_setladrf
23. hme_encap
24. hme_newbuf

    1 /*      $OpenBSD: hme.c,v 1.46 2006/12/21 22:13:36 jason Exp $  */
    2 /*      $NetBSD: hme.c,v 1.21 2001/07/07 15:59:37 thorpej Exp $ */
    4 /*-
    5  * Copyright (c) 1999 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Paul Kranenburg.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *        This product includes software developed by the NetBSD
   22  *        Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   40 /*
   41  * HME Ethernet module driver.
   42  */
   44 #include "bpfilter.h"
   45 #include "vlan.h"
   47 #undef HMEDEBUG
   49 #include <sys/param.h>
   50 #include <sys/systm.h>
   51 #include <sys/kernel.h>
   52 #include <sys/mbuf.h> 
   53 #include <sys/syslog.h>
   54 #include <sys/socket.h>
   55 #include <sys/device.h>
   56 #include <sys/malloc.h>
   57 #include <sys/ioctl.h>
   58 #include <sys/errno.h>
   60 #include <net/if.h>
   61 #include <net/if_dl.h>
   62 #include <net/if_media.h>
   64 #ifdef INET
   65 #include <netinet/in.h>
   66 #include <netinet/in_systm.h>
   67 #include <netinet/in_var.h>
   68 #include <netinet/ip.h>
   69 #include <netinet/if_ether.h>
   70 #include <netinet/tcp.h>
   71 #include <netinet/udp.h>
   72 #endif
   74 #if NBPFILTER > 0
   75 #include <net/bpf.h>
   76 #endif
   78 #include <dev/mii/mii.h>
   79 #include <dev/mii/miivar.h>
   81 #include <machine/bus.h>
   83 #include <dev/ic/hmereg.h>
   84 #include <dev/ic/hmevar.h>
   86 struct cfdriver hme_cd = {
NULL, "hme", DV_IFNET
   88 };
   90 #define HME_RX_OFFSET   2
   92 void            hme_start(struct ifnet *);
   93 void            hme_stop(struct hme_softc *);
   94 int             hme_ioctl(struct ifnet *, u_long, caddr_t);
   95 void            hme_tick(void *);
   96 void            hme_watchdog(struct ifnet *);
   97 void            hme_shutdown(void *);
   98 void            hme_init(struct hme_softc *);
   99 void            hme_meminit(struct hme_softc *);
  100 void            hme_mifinit(struct hme_softc *);
  101 void            hme_reset(struct hme_softc *);
  102 void            hme_setladrf(struct hme_softc *);
  103 int             hme_newbuf(struct hme_softc *, struct hme_sxd *, int);
  104 int             hme_encap(struct hme_softc *, struct mbuf *, int *);
  106 /* MII methods & callbacks */
  107 static int      hme_mii_readreg(struct device *, int, int);
  108 static void     hme_mii_writereg(struct device *, int, int, int);
  109 static void     hme_mii_statchg(struct device *);
  111 int             hme_mediachange(struct ifnet *);
  112 void            hme_mediastatus(struct ifnet *, struct ifmediareq *);
  114 int             hme_eint(struct hme_softc *, u_int);
  115 int             hme_rint(struct hme_softc *);
  116 int             hme_tint(struct hme_softc *);
  117 /* TCP/UDP checksum offload support */
  118 void            hme_rxcksum(struct mbuf *, u_int32_t);
  120 void
hme_config(sc)
  122         struct hme_softc *sc;
  123 {
  124         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  125         struct mii_data *mii = &sc->sc_mii;
  126         struct mii_softc *child;
bus_dma_tag_t dmatag = sc->sc_dmatag;
bus_dma_segment_t seg;
bus_size_t size;
  130         int rseg, error, i;
  132         /*
  133          * HME common initialization.
  134          *
  135          * hme_softc fields that must be initialized by the front-end:
  136          *
  137          * the bus tag:
  138          *      sc_bustag
  139          *
  140          * the dma bus tag:
  141          *      sc_dmatag
  142          *
  143          * the bus handles:
  144          *      sc_seb          (Shared Ethernet Block registers)
  145          *      sc_erx          (Receiver Unit registers)
  146          *      sc_etx          (Transmitter Unit registers)
  147          *      sc_mac          (MAC registers)
  148          *      sc_mif          (Management Interface registers)
  149          *
  150          * the maximum bus burst size:
  151          *      sc_burst
  152          *
  153          * the local Ethernet address:
  154          *      sc_arpcom.ac_enaddr
  155          *
  156          */
  158         /* Make sure the chip is stopped. */
hme_stop(sc);
  161         for (i = 0; i < HME_TX_RING_SIZE; i++) {
  162                 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1,
MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
  164                     &sc->sc_txd[i].sd_map) != 0) {
sc->sc_txd[i].sd_map = NULL;
  166                         goto fail;
  167                 }
  168         }
  169         for (i = 0; i < HME_RX_RING_SIZE; i++) {
  170                 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1,
MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
  172                     &sc->sc_rxd[i].sd_map) != 0) {
sc->sc_rxd[i].sd_map = NULL;
  174                         goto fail;
  175                 }
  176         }
  177         if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 0,
BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_rxmap_spare) != 0) {
sc->sc_rxmap_spare = NULL;
  180                 goto fail;
  181         }
  183         /*
  184          * Allocate DMA capable memory
  185          * Buffer descriptors must be aligned on a 2048 byte boundary;
  186          * take this into account when calculating the size. Note that
  187          * the maximum number of descriptors (256) occupies 2048 bytes,
  188          * so we allocate that much regardless of the number of descriptors.
  189          */
size = (HME_XD_SIZE * HME_RX_RING_MAX) +        /* RX descriptors */
  191             (HME_XD_SIZE * HME_TX_RING_MAX);            /* TX descriptors */
  193         /* Allocate DMA buffer */
  194         if ((error = bus_dmamem_alloc(dmatag, size, 2048, 0, &seg, 1, &rseg,
BUS_DMA_NOWAIT)) != 0) {
printf("\n%s: DMA buffer alloc error %d\n",
sc->sc_dev.dv_xname, error);
  198                 return;
  199         }
  201         /* Map DMA memory in CPU addressable space */
  202         if ((error = bus_dmamem_map(dmatag, &seg, rseg, size,
  203             &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
printf("\n%s: DMA buffer map error %d\n",
sc->sc_dev.dv_xname, error);
bus_dmamap_unload(dmatag, sc->sc_dmamap);
bus_dmamem_free(dmatag, &seg, rseg);
  208                 return;
  209         }
  211         if ((error = bus_dmamap_create(dmatag, size, 1, size, 0,
BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
printf("\n%s: DMA map create error %d\n",
sc->sc_dev.dv_xname, error);
  215                 return;
  216         }
  218         /* Load the buffer */
  219         if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap,
sc->sc_rb.rb_membase, size, NULL,
BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
printf("\n%s: DMA buffer map load error %d\n",
sc->sc_dev.dv_xname, error);
bus_dmamem_free(dmatag, &seg, rseg);
  225                 return;
  226         }
sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
  231         /* Initialize ifnet structure. */
strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname);
ifp->if_softc = sc;
ifp->if_start = hme_start;
ifp->if_ioctl = hme_ioctl;
ifp->if_watchdog = hme_watchdog;
ifp->if_flags =
IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
sc->sc_if_flags = ifp->if_flags;
IFQ_SET_READY(&ifp->if_snd);
ifp->if_capabilities = IFCAP_VLAN_MTU;
  243         /* Initialize ifmedia structures and MII info */
mii->mii_ifp = ifp;
mii->mii_readreg = hme_mii_readreg; 
mii->mii_writereg = hme_mii_writereg;
mii->mii_statchg = hme_mii_statchg;
ifmedia_init(&mii->mii_media, IFM_IMASK,
hme_mediachange, hme_mediastatus);
hme_mifinit(sc);
  254         if (sc->sc_tcvr == -1)
mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, 0);
  257         else
mii_attach(&sc->sc_dev, mii, 0xffffffff, sc->sc_tcvr,
MII_OFFSET_ANY, 0);
child = LIST_FIRST(&mii->mii_phys);
  262         if (child == NULL) {
  263                 /* No PHY attached */
ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
  266         } else {
  267                 /*
  268                  * Walk along the list of attached MII devices and
  269                  * establish an `MII instance' to `phy number'
  270                  * mapping. We'll use this mapping in media change
  271                  * requests to determine which phy to use to program
  272                  * the MIF configuration register.
  273                  */
  274                 for (; child != NULL; child = LIST_NEXT(child, mii_list)) {
  275                         /*
  276                          * Note: we support just two PHYs: the built-in
  277                          * internal device and an external on the MII
  278                          * connector.
  279                          */
  280                         if (child->mii_phy > 1 || child->mii_inst > 1) {
printf("%s: cannot accommodate MII device %s"
  282                                     " at phy %d, instance %d\n",
sc->sc_dev.dv_xname,
child->mii_dev.dv_xname,
child->mii_phy, child->mii_inst);
  286                                 continue;
  287                         }
sc->sc_phys[child->mii_inst] = child->mii_phy;
  290                 }
  292                 /*
  293                  * XXX - we can really do the following ONLY if the
  294                  * phy indeed has the auto negotiation capability!!
  295                  */
ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO);
  297         }
  299         /* Attach the interface. */
if_attach(ifp);
ether_ifattach(ifp);
sc->sc_sh = shutdownhook_establish(hme_shutdown, sc);
  304         if (sc->sc_sh == NULL)
panic("hme_config: can't establish shutdownhook");
timeout_set(&sc->sc_tick_ch, hme_tick, sc);
  308         return;
fail:
  311         if (sc->sc_rxmap_spare != NULL)
bus_dmamap_destroy(sc->sc_dmatag, sc->sc_rxmap_spare);
  313         for (i = 0; i < HME_TX_RING_SIZE; i++)
  314                 if (sc->sc_txd[i].sd_map != NULL)
bus_dmamap_destroy(sc->sc_dmatag, sc->sc_txd[i].sd_map);
  316         for (i = 0; i < HME_RX_RING_SIZE; i++)
  317                 if (sc->sc_rxd[i].sd_map != NULL)
bus_dmamap_destroy(sc->sc_dmatag, sc->sc_rxd[i].sd_map);
  319 }
  321 void
hme_tick(arg)
  323         void *arg;
  324 {
  325         struct hme_softc *sc = arg;
  326         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mac = sc->sc_mac;
  329         int s;
s = splnet();
  332         /*
  333          * Unload collision counters
  334          */
ifp->if_collisions +=
bus_space_read_4(t, mac, HME_MACI_NCCNT) +
bus_space_read_4(t, mac, HME_MACI_FCCNT) +
bus_space_read_4(t, mac, HME_MACI_EXCNT) +
bus_space_read_4(t, mac, HME_MACI_LTCNT);
  341         /*
  342          * then clear the hardware counters.
  343          */
bus_space_write_4(t, mac, HME_MACI_NCCNT, 0);
bus_space_write_4(t, mac, HME_MACI_FCCNT, 0);
bus_space_write_4(t, mac, HME_MACI_EXCNT, 0);
bus_space_write_4(t, mac, HME_MACI_LTCNT, 0);
mii_tick(&sc->sc_mii);
splx(s);
timeout_add(&sc->sc_tick_ch, hz);
  353 }
  355 void
hme_reset(sc)
  357         struct hme_softc *sc;
  358 {
  359         int s;
s = splnet();
hme_init(sc);
splx(s);
  364 }
  366 void
hme_stop(sc)
  368         struct hme_softc *sc;
  369 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t seb = sc->sc_seb;
  372         int n;
timeout_del(&sc->sc_tick_ch);
mii_down(&sc->sc_mii);
  377         /* Mask all interrupts */
bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff);
  380         /* Reset transmitter and receiver */
bus_space_write_4(t, seb, HME_SEBI_RESET,
  382             (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX));
  384         for (n = 0; n < 20; n++) {
u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET);
  386                 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0)
  387                         break;
DELAY(20);
  389         }
  390         if (n >= 20)
printf("%s: hme_stop: reset failed\n", sc->sc_dev.dv_xname);
  393         for (n = 0; n < HME_TX_RING_SIZE; n++) {
  394                 if (sc->sc_txd[n].sd_loaded) {
bus_dmamap_sync(sc->sc_dmatag, sc->sc_txd[n].sd_map,
  396                             0, sc->sc_txd[n].sd_map->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmatag, sc->sc_txd[n].sd_map);
sc->sc_txd[n].sd_loaded = 0;
  400                 }
  401                 if (sc->sc_txd[n].sd_mbuf != NULL) {
m_freem(sc->sc_txd[n].sd_mbuf);
sc->sc_txd[n].sd_mbuf = NULL;
  404                 }
  405         }
  406 }
  408 void
hme_meminit(sc)
  410         struct hme_softc *sc;
  411 {
bus_addr_t dma;
caddr_t p;
  414         unsigned int i;
  415         struct hme_ring *hr = &sc->sc_rb;
p = hr->rb_membase;
dma = hr->rb_dmabase;
  420         /*
  421          * Allocate transmit descriptors
  422          */
hr->rb_txd = p;
hr->rb_txddma = dma;
p += HME_TX_RING_SIZE * HME_XD_SIZE;
dma += HME_TX_RING_SIZE * HME_XD_SIZE;
  427         /* We have reserved descriptor space until the next 2048 byte boundary.*/
dma = (bus_addr_t)roundup((u_long)dma, 2048);
p = (caddr_t)roundup((u_long)p, 2048);
  431         /*
  432          * Allocate receive descriptors
  433          */
hr->rb_rxd = p;
hr->rb_rxddma = dma;
p += HME_RX_RING_SIZE * HME_XD_SIZE;
dma += HME_RX_RING_SIZE * HME_XD_SIZE;
  438         /* Again move forward to the next 2048 byte boundary.*/
dma = (bus_addr_t)roundup((u_long)dma, 2048);
p = (caddr_t)roundup((u_long)p, 2048);
  442         /*
  443          * Initialize transmit descriptors
  444          */
  445         for (i = 0; i < HME_TX_RING_SIZE; i++) {
HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, 0);
HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0);
sc->sc_txd[i].sd_mbuf = NULL;
  449         }
  451         /*
  452          * Initialize receive descriptors
  453          */
  454         for (i = 0; i < HME_RX_RING_SIZE; i++) {
  455                 if (hme_newbuf(sc, &sc->sc_rxd[i], 1)) {
printf("%s: rx allocation failed\n",
sc->sc_dev.dv_xname);
  458                         break;
  459                 }
HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i,
sc->sc_rxd[i].sd_map->dm_segs[0].ds_addr);
HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i,
HME_XD_OWN | HME_XD_ENCODE_RSIZE(HME_RX_PKTSIZE));
  464         }
sc->sc_tx_prod = sc->sc_tx_cons = sc->sc_tx_cnt = 0;
sc->sc_last_rd = 0;
  468 }
  470 /*
  471  * Initialization of interface; set up initialization block
  472  * and transmit/receive descriptor rings.
  473  */
  474 void
hme_init(sc)
  476         struct hme_softc *sc;
  477 {
  478         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t seb = sc->sc_seb;
bus_space_handle_t etx = sc->sc_etx;
bus_space_handle_t erx = sc->sc_erx;
bus_space_handle_t mac = sc->sc_mac;
u_int8_t *ea;
u_int32_t v, n;
  487         /*
  488          * Initialization sequence. The numbered steps below correspond
  489          * to the sequence outlined in section 6.3.5.1 in the Ethernet
  490          * Channel Engine manual (part of the PCIO manual).
  491          * See also the STP2002-STQ document from Sun Microsystems.
  492          */
  494         /* step 1 & 2. Reset the Ethernet Channel */
hme_stop(sc);
  497         /* Re-initialize the MIF */
hme_mifinit(sc);
  500         /* Call MI reset function if any */
  501         if (sc->sc_hwreset)
  502                 (*sc->sc_hwreset)(sc);
  504 #if 0
  505         /* Mask all MIF interrupts, just in case */
bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff);
  507 #endif
  509         /* step 3. Setup data structures in host memory */
hme_meminit(sc);
  512         /* step 4. TX MAC registers & counters */
bus_space_write_4(t, mac, HME_MACI_NCCNT, 0);
bus_space_write_4(t, mac, HME_MACI_FCCNT, 0);
bus_space_write_4(t, mac, HME_MACI_EXCNT, 0);
bus_space_write_4(t, mac, HME_MACI_LTCNT, 0);
bus_space_write_4(t, mac, HME_MACI_TXSIZE, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
  519         /* Load station MAC address */
ea = sc->sc_arpcom.ac_enaddr;
bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]);
bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]);
bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]);
  525         /*
  526          * Init seed for backoff
  527          * (source suggested by manual: low 10 bits of MAC address)
  528          */ 
v = ((ea[4] << 8) | ea[5]) & 0x3fff;
bus_space_write_4(t, mac, HME_MACI_RANDSEED, v);
  533         /* Note: Accepting power-on default for other MAC registers here.. */
  536         /* step 5. RX MAC registers & counters */
hme_setladrf(sc);
  539         /* step 6 & 7. Program Descriptor Ring Base Addresses */
bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma);
bus_space_write_4(t, etx, HME_ETXI_RSIZE, HME_TX_RING_SIZE);
bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma);
bus_space_write_4(t, mac, HME_MACI_RXSIZE, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
  546         /* step 8. Global Configuration & Interrupt Mask */
bus_space_write_4(t, seb, HME_SEBI_IMASK,
  548             ~(HME_SEB_STAT_HOSTTOTX | HME_SEB_STAT_RXTOHOST |
HME_SEB_STAT_TXALL | HME_SEB_STAT_TXPERR |
HME_SEB_STAT_RCNTEXP | HME_SEB_STAT_ALL_ERRORS));
  552         switch (sc->sc_burst) {
  553         default:
v = 0;
  555                 break;
  556         case 16:
v = HME_SEB_CFG_BURST16;
  558                 break;
  559         case 32:
v = HME_SEB_CFG_BURST32;
  561                 break;
  562         case 64:
v = HME_SEB_CFG_BURST64;
  564                 break;
  565         }
bus_space_write_4(t, seb, HME_SEBI_CFG, v);
  568         /* step 9. ETX Configuration: use mostly default values */
  570         /* Enable DMA */
v = bus_space_read_4(t, etx, HME_ETXI_CFG);
v |= HME_ETX_CFG_DMAENABLE;
bus_space_write_4(t, etx, HME_ETXI_CFG, v);
  575         /* Transmit Descriptor ring size: in increments of 16 */
bus_space_write_4(t, etx, HME_ETXI_RSIZE, HME_TX_RING_SIZE / 16 - 1);
  578         /* step 10. ERX Configuration */
v = bus_space_read_4(t, erx, HME_ERXI_CFG);
v &= ~HME_ERX_CFG_RINGSIZE256;
  581 #if HME_RX_RING_SIZE == 32
v |= HME_ERX_CFG_RINGSIZE32;
  583 #elif HME_RX_RING_SIZE == 64
v |= HME_ERX_CFG_RINGSIZE64;
  585 #elif HME_RX_RING_SIZE == 128
v |= HME_ERX_CFG_RINGSIZE128;
  587 #elif HME_RX_RING_SIZE == 256
v |= HME_ERX_CFG_RINGSIZE256;
  589 #else
  590 # error "RX ring size must be 32, 64, 128, or 256"
  591 #endif
  592         /* Enable DMA */
v |= HME_ERX_CFG_DMAENABLE | (HME_RX_OFFSET << 3);
  594         /* RX TCP/UDP cksum offset */
n = (ETHER_HDR_LEN + sizeof(struct ip)) / 2;
n = (n << HME_ERX_CFG_CSUM_SHIFT) & HME_ERX_CFG_CSUMSTART;
v |= n;
bus_space_write_4(t, erx, HME_ERXI_CFG, v);
  600         /* step 11. XIF Configuration */
v = bus_space_read_4(t, mac, HME_MACI_XIF);
v |= HME_MAC_XIF_OE;
bus_space_write_4(t, mac, HME_MACI_XIF, v);
  605         /* step 12. RX_MAC Configuration Register */
v = bus_space_read_4(t, mac, HME_MACI_RXCFG);
v |= HME_MAC_RXCFG_ENABLE;
bus_space_write_4(t, mac, HME_MACI_RXCFG, v);
  610         /* step 13. TX_MAC Configuration Register */
v = bus_space_read_4(t, mac, HME_MACI_TXCFG);
v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP);
bus_space_write_4(t, mac, HME_MACI_TXCFG, v);
  615         /* step 14. Issue Transmit Pending command */
  617         /* Call MI initialization function if any */
  618         if (sc->sc_hwinit)
  619                 (*sc->sc_hwinit)(sc);
  621         /* Set the current media. */
mii_mediachg(&sc->sc_mii);
  624         /* Start the one second timer. */
timeout_add(&sc->sc_tick_ch, hz);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
sc->sc_if_flags = ifp->if_flags;
ifp->if_timer = 0;
hme_start(ifp);
  632 }
  634 void
hme_start(ifp)
  636         struct ifnet *ifp;
  637 {
  638         struct hme_softc *sc = (struct hme_softc *)ifp->if_softc;
  639         struct mbuf *m;
  640         int bix, cnt = 0;
  642         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
  643                 return;
bix = sc->sc_tx_prod;
  646         while (sc->sc_txd[bix].sd_mbuf == NULL) {
IFQ_POLL(&ifp->if_snd, m);
  648                 if (m == NULL)
  649                         break;
  651 #if NBPFILTER > 0
  652                 /*
  653                  * If BPF is listening on this interface, let it see the
  654                  * packet before we commit it to the wire.
  655                  */
  656                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
  658 #endif
  660                 if (hme_encap(sc, m, &bix)) {
ifp->if_flags |= IFF_OACTIVE;
  662                         break;
  663                 }
IFQ_DEQUEUE(&ifp->if_snd, m);
bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING,
HME_ETX_TP_DMAWAKEUP);
cnt++;
  670         }
  672         if (cnt != 0) {
sc->sc_tx_prod = bix;
ifp->if_timer = 5;
  675         }
  676 }
  678 /*
  679  * Transmit interrupt.
  680  */
  681 int
hme_tint(sc)
  683         struct hme_softc *sc;
  684 {
  685         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  686         unsigned int ri, txflags;
  687         struct hme_sxd *sd;
  688         int cnt = sc->sc_tx_cnt;
  690         /* Fetch current position in the transmit ring */
ri = sc->sc_tx_cons;
sd = &sc->sc_txd[ri];
  694         for (;;) {
  695                 if (cnt <= 0)
  696                         break;
txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri);
  700                 if (txflags & HME_XD_OWN)
  701                         break;
ifp->if_flags &= ~IFF_OACTIVE;
  704                 if (txflags & HME_XD_EOP)
ifp->if_opackets++;
bus_dmamap_sync(sc->sc_dmatag, sd->sd_map,
  708                     0, sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmatag, sd->sd_map);
sd->sd_loaded = 0;
  712                 if (sd->sd_mbuf != NULL) {
m_freem(sd->sd_mbuf);
sd->sd_mbuf = NULL;
  715                 }
  717                 if (++ri == HME_TX_RING_SIZE) {
ri = 0;
sd = sc->sc_txd;
  720                 } else
sd++;
  723                 --cnt;
  724         }
sc->sc_tx_cnt = cnt;
ifp->if_timer = cnt > 0 ? 5 : 0;
  729         /* Update ring */
sc->sc_tx_cons = ri;
hme_start(ifp);
  734         return (1);
  735 }
  737 /*
  738  * XXX layering violation
  739  *
  740  * If we can have additional csum data member in 'struct pkthdr' for
  741  * these incomplete checksum offload capable hardware, things would be
  742  * much simpler. That member variable will carry partial checksum
  743  * data and it may be evaluated in TCP/UDP input handler after
  744  * computing pseudo header checksumming.
  745  */
  746 void
hme_rxcksum(struct mbuf *m, u_int32_t flags)
  748 {
  749         struct ether_header *eh;
  750         struct ip *ip;
  751         struct udphdr *uh;
int32_t hlen, len, pktlen;
u_int16_t cksum, *opts;
u_int32_t temp32;
  755         union pseudoh {
  756                 struct hdr {
u_int16_t len;
u_int8_t ttl;
u_int8_t proto;
u_int32_t src;
u_int32_t dst;
  762                 } h;
u_int16_t w[6];
  764         } ph;
pktlen = m->m_pkthdr.len;
  767         if (pktlen < sizeof(struct ether_header))
  768                 return;
eh = mtod(m, struct ether_header *);
  770         if (eh->ether_type != htons(ETHERTYPE_IP))
  771                 return;
ip = (struct ip *)(eh + 1);
  773         if (ip->ip_v != IPVERSION)
  774                 return;
hlen = ip->ip_hl << 2;
pktlen -= sizeof(struct ether_header);
  778         if (hlen < sizeof(struct ip))
  779                 return;
  780         if (ntohs(ip->ip_len) < hlen)
  781                 return;
  782         if (ntohs(ip->ip_len) != pktlen) 
  783                 return;
  784         if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
  785                 return; /* can't handle fragmented packet */
  787         switch (ip->ip_p) {
  788         case IPPROTO_TCP:
  789                 if (pktlen < (hlen + sizeof(struct tcphdr)))
  790                         return;
  791                 break;
  792         case IPPROTO_UDP:
  793                 if (pktlen < (hlen + sizeof(struct udphdr)))
  794                         return;
uh = (struct udphdr *)((caddr_t)ip + hlen);
  796                 if (uh->uh_sum == 0)
  797                         return; /* no checksum */
  798                 break;
  799         default:
  800                 return;
  801         }
cksum = htons(~(flags & HME_XD_RXCKSUM));
  804         /* cksum fixup for IP options */
len = hlen - sizeof(struct ip);
  806         if (len > 0) {
opts = (u_int16_t *)(ip + 1);
  808                 for (; len > 0; len -= sizeof(u_int16_t), opts++) {
temp32 = cksum - *opts;
temp32 = (temp32 >> 16) + (temp32 & 65535);
cksum = temp32 & 65535;
  812                 }
  813         }
  814         /* cksum fixup for pseudo-header, replace with in_cksum_phdr()? */
ph.h.len = htons(ntohs(ip->ip_len) - hlen);
ph.h.ttl = 0;
ph.h.proto = ip->ip_p;
ph.h.src = ip->ip_src.s_addr;
ph.h.dst = ip->ip_dst.s_addr;
temp32 = cksum;
opts = &ph.w[0];
temp32 += opts[0] + opts[1] + opts[2] + opts[3] + opts[4] + opts[5];
temp32 = (temp32 >> 16) + (temp32 & 65535);
temp32 += (temp32 >> 16);
cksum = ~temp32;
  826         if (cksum == 0) {
m->m_pkthdr.csum_flags |=
M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK;
  829         }
  830 }
  832 /*
  833  * Receive interrupt.
  834  */
  835 int
hme_rint(sc)
  837         struct hme_softc *sc;
  838 {
  839         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  840         struct mbuf *m;
  841         struct hme_sxd *sd;
  842         unsigned int ri, len;
u_int32_t flags;
ri = sc->sc_last_rd;
sd = &sc->sc_rxd[ri];
  848         /*
  849          * Process all buffers with valid data.
  850          */
  851         for (;;) {
flags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_rxd, ri);
  853                 if (flags & HME_XD_OWN)
  854                         break;
  856                 if (flags & HME_XD_OFL) {
printf("%s: buffer overflow, ri=%d; flags=0x%x\n",
sc->sc_dev.dv_xname, ri, flags);
  859                         goto again;
  860                 }
m = sd->sd_mbuf;
len = HME_XD_DECODE_RSIZE(flags);
m->m_pkthdr.len = m->m_len = len;
  866                 if (hme_newbuf(sc, sd, 0)) {
  867                         /*
  868                          * Allocation of new mbuf cluster failed, leave the
  869                          * old one in place and keep going.
  870                          */
ifp->if_ierrors++;
  872                         goto again;
  873                 }
ifp->if_ipackets++;
hme_rxcksum(m, flags);
  878 #if NBPFILTER > 0
  879                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
  881 #endif
ether_input_mbuf(ifp, m);
again:
HME_XD_SETADDR(sc->sc_pci, sc->sc_rb.rb_rxd, ri,
sd->sd_map->dm_segs[0].ds_addr);
HME_XD_SETFLAGS(sc->sc_pci, sc->sc_rb.rb_rxd, ri,
HME_XD_OWN | HME_XD_ENCODE_RSIZE(HME_RX_PKTSIZE));
  891                 if (++ri == HME_RX_RING_SIZE) {
ri = 0;
sd = sc->sc_rxd;
  894                 } else
sd++;
  896         }
sc->sc_last_rd = ri;
  899         return (1);
  900 }
  902 int
hme_eint(sc, status)
  904         struct hme_softc *sc;
u_int status;
  906 {
  907         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  909         if (status & HME_SEB_STAT_MIFIRQ) {
printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname);
status &= ~HME_SEB_STAT_MIFIRQ;
  912         }
  914         if (status & HME_SEB_STAT_DTIMEXP) {
ifp->if_oerrors++;
status &= ~HME_SEB_STAT_DTIMEXP;
  917         }
  919         if (status & HME_SEB_STAT_NORXD) {
ifp->if_ierrors++;
status &= ~HME_SEB_STAT_NORXD;
  922         }
status &= ~(HME_SEB_STAT_RXTOHOST | HME_SEB_STAT_GOTFRAME |
HME_SEB_STAT_SENTFRAME | HME_SEB_STAT_HOSTTOTX |
HME_SEB_STAT_TXALL);
  928         if (status == 0)
  929                 return (1);
  931 #ifdef HME_DEBUG
printf("%s: status=%b\n", sc->sc_dev.dv_xname, status, HME_SEB_STAT_BITS);
  933 #endif
  934         return (1);
  935 }
  937 int
hme_intr(v)
  939         void *v;
  940 {
  941         struct hme_softc *sc = (struct hme_softc *)v;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t seb = sc->sc_seb;
u_int32_t status;
  945         int r = 0;
status = bus_space_read_4(t, seb, HME_SEBI_STAT);
  949         if ((status & HME_SEB_STAT_ALL_ERRORS) != 0)
r |= hme_eint(sc, status);
  952         if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0)
r |= hme_tint(sc);
  955         if ((status & HME_SEB_STAT_RXTOHOST) != 0)
r |= hme_rint(sc);
  958         return (r);
  959 }
  962 void
hme_watchdog(ifp)
  964         struct ifnet *ifp;
  965 {
  966         struct hme_softc *sc = ifp->if_softc;
log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
ifp->if_oerrors++;
hme_reset(sc);
  972 }
  974 /*
  975  * Initialize the MII Management Interface
  976  */
  977 void
hme_mifinit(sc)
  979         struct hme_softc *sc;
  980 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mif = sc->sc_mif;
bus_space_handle_t mac = sc->sc_mac;
  984         int phy;
u_int32_t v;
v = bus_space_read_4(t, mif, HME_MIFI_CFG);
phy = HME_PHYAD_EXTERNAL;
  989         if (v & HME_MIF_CFG_MDI1)
phy = sc->sc_tcvr = HME_PHYAD_EXTERNAL;
  991         else if (v & HME_MIF_CFG_MDI0)
phy = sc->sc_tcvr = HME_PHYAD_INTERNAL;
  993         else
sc->sc_tcvr = -1;
  996         /* Configure the MIF in frame mode, no poll, current phy select */
v = 0;
  998         if (phy == HME_PHYAD_EXTERNAL)
v |= HME_MIF_CFG_PHY;
bus_space_write_4(t, mif, HME_MIFI_CFG, v);
 1002         /* If an external transceiver is selected, enable its MII drivers */
v = bus_space_read_4(t, mac, HME_MACI_XIF);
v &= ~HME_MAC_XIF_MIIENABLE;
 1005         if (phy == HME_PHYAD_EXTERNAL)
v |= HME_MAC_XIF_MIIENABLE;
bus_space_write_4(t, mac, HME_MACI_XIF, v);
 1008 }
 1010 /*
 1011  * MII interface
 1012  */
 1013 static int
hme_mii_readreg(self, phy, reg)
 1015         struct device *self;
 1016         int phy, reg;
 1017 {
 1018         struct hme_softc *sc = (struct hme_softc *)self;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mif = sc->sc_mif;
bus_space_handle_t mac = sc->sc_mac;
u_int32_t v, xif_cfg, mifi_cfg;
 1023         int n;
 1025         if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL)
 1026                 return (0);
 1028         /* Select the desired PHY in the MIF configuration register */
v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG);
v &= ~HME_MIF_CFG_PHY;
 1031         if (phy == HME_PHYAD_EXTERNAL)
v |= HME_MIF_CFG_PHY;
bus_space_write_4(t, mif, HME_MIFI_CFG, v);
 1035         /* Enable MII drivers on external transceiver */ 
v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF);
 1037         if (phy == HME_PHYAD_EXTERNAL)
v |= HME_MAC_XIF_MIIENABLE;
 1039         else
v &= ~HME_MAC_XIF_MIIENABLE;
bus_space_write_4(t, mac, HME_MACI_XIF, v);
 1043         /* Construct the frame command */
v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) |
HME_MIF_FO_TAMSB |
 1046             (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) |
 1047             (phy << HME_MIF_FO_PHYAD_SHIFT) |
 1048             (reg << HME_MIF_FO_REGAD_SHIFT);
bus_space_write_4(t, mif, HME_MIFI_FO, v);
 1051         for (n = 0; n < 100; n++) {
DELAY(1);
v = bus_space_read_4(t, mif, HME_MIFI_FO);
 1054                 if (v & HME_MIF_FO_TALSB) {
v &= HME_MIF_FO_DATA;
 1056                         goto out;
 1057                 }
 1058         }
v = 0;
printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname);
out:
 1064         /* Restore MIFI_CFG register */
bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg);
 1066         /* Restore XIF register */
bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg);
 1068         return (v);
 1069 }
 1071 static void
hme_mii_writereg(self, phy, reg, val)
 1073         struct device *self;
 1074         int phy, reg, val;
 1075 {
 1076         struct hme_softc *sc = (void *)self;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mif = sc->sc_mif;
bus_space_handle_t mac = sc->sc_mac;
u_int32_t v, xif_cfg, mifi_cfg;
 1081         int n;
 1083         /* We can at most have two PHYs */
 1084         if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL)
 1085                 return;
 1087         /* Select the desired PHY in the MIF configuration register */
v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG);
v &= ~HME_MIF_CFG_PHY;
 1090         if (phy == HME_PHYAD_EXTERNAL)
v |= HME_MIF_CFG_PHY;
bus_space_write_4(t, mif, HME_MIFI_CFG, v);
 1094         /* Enable MII drivers on external transceiver */ 
v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF);
 1096         if (phy == HME_PHYAD_EXTERNAL)
v |= HME_MAC_XIF_MIIENABLE;
 1098         else
v &= ~HME_MAC_XIF_MIIENABLE;
bus_space_write_4(t, mac, HME_MACI_XIF, v);
 1102         /* Construct the frame command */
v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT)  |
HME_MIF_FO_TAMSB                            |
 1105             (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) |
 1106             (phy << HME_MIF_FO_PHYAD_SHIFT)             |
 1107             (reg << HME_MIF_FO_REGAD_SHIFT)             |
 1108             (val & HME_MIF_FO_DATA);
bus_space_write_4(t, mif, HME_MIFI_FO, v);
 1111         for (n = 0; n < 100; n++) {
DELAY(1);
v = bus_space_read_4(t, mif, HME_MIFI_FO);
 1114                 if (v & HME_MIF_FO_TALSB)
 1115                         goto out;
 1116         }
printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname);
out:
 1120         /* Restore MIFI_CFG register */
bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg);
 1122         /* Restore XIF register */
bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg);
 1124 }
 1126 static void
hme_mii_statchg(dev)
 1128         struct device *dev;
 1129 {
 1130         struct hme_softc *sc = (void *)dev;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mac = sc->sc_mac;
u_int32_t v;
 1135 #ifdef HMEDEBUG
 1136         if (sc->sc_debug)
printf("hme_mii_statchg: status change\n", phy);
 1138 #endif
 1140         /* Set the MAC Full Duplex bit appropriately */
 1141         /* Apparently the hme chip is SIMPLEX if working in full duplex mode,
 1142            but not otherwise. */
v = bus_space_read_4(t, mac, HME_MACI_TXCFG);
 1144         if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) {
v |= HME_MAC_TXCFG_FULLDPLX;
sc->sc_arpcom.ac_if.if_flags |= IFF_SIMPLEX;
 1147         } else {
v &= ~HME_MAC_TXCFG_FULLDPLX;
sc->sc_arpcom.ac_if.if_flags &= ~IFF_SIMPLEX;
 1150         }
sc->sc_if_flags = sc->sc_arpcom.ac_if.if_flags;
bus_space_write_4(t, mac, HME_MACI_TXCFG, v);
 1153 }
 1155 int
hme_mediachange(ifp)
 1157         struct ifnet *ifp;
 1158 {
 1159         struct hme_softc *sc = ifp->if_softc;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mif = sc->sc_mif;
bus_space_handle_t mac = sc->sc_mac;
 1163         int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
 1164         int phy = sc->sc_phys[instance];
u_int32_t v;
 1167 #ifdef HMEDEBUG
 1168         if (sc->sc_debug)
printf("hme_mediachange: phy = %d\n", phy);
 1170 #endif
 1171         if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER)
 1172                 return (EINVAL);
 1174         /* Select the current PHY in the MIF configuration register */
v = bus_space_read_4(t, mif, HME_MIFI_CFG);
v &= ~HME_MIF_CFG_PHY;
 1177         if (phy == HME_PHYAD_EXTERNAL)
v |= HME_MIF_CFG_PHY;
bus_space_write_4(t, mif, HME_MIFI_CFG, v);
 1181         /* If an external transceiver is selected, enable its MII drivers */
v = bus_space_read_4(t, mac, HME_MACI_XIF);
v &= ~HME_MAC_XIF_MIIENABLE;
 1184         if (phy == HME_PHYAD_EXTERNAL)
v |= HME_MAC_XIF_MIIENABLE;
bus_space_write_4(t, mac, HME_MACI_XIF, v);
 1188         return (mii_mediachg(&sc->sc_mii));
 1189 }
 1191 void
hme_mediastatus(ifp, ifmr)
 1193         struct ifnet *ifp;
 1194         struct ifmediareq *ifmr;
 1195 {
 1196         struct hme_softc *sc = ifp->if_softc;
 1198         if ((ifp->if_flags & IFF_UP) == 0)
 1199                 return;
mii_pollstat(&sc->sc_mii);
ifmr->ifm_active = sc->sc_mii.mii_media_active;
ifmr->ifm_status = sc->sc_mii.mii_media_status;
 1204 }
 1206 /*
 1207  * Process an ioctl request.
 1208  */
 1209 int
hme_ioctl(ifp, cmd, data)
 1211         struct ifnet *ifp;
u_long cmd;
caddr_t data;
 1214 {
 1215         struct hme_softc *sc = ifp->if_softc;
 1216         struct ifaddr *ifa = (struct ifaddr *)data;
 1217         struct ifreq *ifr = (struct ifreq *)data;
 1218         int s, error = 0;
s = splnet();
 1222         if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
splx(s);
 1224                 return (error);
 1225         }
 1227         switch (cmd) {
 1229         case SIOCSIFADDR:
 1230                 switch (ifa->ifa_addr->sa_family) {
 1231 #ifdef INET
 1232                 case AF_INET:
 1233                         if (ifp->if_flags & IFF_UP)
hme_setladrf(sc);
 1235                         else {
ifp->if_flags |= IFF_UP;
hme_init(sc);
 1238                         }
arp_ifinit(&sc->sc_arpcom, ifa);
 1240                         break;
 1241 #endif
 1242                 default:
hme_init(sc);
 1244                         break;
 1245                 }
 1246                 break;
 1248         case SIOCSIFFLAGS:
 1249                 if ((ifp->if_flags & IFF_UP) == 0 &&
 1250                     (ifp->if_flags & IFF_RUNNING) != 0) {
 1251                         /*
 1252                          * If interface is marked down and it is running, then
 1253                          * stop it.
 1254                          */
hme_stop(sc);
ifp->if_flags &= ~IFF_RUNNING;
 1257                 } else if ((ifp->if_flags & IFF_UP) != 0 &&
 1258                            (ifp->if_flags & IFF_RUNNING) == 0) {
 1259                         /*
 1260                          * If interface is marked up and it is stopped, then
 1261                          * start it.
 1262                          */
hme_init(sc);
 1264                 } else if ((ifp->if_flags & IFF_UP) != 0) {
 1265                         /*
 1266                          * If setting debug or promiscuous mode, do not reset
 1267                          * the chip; for everything else, call hme_init()
 1268                          * which will trigger a reset.
 1269                          */
 1270 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG)
 1271                         if (ifp->if_flags == sc->sc_if_flags)
 1272                                 break;
 1273                         if ((ifp->if_flags & (~RESETIGN))
 1274                             == (sc->sc_if_flags & (~RESETIGN)))
hme_setladrf(sc);
 1276                         else
hme_init(sc);
 1278 #undef RESETIGN
 1279                 }
 1280 #ifdef HMEDEBUG
sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0;
 1282 #endif
 1283                 break;
 1285         case SIOCADDMULTI:
 1286         case SIOCDELMULTI:
error = (cmd == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_arpcom) :
ether_delmulti(ifr, &sc->sc_arpcom);
 1291                 if (error == ENETRESET) {
 1292                         /*
 1293                          * Multicast list has changed; set the hardware filter
 1294                          * accordingly.
 1295                          */
 1296                         if (ifp->if_flags & IFF_RUNNING)
hme_setladrf(sc);
error = 0;
 1299                 }
 1300                 break;
 1302         case SIOCGIFMEDIA:
 1303         case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
 1305                 break;
 1307         default:
error = ENOTTY;
 1309                 break;
 1310         }
sc->sc_if_flags = ifp->if_flags;
splx(s);
 1314         return (error);
 1315 }
 1317 void
hme_shutdown(arg)
 1319         void *arg;
 1320 {
hme_stop((struct hme_softc *)arg);
 1322 }
 1324 /*
 1325  * Set up the logical address filter.
 1326  */
 1327 void
hme_setladrf(sc)
 1329         struct hme_softc *sc;
 1330 {
 1331         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
 1332         struct ether_multi *enm;
 1333         struct ether_multistep step;
 1334         struct arpcom *ac = &sc->sc_arpcom;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mac = sc->sc_mac;
u_int32_t hash[4];
u_int32_t v, crc;
 1340         /* Clear hash table */
hash[3] = hash[2] = hash[1] = hash[0] = 0;
 1343         /* Get current RX configuration */
v = bus_space_read_4(t, mac, HME_MACI_RXCFG);
 1346         if ((ifp->if_flags & IFF_PROMISC) != 0) {
 1347                 /* Turn on promiscuous mode; turn off the hash filter */
v |= HME_MAC_RXCFG_PMISC;
v &= ~HME_MAC_RXCFG_HENABLE;
ifp->if_flags |= IFF_ALLMULTI;
 1351                 goto chipit;
 1352         }
 1354         /* Turn off promiscuous mode; turn on the hash filter */
v &= ~HME_MAC_RXCFG_PMISC;
v |= HME_MAC_RXCFG_HENABLE;
 1358         /*
 1359          * Set up multicast address filter by passing all multicast addresses
 1360          * through a crc generator, and then using the high order 6 bits as an
 1361          * index into the 64 bit logical address filter.  The high order bit
 1362          * selects the word, while the rest of the bits select the bit within
 1363          * the word.
 1364          */
ETHER_FIRST_MULTI(step, ac, enm);
 1367         while (enm != NULL) {
 1368                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 1369                         /*
 1370                          * We must listen to a range of multicast addresses.
 1371                          * For now, just accept all multicasts, rather than
 1372                          * trying to set only those filter bits needed to match
 1373                          * the range.  (At this time, the only use of address
 1374                          * ranges is for IP multicast routing, for which the
 1375                          * range is big enough to require all bits set.)
 1376                          */
hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
ifp->if_flags |= IFF_ALLMULTI;
 1379                         goto chipit;
 1380                 }
crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN)>> 26; 
 1384                 /* Set the corresponding bit in the filter. */
hash[crc >> 4] |= 1 << (crc & 0xf);
ETHER_NEXT_MULTI(step, enm);
 1388         }
ifp->if_flags &= ~IFF_ALLMULTI;
chipit:
 1393         /* Now load the hash table into the chip */
bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]);
bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]);
bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]);
bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]);
bus_space_write_4(t, mac, HME_MACI_RXCFG, v);
 1399 }
 1401 int
hme_encap(sc, mhead, bixp)
 1403         struct hme_softc *sc;
 1404         struct mbuf *mhead;
 1405         int *bixp;
 1406 {
 1407         struct hme_sxd *sd;
 1408         struct mbuf *m;
 1409         int frag, cur, cnt = 0;
u_int32_t flags;
 1411         struct hme_ring *hr = &sc->sc_rb;
cur = frag = *bixp;
sd = &sc->sc_txd[frag];
 1416         for (m = mhead; m != NULL; m = m->m_next) {
 1417                 if (m->m_len == 0)
 1418                         continue;
 1420                 if ((HME_TX_RING_SIZE - (sc->sc_tx_cnt + cnt)) < 5)
 1421                         goto err;
 1423                 if (bus_dmamap_load(sc->sc_dmatag, sd->sd_map,
mtod(m, caddr_t), m->m_len, NULL, BUS_DMA_NOWAIT) != 0)
 1425                         goto err;
sd->sd_loaded = 1;
bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0,
sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
sd->sd_mbuf = NULL;
flags = HME_XD_ENCODE_TSIZE(m->m_len);
 1434                 if (cnt == 0)
flags |= HME_XD_SOP;
 1436                 else
flags |= HME_XD_OWN;
HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, frag,
sd->sd_map->dm_segs[0].ds_addr);
HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, frag, flags);
cur = frag;
cnt++;
 1445                 if (++frag == HME_TX_RING_SIZE) {
frag = 0;
sd = sc->sc_txd;
 1448                 } else
sd++;
 1450         }
 1452         /* Set end of packet on last descriptor. */
flags = HME_XD_GETFLAGS(sc->sc_pci, hr->rb_txd, cur);
flags |= HME_XD_EOP;
HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, cur, flags);
sc->sc_txd[cur].sd_mbuf = mhead;
 1458         /* Give first frame over to the hardware. */
flags = HME_XD_GETFLAGS(sc->sc_pci, hr->rb_txd, (*bixp));
flags |= HME_XD_OWN;
HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, (*bixp), flags);
sc->sc_tx_cnt += cnt;
 1464         *bixp = frag;
 1466         /* sync descriptors */
 1468         return (0);
err:
 1471         /*
 1472          * Invalidate the stuff we may have already put into place. We
 1473          * will be called again to queue it later.
 1474          */
 1475         for (; cnt > 0; cnt--) {
 1476                 if (--frag == -1)
frag = HME_TX_RING_SIZE - 1;
sd = &sc->sc_txd[frag];
bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0,
sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmatag, sd->sd_map);
sd->sd_loaded = 0;
sd->sd_mbuf = NULL;
 1484         }
 1485         return (ENOBUFS);
 1486 }
 1488 int
hme_newbuf(sc, d, freeit)
 1490         struct hme_softc *sc;
 1491         struct hme_sxd *d;
 1492         int freeit;
 1493 {
 1494         struct mbuf *m;
bus_dmamap_t map;
 1497         /*
 1498          * All operations should be on local variables and/or rx spare map
 1499          * until we're sure everything is a success.
 1500          */
MGETHDR(m, M_DONTWAIT, MT_DATA);
 1503         if (m == NULL)
 1504                 return (ENOBUFS);
m->m_pkthdr.rcvif = &sc->sc_arpcom.ac_if;
MCLGET(m, M_DONTWAIT);
 1508         if ((m->m_flags & M_EXT) == 0) {
m_freem(m);
 1510                 return (ENOBUFS);
 1511         }
 1513         if (bus_dmamap_load(sc->sc_dmatag, sc->sc_rxmap_spare,
mtod(m, caddr_t), MCLBYTES - HME_RX_OFFSET, NULL,
BUS_DMA_NOWAIT) != 0) {
m_freem(m);
 1517                 return (ENOBUFS);
 1518         }
 1520         /*
 1521          * At this point we have a new buffer loaded into the spare map.
 1522          * Just need to clear out the old mbuf/map and put the new one
 1523          * in place.
 1524          */
 1526         if (d->sd_loaded) {
bus_dmamap_sync(sc->sc_dmatag, d->sd_map,
 1528                     0, d->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->sc_dmatag, d->sd_map);
d->sd_loaded = 0;
 1531         }
 1533         if ((d->sd_mbuf != NULL) && freeit) {
m_freem(d->sd_mbuf);
d->sd_mbuf = NULL;
 1536         }
map = d->sd_map;
d->sd_map = sc->sc_rxmap_spare;
sc->sc_rxmap_spare = map;
d->sd_loaded = 1;
bus_dmamap_sync(sc->sc_dmatag, d->sd_map, 0, d->sd_map->dm_mapsize,
BUS_DMASYNC_PREREAD);
m->m_data += HME_RX_OFFSET;
d->sd_mbuf = m;
 1549         return (0);
 1550 }