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34 #ifndef _BNX_H_DEFINED
35 #define _BNX_H_DEFINED
36
37 #ifdef _KERNEL
38 #include "bpfilter.h"
39 #include "vlan.h"
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/sockio.h>
44 #include <sys/mbuf.h>
45 #include <sys/malloc.h>
46 #include <sys/kernel.h>
47 #include <sys/device.h>
48 #include <sys/socket.h>
49 #include <sys/timeout.h>
50
51 #include <net/if.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54
55 #ifdef INET
56 #include <netinet/in.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/in_var.h>
59 #include <netinet/ip.h>
60 #include <netinet/if_ether.h>
61 #endif
62
63 #if NVLAN > 0
64 #include <net/if_types.h>
65 #include <net/if_vlan_var.h>
66 #endif
67
68 #if NBPFILTER > 0
69 #include <net/bpf.h>
70 #endif
71
72 #include <dev/pci/pcireg.h>
73 #include <dev/pci/pcivar.h>
74 #include <dev/pci/pcidevs.h>
75
76 #include <dev/mii/mii.h>
77 #include <dev/mii/miivar.h>
78 #include <dev/mii/miidevs.h>
79 #include <dev/mii/brgphyreg.h>
80
81
82
83
84 #define BNX_CP_LOAD 0x00000001
85 #define BNX_CP_SEND 0x00000002
86 #define BNX_CP_RECV 0x00000004
87 #define BNX_CP_INTR 0x00000008
88 #define BNX_CP_UNLOAD 0x00000010
89 #define BNX_CP_RESET 0x00000020
90 #define BNX_CP_ALL 0x00FFFFFF
91
92 #define BNX_CP_MASK 0x00FFFFFF
93
94 #define BNX_LEVEL_FATAL 0x00000000
95 #define BNX_LEVEL_WARN 0x01000000
96 #define BNX_LEVEL_INFO 0x02000000
97 #define BNX_LEVEL_VERBOSE 0x03000000
98 #define BNX_LEVEL_EXCESSIVE 0x04000000
99
100 #define BNX_LEVEL_MASK 0xFF000000
101
102 #define BNX_WARN_LOAD (BNX_CP_LOAD | BNX_LEVEL_WARN)
103 #define BNX_INFO_LOAD (BNX_CP_LOAD | BNX_LEVEL_INFO)
104 #define BNX_VERBOSE_LOAD (BNX_CP_LOAD | BNX_LEVEL_VERBOSE)
105 #define BNX_EXCESSIVE_LOAD (BNX_CP_LOAD | BNX_LEVEL_EXCESSIVE)
106
107 #define BNX_WARN_SEND (BNX_CP_SEND | BNX_LEVEL_WARN)
108 #define BNX_INFO_SEND (BNX_CP_SEND | BNX_LEVEL_INFO)
109 #define BNX_VERBOSE_SEND (BNX_CP_SEND | BNX_LEVEL_VERBOSE)
110 #define BNX_EXCESSIVE_SEND (BNX_CP_SEND | BNX_LEVEL_EXCESSIVE)
111
112 #define BNX_WARN_RECV (BNX_CP_RECV | BNX_LEVEL_WARN)
113 #define BNX_INFO_RECV (BNX_CP_RECV | BNX_LEVEL_INFO)
114 #define BNX_VERBOSE_RECV (BNX_CP_RECV | BNX_LEVEL_VERBOSE)
115 #define BNX_EXCESSIVE_RECV (BNX_CP_RECV | BNX_LEVEL_EXCESSIVE)
116
117 #define BNX_WARN_INTR (BNX_CP_INTR | BNX_LEVEL_WARN)
118 #define BNX_INFO_INTR (BNX_CP_INTR | BNX_LEVEL_INFO)
119 #define BNX_VERBOSE_INTR (BNX_CP_INTR | BNX_LEVEL_VERBOSE)
120 #define BNX_EXCESSIVE_INTR (BNX_CP_INTR | BNX_LEVEL_EXCESSIVE)
121
122 #define BNX_WARN_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_WARN)
123 #define BNX_INFO_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_INFO)
124 #define BNX_VERBOSE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_VERBOSE)
125 #define BNX_EXCESSIVE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_EXCESSIVE)
126
127 #define BNX_WARN_RESET (BNX_CP_RESET | BNX_LEVEL_WARN)
128 #define BNX_INFO_RESET (BNX_CP_RESET | BNX_LEVEL_INFO)
129 #define BNX_VERBOSE_RESET (BNX_CP_RESET | BNX_LEVEL_VERBOSE)
130 #define BNX_EXCESSIVE_RESET (BNX_CP_RESET | BNX_LEVEL_EXCESSIVE)
131
132 #define BNX_FATAL (BNX_CP_ALL | BNX_LEVEL_FATAL)
133 #define BNX_WARN (BNX_CP_ALL | BNX_LEVEL_WARN)
134 #define BNX_INFO (BNX_CP_ALL | BNX_LEVEL_INFO)
135 #define BNX_VERBOSE (BNX_CP_ALL | BNX_LEVEL_VERBOSE)
136 #define BNX_EXCESSIVE (BNX_CP_ALL | BNX_LEVEL_EXCESSIVE)
137
138 #define BNX_CODE_PATH(cp) ((cp & BNX_CP_MASK) & bnx_debug)
139 #define BNX_MSG_LEVEL(lv) ((lv & BNX_LEVEL_MASK) <= (bnx_debug & BNX_LEVEL_MASK))
140 #define BNX_LOG_MSG(m) (BNX_CODE_PATH(m) && BNX_MSG_LEVEL(m))
141
142 #ifdef BNX_DEBUG
143
144
145 #define DBPRINT(sc, level, format, args...) \
146 if (BNX_LOG_MSG(level)) { \
147 printf("%s: " format, sc->bnx_dev.dv_xname, ## args); \
148 }
149
150
151 #define DBRUN(m, args...) \
152 if (BNX_LOG_MSG(m)) { \
153 args; \
154 }
155
156
157 #define DBRUNLV(level, args...) \
158 if (BNX_MSG_LEVEL(level)) { \
159 args; \
160 }
161
162
163 #define DBRUNCP(cp, args...) \
164 if (BNX_CODE_PATH(cp)) { \
165 args; \
166 }
167
168
169 #define DBRUNIF(cond, args...) \
170 if (cond) { \
171 args; \
172 }
173 #if 0
174
175 #include <sys/random.h>
176 #endif
177
178
179 #define DB_RANDOMFALSE(defects) (random() > defects)
180 #define DB_OR_RANDOMFALSE(defects) || (random() > defects)
181 #define DB_AND_RANDOMFALSE(defects) && (random() > ddfects)
182
183
184 #define DB_RANDOMTRUE(defects) (random() < defects)
185 #define DB_OR_RANDOMTRUE(defects) || (random() < defects)
186 #define DB_AND_RANDOMTRUE(defects) && (random() < defects)
187
188 #else
189
190 #define DBPRINT(level, format, args...)
191 #define DBRUN(m, args...)
192 #define DBRUNLV(level, args...)
193 #define DBRUNCP(cp, args...)
194 #define DBRUNIF(cond, args...)
195 #define DB_RANDOMFALSE(defects)
196 #define DB_OR_RANDOMFALSE(percent)
197 #define DB_AND_RANDOMFALSE(percent)
198 #define DB_RANDOMTRUE(defects)
199 #define DB_OR_RANDOMTRUE(percent)
200 #define DB_AND_RANDOMTRUE(percent)
201
202 #endif
203
204
205
206
207
208 #define BRCM_VENDORID 0x14E4
209 #define BRCM_DEVICEID_BCM5706 0x164A
210 #define BRCM_DEVICEID_BCM5706S 0x16AA
211 #define BRCM_DEVICEID_BCM5708 0x164C
212 #define BRCM_DEVICEID_BCM5708S 0x16AC
213
214 #define HP_VENDORID 0x103C
215
216 #define PCI_ANY_ID (u_int16_t) (~0U)
217
218
219
220 #define BNX_CHIP_NUM(sc) (((sc)->bnx_chipid) & 0xffff0000)
221 #define BNX_CHIP_NUM_5706 0x57060000
222 #define BNX_CHIP_NUM_5708 0x57080000
223
224 #define BNX_CHIP_REV(sc) (((sc)->bnx_chipid) & 0x0000f000)
225 #define BNX_CHIP_REV_Ax 0x00000000
226 #define BNX_CHIP_REV_Bx 0x00001000
227 #define BNX_CHIP_REV_Cx 0x00002000
228
229 #define BNX_CHIP_METAL(sc) (((sc)->bnx_chipid) & 0x00000ff0)
230 #define BNX_CHIP_BOND(bp) (((sc)->bnx_chipid) & 0x0000000f)
231
232 #define BNX_CHIP_ID(sc) (((sc)->bnx_chipid) & 0xfffffff0)
233 #define BNX_CHIP_ID_5706_A0 0x57060000
234 #define BNX_CHIP_ID_5706_A1 0x57060010
235 #define BNX_CHIP_ID_5706_A2 0x57060020
236 #define BNX_CHIP_ID_5708_A0 0x57080000
237 #define BNX_CHIP_ID_5708_B0 0x57081000
238 #define BNX_CHIP_ID_5708_B1 0x57081010
239
240 #define BNX_CHIP_BOND_ID(sc) (((sc)->bnx_chipid) & 0xf)
241
242
243 #define BNX_CHIP_BOND_ID_SERDES_BIT 0x01
244
245
246
247 #define BNX_ASICREV(x) ((x) >> 28)
248 #define BNX_ASICREV_BCM5700 0x06
249
250
251 #define BNX_CHIPREV(x) ((x) >> 24)
252 #define BNX_CHIPREV_5700_AX 0x70
253 #define BNX_CHIPREV_5700_BX 0x71
254 #define BNX_CHIPREV_5700_CX 0x72
255 #define BNX_CHIPREV_5701_AX 0x00
256
257 struct bnx_type {
258 u_int16_t bnx_vid;
259 u_int16_t bnx_did;
260 u_int16_t bnx_svid;
261 u_int16_t bnx_sdid;
262 char *bnx_name;
263 };
264
265
266
267
268 #define bnx_htobe16(x) htobe16(x)
269 #define bnx_htobe32(x) htobe32(x)
270 #define bnx_htobe64(x) htobe64(x)
271 #define bnx_htole16(x) htole16(x)
272 #define bnx_htole32(x) htole32(x)
273 #define bnx_htole64(x) htole64(x)
274
275 #define bnx_be16toh(x) betoh16(x)
276 #define bnx_be32toh(x) betoh32(x)
277 #define bnx_be64toh(x) betoh64(x)
278 #define bnx_le16toh(x) letoh16(x)
279 #define bnx_le32toh(x) letoh32(x)
280 #define bnx_le64toh(x) letoh64(x)
281
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283
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285
286
287
288 #define SEEPROM_PAGE_BITS 2
289 #define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS)
290 #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1)
291 #define SEEPROM_PAGE_SIZE 4
292 #define SEEPROM_TOTAL_SIZE 65536
293
294 #define BUFFERED_FLASH_PAGE_BITS 9
295 #define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS)
296 #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
297 #define BUFFERED_FLASH_PAGE_SIZE 264
298 #define BUFFERED_FLASH_TOTAL_SIZE 0x21000
299
300 #define SAIFUN_FLASH_PAGE_BITS 8
301 #define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS)
302 #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
303 #define SAIFUN_FLASH_PAGE_SIZE 256
304 #define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
305
306 #define ST_MICRO_FLASH_PAGE_BITS 8
307 #define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS)
308 #define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
309 #define ST_MICRO_FLASH_PAGE_SIZE 256
310 #define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536
311
312 #define NVRAM_TIMEOUT_COUNT 30000
313 #define BNX_FLASHDESC_MAX 64
314
315 #define FLASH_STRAP_MASK (BNX_NVM_CFG1_FLASH_MODE | \
316 BNX_NVM_CFG1_BUFFER_MODE | \
317 BNX_NVM_CFG1_PROTECT_MODE | \
318 BNX_NVM_CFG1_FLASH_SIZE)
319
320 #define FLASH_BACKUP_STRAP_MASK (0xf << 26)
321
322 struct flash_spec {
323 u_int32_t strapping;
324 u_int32_t config1;
325 u_int32_t config2;
326 u_int32_t config3;
327 u_int32_t write1;
328 u_int32_t buffered;
329 u_int32_t page_bits;
330 u_int32_t page_size;
331 u_int32_t addr_mask;
332 u_int32_t total_size;
333 u_int8_t *name;
334 };
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346
347
348 #define DRV_PULSE_PERIOD_MS 250
349
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355
356
357 #define FW_ACK_TIME_OUT_MS 100
358
359
360 #define BNX_DRV_RESET_SIGNATURE 0x00000000
361 #define BNX_DRV_RESET_SIGNATURE_MAGIC 0x4841564b
362
363 #define BNX_DRV_MB 0x00000004
364 #define BNX_DRV_MSG_CODE 0xff000000
365 #define BNX_DRV_MSG_CODE_RESET 0x01000000
366 #define BNX_DRV_MSG_CODE_UNLOAD 0x02000000
367 #define BNX_DRV_MSG_CODE_SHUTDOWN 0x03000000
368 #define BNX_DRV_MSG_CODE_SUSPEND_WOL 0x04000000
369 #define BNX_DRV_MSG_CODE_FW_TIMEOUT 0x05000000
370 #define BNX_DRV_MSG_CODE_PULSE 0x06000000
371 #define BNX_DRV_MSG_CODE_DIAG 0x07000000
372 #define BNX_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
373
374 #define BNX_DRV_MSG_DATA 0x00ff0000
375 #define BNX_DRV_MSG_DATA_WAIT0 0x00010000
376 #define BNX_DRV_MSG_DATA_WAIT1 0x00020000
377 #define BNX_DRV_MSG_DATA_WAIT2 0x00030000
378 #define BNX_DRV_MSG_DATA_WAIT3 0x00040000
379
380 #define BNX_DRV_MSG_SEQ 0x0000ffff
381
382 #define BNX_FW_MB 0x00000008
383 #define BNX_FW_MSG_ACK 0x0000ffff
384 #define BNX_FW_MSG_STATUS_MASK 0x00ff0000
385 #define BNX_FW_MSG_STATUS_OK 0x00000000
386 #define BNX_FW_MSG_STATUS_FAILURE 0x00ff0000
387
388 #define BNX_LINK_STATUS 0x0000000c
389 #define BNX_LINK_STATUS_INIT_VALUE 0xffffffff
390 #define BNX_LINK_STATUS_LINK_UP 0x1
391 #define BNX_LINK_STATUS_LINK_DOWN 0x0
392 #define BNX_LINK_STATUS_SPEED_MASK 0x1e
393 #define BNX_LINK_STATUS_AN_INCOMPLETE (0<<1)
394 #define BNX_LINK_STATUS_10HALF (1<<1)
395 #define BNX_LINK_STATUS_10FULL (2<<1)
396 #define BNX_LINK_STATUS_100HALF (3<<1)
397 #define BNX_LINK_STATUS_100BASE_T4 (4<<1)
398 #define BNX_LINK_STATUS_100FULL (5<<1)
399 #define BNX_LINK_STATUS_1000HALF (6<<1)
400 #define BNX_LINK_STATUS_1000FULL (7<<1)
401 #define BNX_LINK_STATUS_2500HALF (8<<1)
402 #define BNX_LINK_STATUS_2500FULL (9<<1)
403 #define BNX_LINK_STATUS_AN_ENABLED (1<<5)
404 #define BNX_LINK_STATUS_AN_COMPLETE (1<<6)
405 #define BNX_LINK_STATUS_PARALLEL_DET (1<<7)
406 #define BNX_LINK_STATUS_RESERVED (1<<8)
407 #define BNX_LINK_STATUS_PARTNER_AD_1000FULL (1<<9)
408 #define BNX_LINK_STATUS_PARTNER_AD_1000HALF (1<<10)
409 #define BNX_LINK_STATUS_PARTNER_AD_100BT4 (1<<11)
410 #define BNX_LINK_STATUS_PARTNER_AD_100FULL (1<<12)
411 #define BNX_LINK_STATUS_PARTNER_AD_100HALF (1<<13)
412 #define BNX_LINK_STATUS_PARTNER_AD_10FULL (1<<14)
413 #define BNX_LINK_STATUS_PARTNER_AD_10HALF (1<<15)
414 #define BNX_LINK_STATUS_TX_FC_ENABLED (1<<16)
415 #define BNX_LINK_STATUS_RX_FC_ENABLED (1<<17)
416 #define BNX_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18)
417 #define BNX_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19)
418 #define BNX_LINK_STATUS_SERDES_LINK (1<<20)
419 #define BNX_LINK_STATUS_PARTNER_AD_2500FULL (1<<21)
420 #define BNX_LINK_STATUS_PARTNER_AD_2500HALF (1<<22)
421
422 #define BNX_DRV_PULSE_MB 0x00000010
423 #define BNX_DRV_PULSE_SEQ_MASK 0x00007fff
424
425
426
427
428 #define BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000
429
430 #define BNX_DEV_INFO_SIGNATURE 0x00000020
431 #define BNX_DEV_INFO_SIGNATURE_MAGIC 0x44564900
432 #define BNX_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00
433 #define BNX_DEV_INFO_FEATURE_CFG_VALID 0x01
434 #define BNX_DEV_INFO_SECONDARY_PORT 0x80
435 #define BNX_DEV_INFO_DRV_ALWAYS_ALIVE 0x40
436
437 #define BNX_SHARED_HW_CFG_PART_NUM 0x00000024
438
439 #define BNX_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034
440 #define BNX_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000
441 #define BNX_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000
442 #define BNX_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00
443 #define BNX_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff
444
445 #define BNX_SHARED_HW_CFG_POWER_CONSUMED 0x00000038
446 #define BNX_SHARED_HW_CFG_CONFIG 0x0000003c
447 #define BNX_SHARED_HW_CFG_DESIGN_NIC 0
448 #define BNX_SHARED_HW_CFG_DESIGN_LOM 0x1
449 #define BNX_SHARED_HW_CFG_PHY_COPPER 0
450 #define BNX_SHARED_HW_CFG_PHY_FIBER 0x2
451 #define BNX_SHARED_HW_CFG_PHY_2_5G 0x20
452 #define BNX_SHARED_HW_CFG_PHY_BACKPLANE 0x40
453 #define BNX_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8
454 #define BNX_SHARED_HW_CFG_LED_MODE_MASK 0x300
455 #define BNX_SHARED_HW_CFG_LED_MODE_MAC 0
456 #define BNX_SHARED_HW_CFG_LED_MODE_GPHY1 0x100
457 #define BNX_SHARED_HW_CFG_LED_MODE_GPHY2 0x200
458
459 #define BNX_SHARED_HW_CFG_CONFIG2 0x00000040
460 #define BNX_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000
461
462 #define BNX_DEV_INFO_BC_REV 0x0000004c
463
464 #define BNX_PORT_HW_CFG_MAC_UPPER 0x00000050
465 #define BNX_PORT_HW_CFG_UPPERMAC_MASK 0xffff
466
467 #define BNX_PORT_HW_CFG_MAC_LOWER 0x00000054
468 #define BNX_PORT_HW_CFG_CONFIG 0x00000058
469 #define BNX_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff
470 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000
471 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000
472 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000
473 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000
474
475 #define BNX_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
476 #define BNX_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
477 #define BNX_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070
478 #define BNX_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074
479 #define BNX_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078
480 #define BNX_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c
481
482 #define BNX_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4
483
484 #define BNX_DEV_INFO_FORMAT_REV 0x000000c4
485 #define BNX_DEV_INFO_FORMAT_REV_MASK 0xff000000
486 #define BNX_DEV_INFO_FORMAT_REV_ID ('A' << 24)
487
488 #define BNX_SHARED_FEATURE 0x000000c8
489 #define BNX_SHARED_FEATURE_MASK 0xffffffff
490
491 #define BNX_PORT_FEATURE 0x000000d8
492 #define BNX_PORT2_FEATURE 0x00000014c
493 #define BNX_PORT_FEATURE_WOL_ENABLED 0x01000000
494 #define BNX_PORT_FEATURE_MBA_ENABLED 0x02000000
495 #define BNX_PORT_FEATURE_ASF_ENABLED 0x04000000
496 #define BNX_PORT_FEATURE_IMD_ENABLED 0x08000000
497 #define BNX_PORT_FEATURE_BAR1_SIZE_MASK 0xf
498 #define BNX_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0
499 #define BNX_PORT_FEATURE_BAR1_SIZE_64K 0x1
500 #define BNX_PORT_FEATURE_BAR1_SIZE_128K 0x2
501 #define BNX_PORT_FEATURE_BAR1_SIZE_256K 0x3
502 #define BNX_PORT_FEATURE_BAR1_SIZE_512K 0x4
503 #define BNX_PORT_FEATURE_BAR1_SIZE_1M 0x5
504 #define BNX_PORT_FEATURE_BAR1_SIZE_2M 0x6
505 #define BNX_PORT_FEATURE_BAR1_SIZE_4M 0x7
506 #define BNX_PORT_FEATURE_BAR1_SIZE_8M 0x8
507 #define BNX_PORT_FEATURE_BAR1_SIZE_16M 0x9
508 #define BNX_PORT_FEATURE_BAR1_SIZE_32M 0xa
509 #define BNX_PORT_FEATURE_BAR1_SIZE_64M 0xb
510 #define BNX_PORT_FEATURE_BAR1_SIZE_128M 0xc
511 #define BNX_PORT_FEATURE_BAR1_SIZE_256M 0xd
512 #define BNX_PORT_FEATURE_BAR1_SIZE_512M 0xe
513 #define BNX_PORT_FEATURE_BAR1_SIZE_1G 0xf
514
515 #define BNX_PORT_FEATURE_WOL 0xdc
516 #define BNX_PORT2_FEATURE_WOL 0x150
517 #define BNX_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4
518 #define BNX_PORT_FEATURE_WOL_DEFAULT_MASK 0x30
519 #define BNX_PORT_FEATURE_WOL_DEFAULT_DISABLE 0
520 #define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10
521 #define BNX_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20
522 #define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30
523 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf
524 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0
525 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1
526 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2
527 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
528 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
529 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5
530 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6
531 #define BNX_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40
532 #define BNX_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
533 #define BNX_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800
534
535 #define BNX_PORT_FEATURE_MBA 0xe0
536 #define BNX_PORT2_FEATURE_MBA 0x154
537 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0
538 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3
539 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0
540 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1
541 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2
542 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2
543 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c
544 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0
545 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4
546 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8
547 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc
548 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10
549 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
550 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
551 #define BNX_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
552 #define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0
553 #define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80
554 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8
555 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00
556 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0
557 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100
558 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200
559 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300
560 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400
561 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500
562 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600
563 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700
564 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800
565 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900
566 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00
567 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00
568 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00
569 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00
570 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00
571 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00
572 #define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16
573 #define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000
574 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20
575 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000
576 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0
577 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000
578 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000
579 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000
580
581 #define BNX_PORT_FEATURE_IMD 0xe4
582 #define BNX_PORT2_FEATURE_IMD 0x158
583 #define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0
584 #define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1
585
586 #define BNX_PORT_FEATURE_VLAN 0xe8
587 #define BNX_PORT2_FEATURE_VLAN 0x15c
588 #define BNX_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff
589 #define BNX_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000
590
591 #define BNX_BC_STATE_RESET_TYPE 0x000001c0
592 #define BNX_BC_STATE_RESET_TYPE_SIG 0x00005254
593 #define BNX_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff
594 #define BNX_BC_STATE_RESET_TYPE_NONE (BNX_BC_STATE_RESET_TYPE_SIG | \
595 0x00010000)
596 #define BNX_BC_STATE_RESET_TYPE_PCI (BNX_BC_STATE_RESET_TYPE_SIG | \
597 0x00020000)
598 #define BNX_BC_STATE_RESET_TYPE_VAUX (BNX_BC_STATE_RESET_TYPE_SIG | \
599 0x00030000)
600 #define BNX_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE
601 #define BNX_BC_STATE_RESET_TYPE_DRV_RESET (BNX_BC_STATE_RESET_TYPE_SIG | \
602 DRV_MSG_CODE_RESET)
603 #define BNX_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX_BC_STATE_RESET_TYPE_SIG | \
604 DRV_MSG_CODE_UNLOAD)
605 #define BNX_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX_BC_STATE_RESET_TYPE_SIG | \
606 DRV_MSG_CODE_SHUTDOWN)
607 #define BNX_BC_STATE_RESET_TYPE_DRV_WOL (BNX_BC_STATE_RESET_TYPE_SIG | \
608 DRV_MSG_CODE_WOL)
609 #define BNX_BC_STATE_RESET_TYPE_DRV_DIAG (BNX_BC_STATE_RESET_TYPE_SIG | \
610 DRV_MSG_CODE_DIAG)
611 #define BNX_BC_STATE_RESET_TYPE_VALUE(msg) (BNX_BC_STATE_RESET_TYPE_SIG | \
612 (msg))
613
614 #define BNX_BC_STATE 0x000001c4
615 #define BNX_BC_STATE_ERR_MASK 0x0000ff00
616 #define BNX_BC_STATE_SIGN 0x42530000
617 #define BNX_BC_STATE_SIGN_MASK 0xffff0000
618 #define BNX_BC_STATE_BC1_START (BNX_BC_STATE_SIGN | 0x1)
619 #define BNX_BC_STATE_GET_NVM_CFG1 (BNX_BC_STATE_SIGN | 0x2)
620 #define BNX_BC_STATE_PROG_BAR (BNX_BC_STATE_SIGN | 0x3)
621 #define BNX_BC_STATE_INIT_VID (BNX_BC_STATE_SIGN | 0x4)
622 #define BNX_BC_STATE_GET_NVM_CFG2 (BNX_BC_STATE_SIGN | 0x5)
623 #define BNX_BC_STATE_APPLY_WKARND (BNX_BC_STATE_SIGN | 0x6)
624 #define BNX_BC_STATE_LOAD_BC2 (BNX_BC_STATE_SIGN | 0x7)
625 #define BNX_BC_STATE_GOING_BC2 (BNX_BC_STATE_SIGN | 0x8)
626 #define BNX_BC_STATE_GOING_DIAG (BNX_BC_STATE_SIGN | 0x9)
627 #define BNX_BC_STATE_RT_FINAL_INIT (BNX_BC_STATE_SIGN | 0x81)
628 #define BNX_BC_STATE_RT_WKARND (BNX_BC_STATE_SIGN | 0x82)
629 #define BNX_BC_STATE_RT_DRV_PULSE (BNX_BC_STATE_SIGN | 0x83)
630 #define BNX_BC_STATE_RT_FIOEVTS (BNX_BC_STATE_SIGN | 0x84)
631 #define BNX_BC_STATE_RT_DRV_CMD (BNX_BC_STATE_SIGN | 0x85)
632 #define BNX_BC_STATE_RT_LOW_POWER (BNX_BC_STATE_SIGN | 0x86)
633 #define BNX_BC_STATE_RT_SET_WOL (BNX_BC_STATE_SIGN | 0x87)
634 #define BNX_BC_STATE_RT_OTHER_FW (BNX_BC_STATE_SIGN | 0x88)
635 #define BNX_BC_STATE_RT_GOING_D3 (BNX_BC_STATE_SIGN | 0x89)
636 #define BNX_BC_STATE_ERR_BAD_VERSION (BNX_BC_STATE_SIGN | 0x0100)
637 #define BNX_BC_STATE_ERR_BAD_BC2_CRC (BNX_BC_STATE_SIGN | 0x0200)
638 #define BNX_BC_STATE_ERR_BC1_LOOP (BNX_BC_STATE_SIGN | 0x0300)
639 #define BNX_BC_STATE_ERR_UNKNOWN_CMD (BNX_BC_STATE_SIGN | 0x0400)
640 #define BNX_BC_STATE_ERR_DRV_DEAD (BNX_BC_STATE_SIGN | 0x0500)
641 #define BNX_BC_STATE_ERR_NO_RXP (BNX_BC_STATE_SIGN | 0x0600)
642 #define BNX_BC_STATE_ERR_TOO_MANY_RBUF (BNX_BC_STATE_SIGN | 0x0700)
643
644 #define BNX_BC_STATE_DEBUG_CMD 0x1dc
645 #define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000
646 #define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000
647 #define BNX_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff
648 #define BNX_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff
649
650 #define HOST_VIEW_SHMEM_BASE 0x167c00
651
652
653
654
655 #define BNX_PCI_BAR0 0x10
656 #define BNX_PCI_PCIX_CMD 0x42
657
658
659
660
661 #define BNX_PRINTF(sc, fmt, args...) printf("%s: " fmt, sc->bnx_dev.dv_xname, ##args)
662
663 #define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)
664 #define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val)
665 #define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)
666 #define REG_RD_IND(sc, offset) bnx_reg_rd_ind(sc, offset)
667 #define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val)
668 #define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val)
669 #define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
670 #define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
671 #define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x)))
672 #define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x)))
673
674 #define BNX_STATS(x) (u_long) stats->stat_ ## x ## _lo
675
676
677
678
679
680
681
682
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685
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689
690
691 struct tx_bd {
692 u_int32_t tx_bd_haddr_hi;
693 u_int32_t tx_bd_haddr_lo;
694 u_int32_t tx_bd_mss_nbytes;
695 u_int16_t tx_bd_flags;
696 u_int16_t tx_bd_vlan_tag;
697 #define TX_BD_FLAGS_CONN_FAULT (1<<0)
698 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1)
699 #define TX_BD_FLAGS_IP_CKSUM (1<<2)
700 #define TX_BD_FLAGS_VLAN_TAG (1<<3)
701 #define TX_BD_FLAGS_COAL_NOW (1<<4)
702 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5)
703 #define TX_BD_FLAGS_END (1<<6)
704 #define TX_BD_FLAGS_START (1<<7)
705 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
706 #define TX_BD_FLAGS_SW_FLAGS (1<<13)
707 #define TX_BD_FLAGS_SW_SNAP (1<<14)
708 #define TX_BD_FLAGS_SW_LSO (1<<15)
709
710 };
711
712
713
714
715
716 struct rx_bd {
717 u_int32_t rx_bd_haddr_hi;
718 u_int32_t rx_bd_haddr_lo;
719 u_int32_t rx_bd_len;
720 u_int32_t rx_bd_flags;
721 #define RX_BD_FLAGS_NOPUSH (1<<0)
722 #define RX_BD_FLAGS_DUMMY (1<<1)
723 #define RX_BD_FLAGS_END (1<<2)
724 #define RX_BD_FLAGS_START (1<<3)
725
726 };
727
728
729
730
731
732 struct status_block {
733 u_int32_t status_attn_bits;
734 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
735 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
736 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
737 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
738 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
739 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
740 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
741 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
742 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
743 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
744 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
745 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
746 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
747 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
748 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
749 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
750 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
751 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
752 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
753 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
754 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
755 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
756 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
757 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
758 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
759 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
760 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
761 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
762 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
763
764 u_int32_t status_attn_bits_ack;
765 #if BYTE_ORDER == BIG_ENDIAN
766 u_int16_t status_tx_quick_consumer_index0;
767 u_int16_t status_tx_quick_consumer_index1;
768 u_int16_t status_tx_quick_consumer_index2;
769 u_int16_t status_tx_quick_consumer_index3;
770 u_int16_t status_rx_quick_consumer_index0;
771 u_int16_t status_rx_quick_consumer_index1;
772 u_int16_t status_rx_quick_consumer_index2;
773 u_int16_t status_rx_quick_consumer_index3;
774 u_int16_t status_rx_quick_consumer_index4;
775 u_int16_t status_rx_quick_consumer_index5;
776 u_int16_t status_rx_quick_consumer_index6;
777 u_int16_t status_rx_quick_consumer_index7;
778 u_int16_t status_rx_quick_consumer_index8;
779 u_int16_t status_rx_quick_consumer_index9;
780 u_int16_t status_rx_quick_consumer_index10;
781 u_int16_t status_rx_quick_consumer_index11;
782 u_int16_t status_rx_quick_consumer_index12;
783 u_int16_t status_rx_quick_consumer_index13;
784 u_int16_t status_rx_quick_consumer_index14;
785 u_int16_t status_rx_quick_consumer_index15;
786 u_int16_t status_completion_producer_index;
787 u_int16_t status_cmd_consumer_index;
788 u_int16_t status_idx;
789 u_int16_t status_unused;
790 #elif BYTE_ORDER == LITTLE_ENDIAN
791 u_int16_t status_tx_quick_consumer_index1;
792 u_int16_t status_tx_quick_consumer_index0;
793 u_int16_t status_tx_quick_consumer_index3;
794 u_int16_t status_tx_quick_consumer_index2;
795 u_int16_t status_rx_quick_consumer_index1;
796 u_int16_t status_rx_quick_consumer_index0;
797 u_int16_t status_rx_quick_consumer_index3;
798 u_int16_t status_rx_quick_consumer_index2;
799 u_int16_t status_rx_quick_consumer_index5;
800 u_int16_t status_rx_quick_consumer_index4;
801 u_int16_t status_rx_quick_consumer_index7;
802 u_int16_t status_rx_quick_consumer_index6;
803 u_int16_t status_rx_quick_consumer_index9;
804 u_int16_t status_rx_quick_consumer_index8;
805 u_int16_t status_rx_quick_consumer_index11;
806 u_int16_t status_rx_quick_consumer_index10;
807 u_int16_t status_rx_quick_consumer_index13;
808 u_int16_t status_rx_quick_consumer_index12;
809 u_int16_t status_rx_quick_consumer_index15;
810 u_int16_t status_rx_quick_consumer_index14;
811 u_int16_t status_cmd_consumer_index;
812 u_int16_t status_completion_producer_index;
813 u_int16_t status_unused;
814 u_int16_t status_idx;
815 #endif
816 };
817
818
819
820
821
822 struct statistics_block {
823 u_int32_t stat_IfHCInOctets_hi;
824 u_int32_t stat_IfHCInOctets_lo;
825 u_int32_t stat_IfHCInBadOctets_hi;
826 u_int32_t stat_IfHCInBadOctets_lo;
827 u_int32_t stat_IfHCOutOctets_hi;
828 u_int32_t stat_IfHCOutOctets_lo;
829 u_int32_t stat_IfHCOutBadOctets_hi;
830 u_int32_t stat_IfHCOutBadOctets_lo;
831 u_int32_t stat_IfHCInUcastPkts_hi;
832 u_int32_t stat_IfHCInUcastPkts_lo;
833 u_int32_t stat_IfHCInMulticastPkts_hi;
834 u_int32_t stat_IfHCInMulticastPkts_lo;
835 u_int32_t stat_IfHCInBroadcastPkts_hi;
836 u_int32_t stat_IfHCInBroadcastPkts_lo;
837 u_int32_t stat_IfHCOutUcastPkts_hi;
838 u_int32_t stat_IfHCOutUcastPkts_lo;
839 u_int32_t stat_IfHCOutMulticastPkts_hi;
840 u_int32_t stat_IfHCOutMulticastPkts_lo;
841 u_int32_t stat_IfHCOutBroadcastPkts_hi;
842 u_int32_t stat_IfHCOutBroadcastPkts_lo;
843 u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
844 u_int32_t stat_Dot3StatsCarrierSenseErrors;
845 u_int32_t stat_Dot3StatsFCSErrors;
846 u_int32_t stat_Dot3StatsAlignmentErrors;
847 u_int32_t stat_Dot3StatsSingleCollisionFrames;
848 u_int32_t stat_Dot3StatsMultipleCollisionFrames;
849 u_int32_t stat_Dot3StatsDeferredTransmissions;
850 u_int32_t stat_Dot3StatsExcessiveCollisions;
851 u_int32_t stat_Dot3StatsLateCollisions;
852 u_int32_t stat_EtherStatsCollisions;
853 u_int32_t stat_EtherStatsFragments;
854 u_int32_t stat_EtherStatsJabbers;
855 u_int32_t stat_EtherStatsUndersizePkts;
856 u_int32_t stat_EtherStatsOverrsizePkts;
857 u_int32_t stat_EtherStatsPktsRx64Octets;
858 u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets;
859 u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets;
860 u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets;
861 u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets;
862 u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets;
863 u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets;
864 u_int32_t stat_EtherStatsPktsTx64Octets;
865 u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets;
866 u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets;
867 u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets;
868 u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets;
869 u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets;
870 u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets;
871 u_int32_t stat_XonPauseFramesReceived;
872 u_int32_t stat_XoffPauseFramesReceived;
873 u_int32_t stat_OutXonSent;
874 u_int32_t stat_OutXoffSent;
875 u_int32_t stat_FlowControlDone;
876 u_int32_t stat_MacControlFramesReceived;
877 u_int32_t stat_XoffStateEntered;
878 u_int32_t stat_IfInFramesL2FilterDiscards;
879 u_int32_t stat_IfInRuleCheckerDiscards;
880 u_int32_t stat_IfInFTQDiscards;
881 u_int32_t stat_IfInMBUFDiscards;
882 u_int32_t stat_IfInRuleCheckerP4Hit;
883 u_int32_t stat_CatchupInRuleCheckerDiscards;
884 u_int32_t stat_CatchupInFTQDiscards;
885 u_int32_t stat_CatchupInMBUFDiscards;
886 u_int32_t stat_CatchupInRuleCheckerP4Hit;
887 u_int32_t stat_GenStat00;
888 u_int32_t stat_GenStat01;
889 u_int32_t stat_GenStat02;
890 u_int32_t stat_GenStat03;
891 u_int32_t stat_GenStat04;
892 u_int32_t stat_GenStat05;
893 u_int32_t stat_GenStat06;
894 u_int32_t stat_GenStat07;
895 u_int32_t stat_GenStat08;
896 u_int32_t stat_GenStat09;
897 u_int32_t stat_GenStat10;
898 u_int32_t stat_GenStat11;
899 u_int32_t stat_GenStat12;
900 u_int32_t stat_GenStat13;
901 u_int32_t stat_GenStat14;
902 u_int32_t stat_GenStat15;
903 };
904
905
906
907
908
909 struct l2_fhdr {
910 u_int32_t l2_fhdr_status;
911 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
912 #define L2_FHDR_STATUS_RULE_P2 (1<<3)
913 #define L2_FHDR_STATUS_RULE_P3 (1<<4)
914 #define L2_FHDR_STATUS_RULE_P4 (1<<5)
915 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
916 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
917 #define L2_FHDR_STATUS_RSS_HASH (1<<8)
918 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
919 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
920 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
921
922 #define L2_FHDR_ERRORS_BAD_CRC (1<<17)
923 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18)
924 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19)
925 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20)
926 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21)
927 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28)
928 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31)
929
930 u_int32_t l2_fhdr_hash;
931 #if BYTE_ORDER == BIG_ENDIAN
932 u_int16_t l2_fhdr_pkt_len;
933 u_int16_t l2_fhdr_vlan_tag;
934 u_int16_t l2_fhdr_ip_xsum;
935 u_int16_t l2_fhdr_tcp_udp_xsum;
936 #elif BYTE_ORDER == LITTLE_ENDIAN
937 u_int16_t l2_fhdr_vlan_tag;
938 u_int16_t l2_fhdr_pkt_len;
939 u_int16_t l2_fhdr_tcp_udp_xsum;
940 u_int16_t l2_fhdr_ip_xsum;
941 #endif
942 };
943
944
945
946
947
948 #define BNX_L2CTX_TYPE 0x00000000
949 #define BNX_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
950 #define BNX_L2CTX_TYPE_TYPE (0xf<<28)
951 #define BNX_L2CTX_TYPE_TYPE_EMPTY (0<<28)
952 #define BNX_L2CTX_TYPE_TYPE_L2 (1<<28)
953
954 #define BNX_L2CTX_TX_HOST_BIDX 0x00000088
955 #define BNX_L2CTX_EST_NBD 0x00000088
956 #define BNX_L2CTX_CMD_TYPE 0x00000088
957 #define BNX_L2CTX_CMD_TYPE_TYPE (0xf<<24)
958 #define BNX_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
959 #define BNX_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
960
961 #define BNX_L2CTX_TX_HOST_BSEQ 0x00000090
962 #define BNX_L2CTX_TSCH_BSEQ 0x00000094
963 #define BNX_L2CTX_TBDR_BSEQ 0x00000098
964 #define BNX_L2CTX_TBDR_BOFF 0x0000009c
965 #define BNX_L2CTX_TBDR_BIDX 0x0000009c
966 #define BNX_L2CTX_TBDR_BHADDR_HI 0x000000a0
967 #define BNX_L2CTX_TBDR_BHADDR_LO 0x000000a4
968 #define BNX_L2CTX_TXP_BOFF 0x000000a8
969 #define BNX_L2CTX_TXP_BIDX 0x000000a8
970 #define BNX_L2CTX_TXP_BSEQ 0x000000ac
971
972
973
974
975
976 #define BNX_L2CTX_BD_PRE_READ 0x00000000
977 #define BNX_L2CTX_CTX_SIZE 0x00000000
978 #define BNX_L2CTX_CTX_TYPE 0x00000000
979 #define BNX_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
980 #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
981 #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
982 #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
983
984 #define BNX_L2CTX_HOST_BDIDX 0x00000004
985 #define BNX_L2CTX_HOST_BSEQ 0x00000008
986 #define BNX_L2CTX_NX_BSEQ 0x0000000c
987 #define BNX_L2CTX_NX_BDHADDR_HI 0x00000010
988 #define BNX_L2CTX_NX_BDHADDR_LO 0x00000014
989 #define BNX_L2CTX_NX_BDIDX 0x00000018
990
991
992
993
994
995
996 #define BNX_PCICFG_MISC_CONFIG 0x00000068
997 #define BNX_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
998 #define BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
999 #define BNX_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
1000 #define BNX_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
1001 #define BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
1002 #define BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
1003 #define BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
1004 #define BNX_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
1005 #define BNX_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
1006 #define BNX_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
1007 #define BNX_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16)
1008
1009 #define BNX_PCICFG_MISC_STATUS 0x0000006c
1010 #define BNX_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
1011 #define BNX_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
1012 #define BNX_PCICFG_MISC_STATUS_M66EN (1L<<2)
1013 #define BNX_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
1014 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4)
1015 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
1016 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
1017 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
1018 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
1019
1020 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
1021 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
1022 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
1023 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
1024 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
1025 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
1026 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
1027 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
1028 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
1029 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
1030 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
1031 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
1032 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
1033 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
1034 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
1035 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
1036 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
1037 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
1038 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
1039 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
1040 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1041 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
1042 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
1043 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
1044 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
1045 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
1046 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
1047 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
1048 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
1049 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
1050
1051 #define BNX_PCICFG_REG_WINDOW_ADDRESS 0x00000078
1052 #define BNX_PCICFG_REG_WINDOW 0x00000080
1053 #define BNX_PCICFG_INT_ACK_CMD 0x00000084
1054 #define BNX_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
1055 #define BNX_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
1056 #define BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
1057 #define BNX_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
1058
1059 #define BNX_PCICFG_STATUS_BIT_SET_CMD 0x00000088
1060 #define BNX_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
1061 #define BNX_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
1062 #define BNX_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
1063
1064
1065
1066
1067
1068
1069 #define BNX_PCI_GRC_WINDOW_ADDR 0x00000400
1070 #define BNX_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8)
1071
1072 #define BNX_PCI_CONFIG_1 0x00000404
1073 #define BNX_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
1074 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
1075 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
1076 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
1077 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
1078 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
1079 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
1080 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
1081 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
1082 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11)
1083 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
1084 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
1085 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
1086 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
1087 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
1088 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
1089 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
1090 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
1091
1092 #define BNX_PCI_CONFIG_2 0x00000408
1093 #define BNX_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
1094 #define BNX_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
1095 #define BNX_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
1096 #define BNX_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
1097 #define BNX_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
1098 #define BNX_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
1099 #define BNX_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
1100 #define BNX_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
1101 #define BNX_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
1102 #define BNX_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
1103 #define BNX_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
1104 #define BNX_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
1105 #define BNX_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
1106 #define BNX_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
1107 #define BNX_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
1108 #define BNX_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
1109 #define BNX_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
1110 #define BNX_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
1111 #define BNX_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
1112 #define BNX_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
1113 #define BNX_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
1114 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
1115 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
1116 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
1117 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
1118 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
1119 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
1120 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
1121 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
1122 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
1123 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
1124 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
1125 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
1126 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
1127 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
1128 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
1129 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
1130 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
1131 #define BNX_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16)
1132 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21)
1133 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
1134 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
1135 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
1136 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
1137 #define BNX_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
1138 #define BNX_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
1139 #define BNX_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
1140
1141 #define BNX_PCI_CONFIG_3 0x0000040c
1142 #define BNX_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
1143 #define BNX_PCI_CONFIG_3_FORCE_PME (1L<<24)
1144 #define BNX_PCI_CONFIG_3_PME_STATUS (1L<<25)
1145 #define BNX_PCI_CONFIG_3_PME_ENABLE (1L<<26)
1146 #define BNX_PCI_CONFIG_3_PM_STATE (0x3L<<27)
1147 #define BNX_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
1148 #define BNX_PCI_CONFIG_3_PCI_POWER (1L<<31)
1149
1150 #define BNX_PCI_PM_DATA_A 0x00000410
1151 #define BNX_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0)
1152 #define BNX_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8)
1153 #define BNX_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16)
1154 #define BNX_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24)
1155
1156 #define BNX_PCI_PM_DATA_B 0x00000414
1157 #define BNX_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0)
1158 #define BNX_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8)
1159 #define BNX_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16)
1160 #define BNX_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24)
1161
1162 #define BNX_PCI_SWAP_DIAG0 0x00000418
1163 #define BNX_PCI_SWAP_DIAG1 0x0000041c
1164 #define BNX_PCI_EXP_ROM_ADDR 0x00000420
1165 #define BNX_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2)
1166 #define BNX_PCI_EXP_ROM_ADDR_REQ (1L<<31)
1167
1168 #define BNX_PCI_EXP_ROM_DATA 0x00000424
1169 #define BNX_PCI_VPD_INTF 0x00000428
1170 #define BNX_PCI_VPD_INTF_INTF_REQ (1L<<0)
1171
1172 #define BNX_PCI_VPD_ADDR_FLAG 0x0000042c
1173 #define BNX_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2)
1174 #define BNX_PCI_VPD_ADDR_FLAG_WR (1<<15)
1175
1176 #define BNX_PCI_VPD_DATA 0x00000430
1177 #define BNX_PCI_ID_VAL1 0x00000434
1178 #define BNX_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0)
1179 #define BNX_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16)
1180
1181 #define BNX_PCI_ID_VAL2 0x00000438
1182 #define BNX_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0)
1183 #define BNX_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16)
1184
1185 #define BNX_PCI_ID_VAL3 0x0000043c
1186 #define BNX_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0)
1187 #define BNX_PCI_ID_VAL3_REVISION_ID (0xffL<<24)
1188
1189 #define BNX_PCI_ID_VAL4 0x00000440
1190 #define BNX_PCI_ID_VAL4_CAP_ENA (0xfL<<0)
1191 #define BNX_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
1192 #define BNX_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
1193 #define BNX_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
1194 #define BNX_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
1195 #define BNX_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
1196 #define BNX_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
1197 #define BNX_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
1198 #define BNX_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
1199 #define BNX_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
1200 #define BNX_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
1201 #define BNX_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
1202 #define BNX_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
1203 #define BNX_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
1204 #define BNX_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
1205 #define BNX_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
1206 #define BNX_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
1207 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
1208 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
1209 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
1210 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
1211 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
1212 #define BNX_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
1213 #define BNX_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12)
1214 #define BNX_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
1215 #define BNX_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
1216 #define BNX_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
1217 #define BNX_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21)
1218 #define BNX_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23)
1219 #define BNX_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26)
1220
1221 #define BNX_PCI_ID_VAL5 0x00000444
1222 #define BNX_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
1223 #define BNX_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
1224 #define BNX_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
1225 #define BNX_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
1226 #define BNX_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
1227 #define BNX_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
1228
1229 #define BNX_PCI_PCIX_EXTENDED_STATUS 0x00000448
1230 #define BNX_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
1231 #define BNX_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
1232 #define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16)
1233 #define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24)
1234
1235 #define BNX_PCI_ID_VAL6 0x0000044c
1236 #define BNX_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
1237 #define BNX_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
1238 #define BNX_PCI_ID_VAL6_BIST (0xffL<<16)
1239
1240 #define BNX_PCI_MSI_DATA 0x00000450
1241 #define BNX_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0)
1242
1243 #define BNX_PCI_MSI_ADDR_H 0x00000454
1244 #define BNX_PCI_MSI_ADDR_L 0x00000458
1245
1246
1247
1248
1249
1250
1251 #define BNX_MISC_COMMAND 0x00000800
1252 #define BNX_MISC_COMMAND_ENABLE_ALL (1L<<0)
1253 #define BNX_MISC_COMMAND_DISABLE_ALL (1L<<1)
1254 #define BNX_MISC_COMMAND_CORE_RESET (1L<<4)
1255 #define BNX_MISC_COMMAND_HARD_RESET (1L<<5)
1256 #define BNX_MISC_COMMAND_PAR_ERROR (1L<<8)
1257 #define BNX_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
1258
1259 #define BNX_MISC_CFG 0x00000804
1260 #define BNX_MISC_CFG_PCI_GRC_TMOUT (1L<<0)
1261 #define BNX_MISC_CFG_NVM_WR_EN (0x3L<<1)
1262 #define BNX_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
1263 #define BNX_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
1264 #define BNX_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
1265 #define BNX_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
1266 #define BNX_MISC_CFG_BIST_EN (1L<<3)
1267 #define BNX_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
1268 #define BNX_MISC_CFG_BYPASS_BSCAN (1L<<5)
1269 #define BNX_MISC_CFG_BYPASS_EJTAG (1L<<6)
1270 #define BNX_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
1271 #define BNX_MISC_CFG_LEDMODE (0x3L<<8)
1272 #define BNX_MISC_CFG_LEDMODE_MAC (0L<<8)
1273 #define BNX_MISC_CFG_LEDMODE_GPHY1 (1L<<8)
1274 #define BNX_MISC_CFG_LEDMODE_GPHY2 (2L<<8)
1275
1276 #define BNX_MISC_ID 0x00000808
1277 #define BNX_MISC_ID_BOND_ID (0xfL<<0)
1278 #define BNX_MISC_ID_CHIP_METAL (0xffL<<4)
1279 #define BNX_MISC_ID_CHIP_REV (0xfL<<12)
1280 #define BNX_MISC_ID_CHIP_NUM (0xffffL<<16)
1281
1282 #define BNX_MISC_ENABLE_STATUS_BITS 0x0000080c
1283 #define BNX_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1284 #define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
1285 #define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1286 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1287 #define BNX_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
1288 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
1289 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1290 #define BNX_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1291 #define BNX_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1292 #define BNX_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
1293 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1294 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1295 #define BNX_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
1296 #define BNX_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
1297 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1298 #define BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
1299 #define BNX_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1300 #define BNX_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
1301 #define BNX_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
1302 #define BNX_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
1303 #define BNX_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1304 #define BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
1305 #define BNX_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1306 #define BNX_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1307 #define BNX_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1308 #define BNX_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
1309 #define BNX_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
1310 #define BNX_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
1311
1312 #define BNX_MISC_ENABLE_SET_BITS 0x00000810
1313 #define BNX_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1314 #define BNX_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
1315 #define BNX_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1316 #define BNX_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1317 #define BNX_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
1318 #define BNX_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
1319 #define BNX_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1320 #define BNX_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1321 #define BNX_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1322 #define BNX_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
1323 #define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1324 #define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1325 #define BNX_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
1326 #define BNX_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
1327 #define BNX_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1328 #define BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
1329 #define BNX_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1330 #define BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
1331 #define BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
1332 #define BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
1333 #define BNX_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1334 #define BNX_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
1335 #define BNX_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1336 #define BNX_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1337 #define BNX_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1338 #define BNX_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
1339 #define BNX_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
1340 #define BNX_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
1341
1342 #define BNX_MISC_ENABLE_CLR_BITS 0x00000814
1343 #define BNX_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1344 #define BNX_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
1345 #define BNX_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1346 #define BNX_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1347 #define BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
1348 #define BNX_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
1349 #define BNX_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1350 #define BNX_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1351 #define BNX_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1352 #define BNX_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
1353 #define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1354 #define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1355 #define BNX_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
1356 #define BNX_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
1357 #define BNX_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1358 #define BNX_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
1359 #define BNX_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1360 #define BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
1361 #define BNX_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
1362 #define BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
1363 #define BNX_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1364 #define BNX_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
1365 #define BNX_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1366 #define BNX_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1367 #define BNX_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1368 #define BNX_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
1369 #define BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
1370 #define BNX_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
1371
1372 #define BNX_MISC_CLOCK_CONTROL_BITS 0x00000818
1373 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
1374 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
1375 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
1376 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
1377 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
1378 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
1379 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
1380 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
1381 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
1382 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
1383 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
1384 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
1385 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
1386 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
1387 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
1388 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
1389 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
1390 #define BNX_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
1391 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
1392 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1393 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
1394 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
1395 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
1396 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
1397 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
1398 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
1399 #define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
1400 #define BNX_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
1401 #define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
1402
1403 #define BNX_MISC_GPIO 0x0000081c
1404 #define BNX_MISC_GPIO_VALUE (0xffL<<0)
1405 #define BNX_MISC_GPIO_SET (0xffL<<8)
1406 #define BNX_MISC_GPIO_CLR (0xffL<<16)
1407 #define BNX_MISC_GPIO_FLOAT (0xffL<<24)
1408
1409 #define BNX_MISC_GPIO_INT 0x00000820
1410 #define BNX_MISC_GPIO_INT_INT_STATE (0xfL<<0)
1411 #define BNX_MISC_GPIO_INT_OLD_VALUE (0xfL<<8)
1412 #define BNX_MISC_GPIO_INT_OLD_SET (0xfL<<16)
1413 #define BNX_MISC_GPIO_INT_OLD_CLR (0xfL<<24)
1414
1415 #define BNX_MISC_CONFIG_LFSR 0x00000824
1416 #define BNX_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
1417
1418 #define BNX_MISC_LFSR_MASK_BITS 0x00000828
1419 #define BNX_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1420 #define BNX_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
1421 #define BNX_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1422 #define BNX_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1423 #define BNX_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
1424 #define BNX_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
1425 #define BNX_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1426 #define BNX_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1427 #define BNX_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1428 #define BNX_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
1429 #define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1430 #define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1431 #define BNX_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
1432 #define BNX_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
1433 #define BNX_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1434 #define BNX_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
1435 #define BNX_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1436 #define BNX_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
1437 #define BNX_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
1438 #define BNX_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
1439 #define BNX_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1440 #define BNX_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
1441 #define BNX_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1442 #define BNX_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1443 #define BNX_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1444 #define BNX_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
1445 #define BNX_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
1446 #define BNX_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
1447
1448 #define BNX_MISC_ARB_REQ0 0x0000082c
1449 #define BNX_MISC_ARB_REQ1 0x00000830
1450 #define BNX_MISC_ARB_REQ2 0x00000834
1451 #define BNX_MISC_ARB_REQ3 0x00000838
1452 #define BNX_MISC_ARB_REQ4 0x0000083c
1453 #define BNX_MISC_ARB_FREE0 0x00000840
1454 #define BNX_MISC_ARB_FREE1 0x00000844
1455 #define BNX_MISC_ARB_FREE2 0x00000848
1456 #define BNX_MISC_ARB_FREE3 0x0000084c
1457 #define BNX_MISC_ARB_FREE4 0x00000850
1458 #define BNX_MISC_ARB_REQ_STATUS0 0x00000854
1459 #define BNX_MISC_ARB_REQ_STATUS1 0x00000858
1460 #define BNX_MISC_ARB_REQ_STATUS2 0x0000085c
1461 #define BNX_MISC_ARB_REQ_STATUS3 0x00000860
1462 #define BNX_MISC_ARB_REQ_STATUS4 0x00000864
1463 #define BNX_MISC_ARB_GNT0 0x00000868
1464 #define BNX_MISC_ARB_GNT0_0 (0x7L<<0)
1465 #define BNX_MISC_ARB_GNT0_1 (0x7L<<4)
1466 #define BNX_MISC_ARB_GNT0_2 (0x7L<<8)
1467 #define BNX_MISC_ARB_GNT0_3 (0x7L<<12)
1468 #define BNX_MISC_ARB_GNT0_4 (0x7L<<16)
1469 #define BNX_MISC_ARB_GNT0_5 (0x7L<<20)
1470 #define BNX_MISC_ARB_GNT0_6 (0x7L<<24)
1471 #define BNX_MISC_ARB_GNT0_7 (0x7L<<28)
1472
1473 #define BNX_MISC_ARB_GNT1 0x0000086c
1474 #define BNX_MISC_ARB_GNT1_8 (0x7L<<0)
1475 #define BNX_MISC_ARB_GNT1_9 (0x7L<<4)
1476 #define BNX_MISC_ARB_GNT1_10 (0x7L<<8)
1477 #define BNX_MISC_ARB_GNT1_11 (0x7L<<12)
1478 #define BNX_MISC_ARB_GNT1_12 (0x7L<<16)
1479 #define BNX_MISC_ARB_GNT1_13 (0x7L<<20)
1480 #define BNX_MISC_ARB_GNT1_14 (0x7L<<24)
1481 #define BNX_MISC_ARB_GNT1_15 (0x7L<<28)
1482
1483 #define BNX_MISC_ARB_GNT2 0x00000870
1484 #define BNX_MISC_ARB_GNT2_16 (0x7L<<0)
1485 #define BNX_MISC_ARB_GNT2_17 (0x7L<<4)
1486 #define BNX_MISC_ARB_GNT2_18 (0x7L<<8)
1487 #define BNX_MISC_ARB_GNT2_19 (0x7L<<12)
1488 #define BNX_MISC_ARB_GNT2_20 (0x7L<<16)
1489 #define BNX_MISC_ARB_GNT2_21 (0x7L<<20)
1490 #define BNX_MISC_ARB_GNT2_22 (0x7L<<24)
1491 #define BNX_MISC_ARB_GNT2_23 (0x7L<<28)
1492
1493 #define BNX_MISC_ARB_GNT3 0x00000874
1494 #define BNX_MISC_ARB_GNT3_24 (0x7L<<0)
1495 #define BNX_MISC_ARB_GNT3_25 (0x7L<<4)
1496 #define BNX_MISC_ARB_GNT3_26 (0x7L<<8)
1497 #define BNX_MISC_ARB_GNT3_27 (0x7L<<12)
1498 #define BNX_MISC_ARB_GNT3_28 (0x7L<<16)
1499 #define BNX_MISC_ARB_GNT3_29 (0x7L<<20)
1500 #define BNX_MISC_ARB_GNT3_30 (0x7L<<24)
1501 #define BNX_MISC_ARB_GNT3_31 (0x7L<<28)
1502
1503 #define BNX_MISC_PRBS_CONTROL 0x00000878
1504 #define BNX_MISC_PRBS_CONTROL_EN (1L<<0)
1505 #define BNX_MISC_PRBS_CONTROL_RSTB (1L<<1)
1506 #define BNX_MISC_PRBS_CONTROL_INV (1L<<2)
1507 #define BNX_MISC_PRBS_CONTROL_ERR_CLR (1L<<3)
1508 #define BNX_MISC_PRBS_CONTROL_ORDER (0x3L<<4)
1509 #define BNX_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4)
1510 #define BNX_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4)
1511 #define BNX_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4)
1512 #define BNX_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4)
1513
1514 #define BNX_MISC_PRBS_STATUS 0x0000087c
1515 #define BNX_MISC_PRBS_STATUS_LOCK (1L<<0)
1516 #define BNX_MISC_PRBS_STATUS_STKY (1L<<1)
1517 #define BNX_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2)
1518 #define BNX_MISC_PRBS_STATUS_STATE (0xfL<<16)
1519
1520 #define BNX_MISC_SM_ASF_CONTROL 0x00000880
1521 #define BNX_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
1522 #define BNX_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
1523 #define BNX_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
1524 #define BNX_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
1525 #define BNX_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
1526 #define BNX_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
1527 #define BNX_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
1528 #define BNX_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
1529 #define BNX_MISC_SM_ASF_CONTROL_RES (0xfL<<8)
1530 #define BNX_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
1531 #define BNX_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
1532 #define BNX_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
1533 #define BNX_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
1534 #define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16)
1535 #define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24)
1536 #define BNX_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
1537 #define BNX_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
1538
1539 #define BNX_MISC_SMB_IN 0x00000884
1540 #define BNX_MISC_SMB_IN_DAT_IN (0xffL<<0)
1541 #define BNX_MISC_SMB_IN_RDY (1L<<8)
1542 #define BNX_MISC_SMB_IN_DONE (1L<<9)
1543 #define BNX_MISC_SMB_IN_FIRSTBYTE (1L<<10)
1544 #define BNX_MISC_SMB_IN_STATUS (0x7L<<11)
1545 #define BNX_MISC_SMB_IN_STATUS_OK (0x0L<<11)
1546 #define BNX_MISC_SMB_IN_STATUS_PEC (0x1L<<11)
1547 #define BNX_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11)
1548 #define BNX_MISC_SMB_IN_STATUS_STOP (0x3L<<11)
1549 #define BNX_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11)
1550
1551 #define BNX_MISC_SMB_OUT 0x00000888
1552 #define BNX_MISC_SMB_OUT_DAT_OUT (0xffL<<0)
1553 #define BNX_MISC_SMB_OUT_RDY (1L<<8)
1554 #define BNX_MISC_SMB_OUT_START (1L<<9)
1555 #define BNX_MISC_SMB_OUT_LAST (1L<<10)
1556 #define BNX_MISC_SMB_OUT_ACC_TYPE (1L<<11)
1557 #define BNX_MISC_SMB_OUT_ENB_PEC (1L<<12)
1558 #define BNX_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
1559 #define BNX_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
1560 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
1561 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
1562 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
1563 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
1564 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
1565 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
1566 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
1567 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
1568 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
1569 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20)
1570 #define BNX_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
1571 #define BNX_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
1572 #define BNX_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
1573 #define BNX_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
1574 #define BNX_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
1575
1576 #define BNX_MISC_SMB_WATCHDOG 0x0000088c
1577 #define BNX_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)
1578
1579 #define BNX_MISC_SMB_HEARTBEAT 0x00000890
1580 #define BNX_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0)
1581
1582 #define BNX_MISC_SMB_POLL_ASF 0x00000894
1583 #define BNX_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0)
1584
1585 #define BNX_MISC_SMB_POLL_LEGACY 0x00000898
1586 #define BNX_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
1587
1588 #define BNX_MISC_SMB_RETRAN 0x0000089c
1589 #define BNX_MISC_SMB_RETRAN_RETRAN (0xffL<<0)
1590
1591 #define BNX_MISC_SMB_TIMESTAMP 0x000008a0
1592 #define BNX_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
1593
1594 #define BNX_MISC_PERR_ENA0 0x000008a4
1595 #define BNX_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
1596 #define BNX_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
1597 #define BNX_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
1598 #define BNX_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
1599 #define BNX_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
1600 #define BNX_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
1601 #define BNX_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
1602 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
1603 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
1604 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
1605 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
1606 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
1607 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
1608 #define BNX_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
1609 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
1610 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
1611 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
1612 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
1613 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
1614 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
1615 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
1616 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
1617 #define BNX_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
1618 #define BNX_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
1619 #define BNX_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
1620 #define BNX_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
1621 #define BNX_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
1622 #define BNX_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
1623 #define BNX_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
1624 #define BNX_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
1625 #define BNX_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
1626 #define BNX_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
1627
1628 #define BNX_MISC_PERR_ENA1 0x000008a8
1629 #define BNX_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
1630 #define BNX_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
1631 #define BNX_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
1632 #define BNX_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
1633 #define BNX_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
1634 #define BNX_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
1635 #define BNX_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
1636 #define BNX_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
1637 #define BNX_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
1638 #define BNX_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
1639 #define BNX_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
1640 #define BNX_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
1641 #define BNX_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
1642 #define BNX_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
1643 #define BNX_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
1644 #define BNX_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
1645 #define BNX_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
1646 #define BNX_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
1647 #define BNX_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
1648 #define BNX_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
1649 #define BNX_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
1650 #define BNX_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
1651 #define BNX_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
1652 #define BNX_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
1653 #define BNX_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
1654 #define BNX_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
1655 #define BNX_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
1656 #define BNX_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
1657 #define BNX_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
1658 #define BNX_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
1659 #define BNX_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
1660 #define BNX_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
1661
1662 #define BNX_MISC_PERR_ENA2 0x000008ac
1663 #define BNX_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
1664 #define BNX_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
1665 #define BNX_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
1666 #define BNX_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
1667 #define BNX_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
1668 #define BNX_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
1669 #define BNX_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
1670 #define BNX_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
1671 #define BNX_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
1672
1673 #define BNX_MISC_DEBUG_VECTOR_SEL 0x000008b0
1674 #define BNX_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
1675 #define BNX_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
1676
1677 #define BNX_MISC_VREG_CONTROL 0x000008b4
1678 #define BNX_MISC_VREG_CONTROL_1_2 (0xfL<<0)
1679 #define BNX_MISC_VREG_CONTROL_2_5 (0xfL<<4)
1680
1681 #define BNX_MISC_FINAL_CLK_CTL_VAL 0x000008b8
1682 #define BNX_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
1683
1684 #define BNX_MISC_UNUSED0 0x000008bc
1685
1686
1687
1688
1689
1690
1691 #define BNX_NVM_COMMAND 0x00006400
1692 #define BNX_NVM_COMMAND_RST (1L<<0)
1693 #define BNX_NVM_COMMAND_DONE (1L<<3)
1694 #define BNX_NVM_COMMAND_DOIT (1L<<4)
1695 #define BNX_NVM_COMMAND_WR (1L<<5)
1696 #define BNX_NVM_COMMAND_ERASE (1L<<6)
1697 #define BNX_NVM_COMMAND_FIRST (1L<<7)
1698 #define BNX_NVM_COMMAND_LAST (1L<<8)
1699 #define BNX_NVM_COMMAND_WREN (1L<<16)
1700 #define BNX_NVM_COMMAND_WRDI (1L<<17)
1701 #define BNX_NVM_COMMAND_EWSR (1L<<18)
1702 #define BNX_NVM_COMMAND_WRSR (1L<<19)
1703
1704 #define BNX_NVM_STATUS 0x00006404
1705 #define BNX_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
1706 #define BNX_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
1707 #define BNX_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
1708
1709 #define BNX_NVM_WRITE 0x00006408
1710 #define BNX_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
1711 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
1712 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
1713 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
1714 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
1715 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
1716 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
1717 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
1718
1719 #define BNX_NVM_ADDR 0x0000640c
1720 #define BNX_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
1721 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
1722 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
1723 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
1724 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
1725 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
1726 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
1727 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
1728
1729 #define BNX_NVM_READ 0x00006410
1730 #define BNX_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
1731 #define BNX_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
1732 #define BNX_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
1733 #define BNX_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
1734 #define BNX_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
1735 #define BNX_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
1736 #define BNX_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
1737 #define BNX_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
1738
1739 #define BNX_NVM_CFG1 0x00006414
1740 #define BNX_NVM_CFG1_FLASH_MODE (1L<<0)
1741 #define BNX_NVM_CFG1_BUFFER_MODE (1L<<1)
1742 #define BNX_NVM_CFG1_PASS_MODE (1L<<2)
1743 #define BNX_NVM_CFG1_BITBANG_MODE (1L<<3)
1744 #define BNX_NVM_CFG1_STATUS_BIT (0x7L<<4)
1745 #define BNX_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
1746 #define BNX_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
1747 #define BNX_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
1748 #define BNX_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
1749 #define BNX_NVM_CFG1_PROTECT_MODE (1L<<24)
1750 #define BNX_NVM_CFG1_FLASH_SIZE (1L<<25)
1751 #define BNX_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
1752
1753 #define BNX_NVM_CFG2 0x00006418
1754 #define BNX_NVM_CFG2_ERASE_CMD (0xffL<<0)
1755 #define BNX_NVM_CFG2_DUMMY (0xffL<<8)
1756 #define BNX_NVM_CFG2_STATUS_CMD (0xffL<<16)
1757
1758 #define BNX_NVM_CFG3 0x0000641c
1759 #define BNX_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
1760 #define BNX_NVM_CFG3_WRITE_CMD (0xffL<<8)
1761 #define BNX_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
1762 #define BNX_NVM_CFG3_READ_CMD (0xffL<<24)
1763
1764 #define BNX_NVM_SW_ARB 0x00006420
1765 #define BNX_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
1766 #define BNX_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
1767 #define BNX_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
1768 #define BNX_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
1769 #define BNX_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
1770 #define BNX_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
1771 #define BNX_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
1772 #define BNX_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
1773 #define BNX_NVM_SW_ARB_ARB_ARB0 (1L<<8)
1774 #define BNX_NVM_SW_ARB_ARB_ARB1 (1L<<9)
1775 #define BNX_NVM_SW_ARB_ARB_ARB2 (1L<<10)
1776 #define BNX_NVM_SW_ARB_ARB_ARB3 (1L<<11)
1777 #define BNX_NVM_SW_ARB_REQ0 (1L<<12)
1778 #define BNX_NVM_SW_ARB_REQ1 (1L<<13)
1779 #define BNX_NVM_SW_ARB_REQ2 (1L<<14)
1780 #define BNX_NVM_SW_ARB_REQ3 (1L<<15)
1781
1782 #define BNX_NVM_ACCESS_ENABLE 0x00006424
1783 #define BNX_NVM_ACCESS_ENABLE_EN (1L<<0)
1784 #define BNX_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
1785
1786 #define BNX_NVM_WRITE1 0x00006428
1787 #define BNX_NVM_WRITE1_WREN_CMD (0xffL<<0)
1788 #define BNX_NVM_WRITE1_WRDI_CMD (0xffL<<8)
1789 #define BNX_NVM_WRITE1_SR_DATA (0xffL<<16)
1790
1791
1792
1793
1794
1795
1796
1797 #define BNX_DMA_COMMAND 0x00000c00
1798 #define BNX_DMA_COMMAND_ENABLE (1L<<0)
1799
1800 #define BNX_DMA_STATUS 0x00000c04
1801 #define BNX_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
1802 #define BNX_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
1803 #define BNX_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
1804 #define BNX_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
1805 #define BNX_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
1806 #define BNX_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
1807 #define BNX_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
1808 #define BNX_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
1809 #define BNX_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
1810 #define BNX_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
1811 #define BNX_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
1812
1813 #define BNX_DMA_CONFIG 0x00000c08
1814 #define BNX_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
1815 #define BNX_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
1816 #define BNX_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
1817 #define BNX_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
1818 #define BNX_DMA_CONFIG_ONE_DMA (1L<<6)
1819 #define BNX_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
1820 #define BNX_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
1821 #define BNX_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
1822 #define BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
1823 #define BNX_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12)
1824 #define BNX_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16)
1825 #define BNX_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20)
1826 #define BNX_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
1827 #define BNX_DMA_CONFIG_BIG_SIZE (0xfL<<24)
1828 #define BNX_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24)
1829 #define BNX_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24)
1830 #define BNX_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
1831 #define BNX_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
1832 #define BNX_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
1833
1834 #define BNX_DMA_BLACKOUT 0x00000c0c
1835 #define BNX_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
1836 #define BNX_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
1837 #define BNX_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
1838
1839 #define BNX_DMA_RCHAN_STAT 0x00000c30
1840 #define BNX_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1841 #define BNX_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3)
1842 #define BNX_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1843 #define BNX_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7)
1844 #define BNX_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1845 #define BNX_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11)
1846 #define BNX_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1847 #define BNX_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15)
1848 #define BNX_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1849 #define BNX_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19)
1850 #define BNX_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1851 #define BNX_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23)
1852 #define BNX_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1853 #define BNX_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27)
1854 #define BNX_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1855 #define BNX_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31)
1856
1857 #define BNX_DMA_WCHAN_STAT 0x00000c34
1858 #define BNX_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1859 #define BNX_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3)
1860 #define BNX_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1861 #define BNX_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7)
1862 #define BNX_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1863 #define BNX_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11)
1864 #define BNX_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1865 #define BNX_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15)
1866 #define BNX_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1867 #define BNX_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19)
1868 #define BNX_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1869 #define BNX_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23)
1870 #define BNX_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1871 #define BNX_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27)
1872 #define BNX_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1873 #define BNX_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31)
1874
1875 #define BNX_DMA_RCHAN_ASSIGNMENT 0x00000c38
1876 #define BNX_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0)
1877 #define BNX_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4)
1878 #define BNX_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8)
1879 #define BNX_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12)
1880 #define BNX_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16)
1881 #define BNX_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20)
1882 #define BNX_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24)
1883 #define BNX_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28)
1884
1885 #define BNX_DMA_WCHAN_ASSIGNMENT 0x00000c3c
1886 #define BNX_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0)
1887 #define BNX_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4)
1888 #define BNX_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8)
1889 #define BNX_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12)
1890 #define BNX_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16)
1891 #define BNX_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20)
1892 #define BNX_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24)
1893 #define BNX_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28)
1894
1895 #define BNX_DMA_RCHAN_STAT_00 0x00000c40
1896 #define BNX_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
1897
1898 #define BNX_DMA_RCHAN_STAT_01 0x00000c44
1899 #define BNX_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
1900
1901 #define BNX_DMA_RCHAN_STAT_02 0x00000c48
1902 #define BNX_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0)
1903 #define BNX_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16)
1904 #define BNX_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17)
1905 #define BNX_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18)
1906
1907 #define BNX_DMA_RCHAN_STAT_10 0x00000c4c
1908 #define BNX_DMA_RCHAN_STAT_11 0x00000c50
1909 #define BNX_DMA_RCHAN_STAT_12 0x00000c54
1910 #define BNX_DMA_RCHAN_STAT_20 0x00000c58
1911 #define BNX_DMA_RCHAN_STAT_21 0x00000c5c
1912 #define BNX_DMA_RCHAN_STAT_22 0x00000c60
1913 #define BNX_DMA_RCHAN_STAT_30 0x00000c64
1914 #define BNX_DMA_RCHAN_STAT_31 0x00000c68
1915 #define BNX_DMA_RCHAN_STAT_32 0x00000c6c
1916 #define BNX_DMA_RCHAN_STAT_40 0x00000c70
1917 #define BNX_DMA_RCHAN_STAT_41 0x00000c74
1918 #define BNX_DMA_RCHAN_STAT_42 0x00000c78
1919 #define BNX_DMA_RCHAN_STAT_50 0x00000c7c
1920 #define BNX_DMA_RCHAN_STAT_51 0x00000c80
1921 #define BNX_DMA_RCHAN_STAT_52 0x00000c84
1922 #define BNX_DMA_RCHAN_STAT_60 0x00000c88
1923 #define BNX_DMA_RCHAN_STAT_61 0x00000c8c
1924 #define BNX_DMA_RCHAN_STAT_62 0x00000c90
1925 #define BNX_DMA_RCHAN_STAT_70 0x00000c94
1926 #define BNX_DMA_RCHAN_STAT_71 0x00000c98
1927 #define BNX_DMA_RCHAN_STAT_72 0x00000c9c
1928 #define BNX_DMA_WCHAN_STAT_00 0x00000ca0
1929 #define BNX_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
1930
1931 #define BNX_DMA_WCHAN_STAT_01 0x00000ca4
1932 #define BNX_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
1933
1934 #define BNX_DMA_WCHAN_STAT_02 0x00000ca8
1935 #define BNX_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0)
1936 #define BNX_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
1937 #define BNX_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
1938 #define BNX_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
1939
1940 #define BNX_DMA_WCHAN_STAT_10 0x00000cac
1941 #define BNX_DMA_WCHAN_STAT_11 0x00000cb0
1942 #define BNX_DMA_WCHAN_STAT_12 0x00000cb4
1943 #define BNX_DMA_WCHAN_STAT_20 0x00000cb8
1944 #define BNX_DMA_WCHAN_STAT_21 0x00000cbc
1945 #define BNX_DMA_WCHAN_STAT_22 0x00000cc0
1946 #define BNX_DMA_WCHAN_STAT_30 0x00000cc4
1947 #define BNX_DMA_WCHAN_STAT_31 0x00000cc8
1948 #define BNX_DMA_WCHAN_STAT_32 0x00000ccc
1949 #define BNX_DMA_WCHAN_STAT_40 0x00000cd0
1950 #define BNX_DMA_WCHAN_STAT_41 0x00000cd4
1951 #define BNX_DMA_WCHAN_STAT_42 0x00000cd8
1952 #define BNX_DMA_WCHAN_STAT_50 0x00000cdc
1953 #define BNX_DMA_WCHAN_STAT_51 0x00000ce0
1954 #define BNX_DMA_WCHAN_STAT_52 0x00000ce4
1955 #define BNX_DMA_WCHAN_STAT_60 0x00000ce8
1956 #define BNX_DMA_WCHAN_STAT_61 0x00000cec
1957 #define BNX_DMA_WCHAN_STAT_62 0x00000cf0
1958 #define BNX_DMA_WCHAN_STAT_70 0x00000cf4
1959 #define BNX_DMA_WCHAN_STAT_71 0x00000cf8
1960 #define BNX_DMA_WCHAN_STAT_72 0x00000cfc
1961 #define BNX_DMA_ARB_STAT_00 0x00000d00
1962 #define BNX_DMA_ARB_STAT_00_MASTER (0xffffL<<0)
1963 #define BNX_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16)
1964 #define BNX_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24)
1965
1966 #define BNX_DMA_ARB_STAT_01 0x00000d04
1967 #define BNX_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0)
1968 #define BNX_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4)
1969 #define BNX_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8)
1970 #define BNX_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12)
1971 #define BNX_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16)
1972 #define BNX_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20)
1973 #define BNX_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24)
1974 #define BNX_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28)
1975
1976 #define BNX_DMA_FUSE_CTRL0_CMD 0x00000f00
1977 #define BNX_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
1978 #define BNX_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
1979 #define BNX_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
1980 #define BNX_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
1981 #define BNX_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8)
1982
1983 #define BNX_DMA_FUSE_CTRL0_DATA 0x00000f04
1984 #define BNX_DMA_FUSE_CTRL1_CMD 0x00000f08
1985 #define BNX_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
1986 #define BNX_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
1987 #define BNX_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
1988 #define BNX_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
1989 #define BNX_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8)
1990
1991 #define BNX_DMA_FUSE_CTRL1_DATA 0x00000f0c
1992 #define BNX_DMA_FUSE_CTRL2_CMD 0x00000f10
1993 #define BNX_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
1994 #define BNX_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
1995 #define BNX_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
1996 #define BNX_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
1997 #define BNX_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8)
1998
1999 #define BNX_DMA_FUSE_CTRL2_DATA 0x00000f14
2000
2001
2002
2003
2004
2005
2006 #define BNX_CTX_COMMAND 0x00001000
2007 #define BNX_CTX_COMMAND_ENABLED (1L<<0)
2008
2009 #define BNX_CTX_STATUS 0x00001004
2010 #define BNX_CTX_STATUS_LOCK_WAIT (1L<<0)
2011 #define BNX_CTX_STATUS_READ_STAT (1L<<16)
2012 #define BNX_CTX_STATUS_WRITE_STAT (1L<<17)
2013 #define BNX_CTX_STATUS_ACC_STALL_STAT (1L<<18)
2014 #define BNX_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
2015
2016 #define BNX_CTX_VIRT_ADDR 0x00001008
2017 #define BNX_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
2018
2019 #define BNX_CTX_PAGE_TBL 0x0000100c
2020 #define BNX_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
2021
2022 #define BNX_CTX_DATA_ADR 0x00001010
2023 #define BNX_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
2024
2025 #define BNX_CTX_DATA 0x00001014
2026 #define BNX_CTX_LOCK 0x00001018
2027 #define BNX_CTX_LOCK_TYPE (0x7L<<0)
2028 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
2029 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
2030 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
2031 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
2032 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
2033 #define BNX_CTX_LOCK_CID_VALUE (0x3fffL<<7)
2034 #define BNX_CTX_LOCK_GRANTED (1L<<26)
2035 #define BNX_CTX_LOCK_MODE (0x7L<<27)
2036 #define BNX_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
2037 #define BNX_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
2038 #define BNX_CTX_LOCK_MODE_SURE (0x2L<<27)
2039 #define BNX_CTX_LOCK_STATUS (1L<<30)
2040 #define BNX_CTX_LOCK_REQ (1L<<31)
2041
2042 #define BNX_CTX_ACCESS_STATUS 0x00001040
2043 #define BNX_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
2044 #define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
2045 #define BNX_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
2046 #define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
2047 #define BNX_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
2048
2049 #define BNX_CTX_DBG_LOCK_STATUS 0x00001044
2050 #define BNX_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
2051 #define BNX_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
2052
2053 #define BNX_CTX_CHNL_LOCK_STATUS_0 0x00001080
2054 #define BNX_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
2055 #define BNX_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
2056 #define BNX_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
2057
2058 #define BNX_CTX_CHNL_LOCK_STATUS_1 0x00001084
2059 #define BNX_CTX_CHNL_LOCK_STATUS_2 0x00001088
2060 #define BNX_CTX_CHNL_LOCK_STATUS_3 0x0000108c
2061 #define BNX_CTX_CHNL_LOCK_STATUS_4 0x00001090
2062 #define BNX_CTX_CHNL_LOCK_STATUS_5 0x00001094
2063 #define BNX_CTX_CHNL_LOCK_STATUS_6 0x00001098
2064 #define BNX_CTX_CHNL_LOCK_STATUS_7 0x0000109c
2065 #define BNX_CTX_CHNL_LOCK_STATUS_8 0x000010a0
2066
2067
2068
2069
2070
2071
2072 #define BNX_EMAC_MODE 0x00001400
2073 #define BNX_EMAC_MODE_RESET (1L<<0)
2074 #define BNX_EMAC_MODE_HALF_DUPLEX (1L<<1)
2075 #define BNX_EMAC_MODE_PORT (0x3L<<2)
2076 #define BNX_EMAC_MODE_PORT_NONE (0L<<2)
2077 #define BNX_EMAC_MODE_PORT_MII (1L<<2)
2078 #define BNX_EMAC_MODE_PORT_GMII (2L<<2)
2079 #define BNX_EMAC_MODE_PORT_MII_10 (3L<<2)
2080 #define BNX_EMAC_MODE_MAC_LOOP (1L<<4)
2081 #define BNX_EMAC_MODE_25G (1L<<5)
2082 #define BNX_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
2083 #define BNX_EMAC_MODE_TX_BURST (1L<<8)
2084 #define BNX_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
2085 #define BNX_EMAC_MODE_EXT_LINK_POL (1L<<10)
2086 #define BNX_EMAC_MODE_FORCE_LINK (1L<<11)
2087 #define BNX_EMAC_MODE_MPKT (1L<<18)
2088 #define BNX_EMAC_MODE_MPKT_RCVD (1L<<19)
2089 #define BNX_EMAC_MODE_ACPI_RCVD (1L<<20)
2090
2091 #define BNX_EMAC_STATUS 0x00001404
2092 #define BNX_EMAC_STATUS_LINK (1L<<11)
2093 #define BNX_EMAC_STATUS_LINK_CHANGE (1L<<12)
2094 #define BNX_EMAC_STATUS_MI_COMPLETE (1L<<22)
2095 #define BNX_EMAC_STATUS_MI_INT (1L<<23)
2096 #define BNX_EMAC_STATUS_AP_ERROR (1L<<24)
2097 #define BNX_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
2098
2099 #define BNX_EMAC_ATTENTION_ENA 0x00001408
2100 #define BNX_EMAC_ATTENTION_ENA_LINK (1L<<11)
2101 #define BNX_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
2102 #define BNX_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
2103 #define BNX_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
2104
2105 #define BNX_EMAC_LED 0x0000140c
2106 #define BNX_EMAC_LED_OVERRIDE (1L<<0)
2107 #define BNX_EMAC_LED_1000MB_OVERRIDE (1L<<1)
2108 #define BNX_EMAC_LED_100MB_OVERRIDE (1L<<2)
2109 #define BNX_EMAC_LED_10MB_OVERRIDE (1L<<3)
2110 #define BNX_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
2111 #define BNX_EMAC_LED_BLNK_TRAFFIC (1L<<5)
2112 #define BNX_EMAC_LED_TRAFFIC (1L<<6)
2113 #define BNX_EMAC_LED_1000MB (1L<<7)
2114 #define BNX_EMAC_LED_100MB (1L<<8)
2115 #define BNX_EMAC_LED_10MB (1L<<9)
2116 #define BNX_EMAC_LED_TRAFFIC_STAT (1L<<10)
2117 #define BNX_EMAC_LED_BLNK_RATE (0xfffL<<19)
2118 #define BNX_EMAC_LED_BLNK_RATE_ENA (1L<<31)
2119
2120 #define BNX_EMAC_MAC_MATCH0 0x00001410
2121 #define BNX_EMAC_MAC_MATCH1 0x00001414
2122 #define BNX_EMAC_MAC_MATCH2 0x00001418
2123 #define BNX_EMAC_MAC_MATCH3 0x0000141c
2124 #define BNX_EMAC_MAC_MATCH4 0x00001420
2125 #define BNX_EMAC_MAC_MATCH5 0x00001424
2126 #define BNX_EMAC_MAC_MATCH6 0x00001428
2127 #define BNX_EMAC_MAC_MATCH7 0x0000142c
2128 #define BNX_EMAC_MAC_MATCH8 0x00001430
2129 #define BNX_EMAC_MAC_MATCH9 0x00001434
2130 #define BNX_EMAC_MAC_MATCH10 0x00001438
2131 #define BNX_EMAC_MAC_MATCH11 0x0000143c
2132 #define BNX_EMAC_MAC_MATCH12 0x00001440
2133 #define BNX_EMAC_MAC_MATCH13 0x00001444
2134 #define BNX_EMAC_MAC_MATCH14 0x00001448
2135 #define BNX_EMAC_MAC_MATCH15 0x0000144c
2136 #define BNX_EMAC_MAC_MATCH16 0x00001450
2137 #define BNX_EMAC_MAC_MATCH17 0x00001454
2138 #define BNX_EMAC_MAC_MATCH18 0x00001458
2139 #define BNX_EMAC_MAC_MATCH19 0x0000145c
2140 #define BNX_EMAC_MAC_MATCH20 0x00001460
2141 #define BNX_EMAC_MAC_MATCH21 0x00001464
2142 #define BNX_EMAC_MAC_MATCH22 0x00001468
2143 #define BNX_EMAC_MAC_MATCH23 0x0000146c
2144 #define BNX_EMAC_MAC_MATCH24 0x00001470
2145 #define BNX_EMAC_MAC_MATCH25 0x00001474
2146 #define BNX_EMAC_MAC_MATCH26 0x00001478
2147 #define BNX_EMAC_MAC_MATCH27 0x0000147c
2148 #define BNX_EMAC_MAC_MATCH28 0x00001480
2149 #define BNX_EMAC_MAC_MATCH29 0x00001484
2150 #define BNX_EMAC_MAC_MATCH30 0x00001488
2151 #define BNX_EMAC_MAC_MATCH31 0x0000148c
2152 #define BNX_EMAC_BACKOFF_SEED 0x00001498
2153 #define BNX_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
2154
2155 #define BNX_EMAC_RX_MTU_SIZE 0x0000149c
2156 #define BNX_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
2157 #define BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
2158
2159 #define BNX_EMAC_SERDES_CNTL 0x000014a4
2160 #define BNX_EMAC_SERDES_CNTL_RXR (0x7L<<0)
2161 #define BNX_EMAC_SERDES_CNTL_RXG (0x3L<<3)
2162 #define BNX_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
2163 #define BNX_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7)
2164 #define BNX_EMAC_SERDES_CNTL_BGMAX (1L<<10)
2165 #define BNX_EMAC_SERDES_CNTL_BGMIN (1L<<11)
2166 #define BNX_EMAC_SERDES_CNTL_TXMODE (1L<<12)
2167 #define BNX_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
2168 #define BNX_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
2169 #define BNX_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
2170 #define BNX_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
2171 #define BNX_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
2172 #define BNX_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
2173 #define BNX_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
2174 #define BNX_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20)
2175 #define BNX_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22)
2176
2177 #define BNX_EMAC_SERDES_STATUS 0x000014a8
2178 #define BNX_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0)
2179 #define BNX_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
2180
2181 #define BNX_EMAC_MDIO_COMM 0x000014ac
2182 #define BNX_EMAC_MDIO_COMM_DATA (0xffffL<<0)
2183 #define BNX_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
2184 #define BNX_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
2185 #define BNX_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
2186 #define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
2187 #define BNX_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
2188 #define BNX_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
2189 #define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
2190 #define BNX_EMAC_MDIO_COMM_FAIL (1L<<28)
2191 #define BNX_EMAC_MDIO_COMM_START_BUSY (1L<<29)
2192 #define BNX_EMAC_MDIO_COMM_DISEXT (1L<<30)
2193
2194 #define BNX_EMAC_MDIO_STATUS 0x000014b0
2195 #define BNX_EMAC_MDIO_STATUS_LINK (1L<<0)
2196 #define BNX_EMAC_MDIO_STATUS_10MB (1L<<1)
2197
2198 #define BNX_EMAC_MDIO_MODE 0x000014b4
2199 #define BNX_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
2200 #define BNX_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
2201 #define BNX_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
2202 #define BNX_EMAC_MDIO_MODE_MDIO (1L<<9)
2203 #define BNX_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
2204 #define BNX_EMAC_MDIO_MODE_MDC (1L<<11)
2205 #define BNX_EMAC_MDIO_MODE_MDINT (1L<<12)
2206 #define BNX_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
2207
2208 #define BNX_EMAC_MDIO_AUTO_STATUS 0x000014b8
2209 #define BNX_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
2210
2211 #define BNX_EMAC_TX_MODE 0x000014bc
2212 #define BNX_EMAC_TX_MODE_RESET (1L<<0)
2213 #define BNX_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
2214 #define BNX_EMAC_TX_MODE_FLOW_EN (1L<<4)
2215 #define BNX_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
2216 #define BNX_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
2217 #define BNX_EMAC_TX_MODE_LINK_AWARE (1L<<7)
2218
2219 #define BNX_EMAC_TX_STATUS 0x000014c0
2220 #define BNX_EMAC_TX_STATUS_XOFFED (1L<<0)
2221 #define BNX_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
2222 #define BNX_EMAC_TX_STATUS_XON_SENT (1L<<2)
2223 #define BNX_EMAC_TX_STATUS_LINK_UP (1L<<3)
2224 #define BNX_EMAC_TX_STATUS_UNDERRUN (1L<<4)
2225
2226 #define BNX_EMAC_TX_LENGTHS 0x000014c4
2227 #define BNX_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
2228 #define BNX_EMAC_TX_LENGTHS_IPG (0xfL<<8)
2229 #define BNX_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
2230
2231 #define BNX_EMAC_RX_MODE 0x000014c8
2232 #define BNX_EMAC_RX_MODE_RESET (1L<<0)
2233 #define BNX_EMAC_RX_MODE_FLOW_EN (1L<<2)
2234 #define BNX_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
2235 #define BNX_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
2236 #define BNX_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
2237 #define BNX_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
2238 #define BNX_EMAC_RX_MODE_LLC_CHK (1L<<7)
2239 #define BNX_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
2240 #define BNX_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
2241 #define BNX_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
2242 #define BNX_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
2243 #define BNX_EMAC_RX_MODE_SORT_MODE (1L<<12)
2244
2245 #define BNX_EMAC_RX_STATUS 0x000014cc
2246 #define BNX_EMAC_RX_STATUS_FFED (1L<<0)
2247 #define BNX_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
2248 #define BNX_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
2249
2250 #define BNX_EMAC_MULTICAST_HASH0 0x000014d0
2251 #define BNX_EMAC_MULTICAST_HASH1 0x000014d4
2252 #define BNX_EMAC_MULTICAST_HASH2 0x000014d8
2253 #define BNX_EMAC_MULTICAST_HASH3 0x000014dc
2254 #define BNX_EMAC_MULTICAST_HASH4 0x000014e0
2255 #define BNX_EMAC_MULTICAST_HASH5 0x000014e4
2256 #define BNX_EMAC_MULTICAST_HASH6 0x000014e8
2257 #define BNX_EMAC_MULTICAST_HASH7 0x000014ec
2258 #define BNX_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
2259 #define BNX_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
2260 #define BNX_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
2261 #define BNX_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c
2262 #define BNX_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510
2263 #define BNX_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514
2264 #define BNX_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518
2265 #define BNX_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c
2266 #define BNX_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520
2267 #define BNX_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
2268 #define BNX_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528
2269 #define BNX_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c
2270 #define BNX_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530
2271 #define BNX_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
2272 #define BNX_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538
2273 #define BNX_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c
2274 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
2275 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
2276 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548
2277 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
2278 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
2279 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
2280 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558
2281 #define BNX_EMAC_RXMAC_DEBUG0 0x0000155c
2282 #define BNX_EMAC_RXMAC_DEBUG1 0x00001560
2283 #define BNX_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
2284 #define BNX_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
2285 #define BNX_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
2286 #define BNX_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
2287 #define BNX_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
2288 #define BNX_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
2289 #define BNX_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
2290 #define BNX_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
2291 #define BNX_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
2292
2293 #define BNX_EMAC_RXMAC_DEBUG2 0x00001564
2294 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
2295 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0)
2296 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0)
2297 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0)
2298 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0)
2299 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0)
2300 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0)
2301 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0)
2302 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0)
2303 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
2304 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3)
2305 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3)
2306 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3)
2307 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3)
2308 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3)
2309 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3)
2310 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3)
2311 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3)
2312 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3)
2313 #define BNX_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
2314 #define BNX_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
2315 #define BNX_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
2316 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
2317 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
2318 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
2319 #define BNX_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
2320 #define BNX_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
2321
2322 #define BNX_EMAC_RXMAC_DEBUG3 0x00001568
2323 #define BNX_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
2324 #define BNX_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
2325
2326 #define BNX_EMAC_RXMAC_DEBUG4 0x0000156c
2327 #define BNX_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
2328 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
2329 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16)
2330 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
2331 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
2332 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
2333 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
2334 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
2335 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
2336 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
2337 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
2338 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
2339 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16)
2340 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16)
2341 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16)
2342 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16)
2343 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16)
2344 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16)
2345 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16)
2346 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16)
2347 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16)
2348 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16)
2349 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16)
2350 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16)
2351 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16)
2352 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16)
2353 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16)
2354 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16)
2355 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16)
2356 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16)
2357 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16)
2358 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
2359 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16)
2360 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16)
2361 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16)
2362 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16)
2363 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16)
2364 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16)
2365 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16)
2366 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16)
2367 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16)
2368 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16)
2369 #define BNX_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
2370 #define BNX_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
2371 #define BNX_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
2372 #define BNX_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
2373 #define BNX_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26)
2374 #define BNX_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
2375 #define BNX_EMAC_RXMAC_DEBUG4_START (1L<<28)
2376
2377 #define BNX_EMAC_RXMAC_DEBUG5 0x00001570
2378 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
2379 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
2380 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
2381 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
2382 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
2383 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
2384 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
2385 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
2386 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
2387 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4)
2388 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4)
2389 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4)
2390 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4)
2391 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4)
2392 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4)
2393 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4)
2394 #define BNX_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
2395 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
2396 #define BNX_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
2397 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
2398 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
2399 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
2400 #define BNX_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
2401 #define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
2402 #define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
2403 #define BNX_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
2404
2405 #define BNX_EMAC_RX_STAT_AC0 0x00001580
2406 #define BNX_EMAC_RX_STAT_AC1 0x00001584
2407 #define BNX_EMAC_RX_STAT_AC2 0x00001588
2408 #define BNX_EMAC_RX_STAT_AC3 0x0000158c
2409 #define BNX_EMAC_RX_STAT_AC4 0x00001590
2410 #define BNX_EMAC_RX_STAT_AC5 0x00001594
2411 #define BNX_EMAC_RX_STAT_AC6 0x00001598
2412 #define BNX_EMAC_RX_STAT_AC7 0x0000159c
2413 #define BNX_EMAC_RX_STAT_AC8 0x000015a0
2414 #define BNX_EMAC_RX_STAT_AC9 0x000015a4
2415 #define BNX_EMAC_RX_STAT_AC10 0x000015a8
2416 #define BNX_EMAC_RX_STAT_AC11 0x000015ac
2417 #define BNX_EMAC_RX_STAT_AC12 0x000015b0
2418 #define BNX_EMAC_RX_STAT_AC13 0x000015b4
2419 #define BNX_EMAC_RX_STAT_AC14 0x000015b8
2420 #define BNX_EMAC_RX_STAT_AC15 0x000015bc
2421 #define BNX_EMAC_RX_STAT_AC16 0x000015c0
2422 #define BNX_EMAC_RX_STAT_AC17 0x000015c4
2423 #define BNX_EMAC_RX_STAT_AC18 0x000015c8
2424 #define BNX_EMAC_RX_STAT_AC19 0x000015cc
2425 #define BNX_EMAC_RX_STAT_AC20 0x000015d0
2426 #define BNX_EMAC_RX_STAT_AC21 0x000015d4
2427 #define BNX_EMAC_RX_STAT_AC22 0x000015d8
2428 #define BNX_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
2429 #define BNX_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
2430 #define BNX_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
2431 #define BNX_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
2432 #define BNX_EMAC_TX_STAT_OUTXONSENT 0x0000160c
2433 #define BNX_EMAC_TX_STAT_OUTXOFFSENT 0x00001610
2434 #define BNX_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614
2435 #define BNX_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
2436 #define BNX_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c
2437 #define BNX_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
2438 #define BNX_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
2439 #define BNX_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628
2440 #define BNX_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c
2441 #define BNX_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630
2442 #define BNX_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634
2443 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
2444 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
2445 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640
2446 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
2447 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
2448 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
2449 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650
2450 #define BNX_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
2451 #define BNX_EMAC_TXMAC_DEBUG0 0x00001658
2452 #define BNX_EMAC_TXMAC_DEBUG1 0x0000165c
2453 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
2454 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0)
2455 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0)
2456 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0)
2457 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0)
2458 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0)
2459 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0)
2460 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0)
2461 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0)
2462 #define BNX_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
2463 #define BNX_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
2464 #define BNX_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
2465 #define BNX_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
2466 #define BNX_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
2467 #define BNX_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
2468 #define BNX_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
2469 #define BNX_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
2470 #define BNX_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
2471 #define BNX_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
2472
2473 #define BNX_EMAC_TXMAC_DEBUG2 0x00001660
2474 #define BNX_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
2475 #define BNX_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
2476 #define BNX_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
2477 #define BNX_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
2478
2479 #define BNX_EMAC_TXMAC_DEBUG3 0x00001664
2480 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
2481 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0)
2482 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0)
2483 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0)
2484 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0)
2485 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0)
2486 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0)
2487 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0)
2488 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0)
2489 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0)
2490 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0)
2491 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0)
2492 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0)
2493 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0)
2494 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0)
2495 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0)
2496 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
2497 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4)
2498 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4)
2499 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4)
2500 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4)
2501 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4)
2502 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4)
2503 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4)
2504 #define BNX_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
2505 #define BNX_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
2506 #define BNX_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
2507 #define BNX_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
2508
2509 #define BNX_EMAC_TXMAC_DEBUG4 0x00001668
2510 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
2511 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
2512 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
2513 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
2514 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
2515 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
2516 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
2517 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
2518 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
2519 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
2520 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
2521 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
2522 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
2523 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
2524 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
2525 #define BNX_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
2526 #define BNX_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
2527 #define BNX_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
2528 #define BNX_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
2529 #define BNX_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
2530 #define BNX_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
2531 #define BNX_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
2532 #define BNX_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
2533 #define BNX_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
2534 #define BNX_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
2535 #define BNX_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
2536 #define BNX_EMAC_TXMAC_DEBUG4_GO (1L<<31)
2537
2538 #define BNX_EMAC_TX_STAT_AC0 0x00001680
2539 #define BNX_EMAC_TX_STAT_AC1 0x00001684
2540 #define BNX_EMAC_TX_STAT_AC2 0x00001688
2541 #define BNX_EMAC_TX_STAT_AC3 0x0000168c
2542 #define BNX_EMAC_TX_STAT_AC4 0x00001690
2543 #define BNX_EMAC_TX_STAT_AC5 0x00001694
2544 #define BNX_EMAC_TX_STAT_AC6 0x00001698
2545 #define BNX_EMAC_TX_STAT_AC7 0x0000169c
2546 #define BNX_EMAC_TX_STAT_AC8 0x000016a0
2547 #define BNX_EMAC_TX_STAT_AC9 0x000016a4
2548 #define BNX_EMAC_TX_STAT_AC10 0x000016a8
2549 #define BNX_EMAC_TX_STAT_AC11 0x000016ac
2550 #define BNX_EMAC_TX_STAT_AC12 0x000016b0
2551 #define BNX_EMAC_TX_STAT_AC13 0x000016b4
2552 #define BNX_EMAC_TX_STAT_AC14 0x000016b8
2553 #define BNX_EMAC_TX_STAT_AC15 0x000016bc
2554 #define BNX_EMAC_TX_STAT_AC16 0x000016c0
2555 #define BNX_EMAC_TX_STAT_AC17 0x000016c4
2556 #define BNX_EMAC_TX_STAT_AC18 0x000016c8
2557 #define BNX_EMAC_TX_STAT_AC19 0x000016cc
2558 #define BNX_EMAC_TX_STAT_AC20 0x000016d0
2559 #define BNX_EMAC_TX_STAT_AC21 0x000016d4
2560 #define BNX_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
2561
2562
2563
2564
2565
2566
2567 #define BNX_RPM_COMMAND 0x00001800
2568 #define BNX_RPM_COMMAND_ENABLED (1L<<0)
2569 #define BNX_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
2570
2571 #define BNX_RPM_STATUS 0x00001804
2572 #define BNX_RPM_STATUS_MBUF_WAIT (1L<<0)
2573 #define BNX_RPM_STATUS_FREE_WAIT (1L<<1)
2574
2575 #define BNX_RPM_CONFIG 0x00001808
2576 #define BNX_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
2577 #define BNX_RPM_CONFIG_ACPI_ENA (1L<<1)
2578 #define BNX_RPM_CONFIG_ACPI_KEEP (1L<<2)
2579 #define BNX_RPM_CONFIG_MP_KEEP (1L<<3)
2580 #define BNX_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
2581 #define BNX_RPM_CONFIG_IGNORE_VLAN (1L<<31)
2582
2583 #define BNX_RPM_VLAN_MATCH0 0x00001810
2584 #define BNX_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
2585
2586 #define BNX_RPM_VLAN_MATCH1 0x00001814
2587 #define BNX_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
2588
2589 #define BNX_RPM_VLAN_MATCH2 0x00001818
2590 #define BNX_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
2591
2592 #define BNX_RPM_VLAN_MATCH3 0x0000181c
2593 #define BNX_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
2594
2595 #define BNX_RPM_SORT_USER0 0x00001820
2596 #define BNX_RPM_SORT_USER0_PM_EN (0xffffL<<0)
2597 #define BNX_RPM_SORT_USER0_BC_EN (1L<<16)
2598 #define BNX_RPM_SORT_USER0_MC_EN (1L<<17)
2599 #define BNX_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
2600 #define BNX_RPM_SORT_USER0_PROM_EN (1L<<19)
2601 #define BNX_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
2602 #define BNX_RPM_SORT_USER0_PROM_VLAN (1L<<24)
2603 #define BNX_RPM_SORT_USER0_ENA (1L<<31)
2604
2605 #define BNX_RPM_SORT_USER1 0x00001824
2606 #define BNX_RPM_SORT_USER1_PM_EN (0xffffL<<0)
2607 #define BNX_RPM_SORT_USER1_BC_EN (1L<<16)
2608 #define BNX_RPM_SORT_USER1_MC_EN (1L<<17)
2609 #define BNX_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
2610 #define BNX_RPM_SORT_USER1_PROM_EN (1L<<19)
2611 #define BNX_RPM_SORT_USER1_VLAN_EN (0xfL<<20)
2612 #define BNX_RPM_SORT_USER1_PROM_VLAN (1L<<24)
2613 #define BNX_RPM_SORT_USER1_ENA (1L<<31)
2614
2615 #define BNX_RPM_SORT_USER2 0x00001828
2616 #define BNX_RPM_SORT_USER2_PM_EN (0xffffL<<0)
2617 #define BNX_RPM_SORT_USER2_BC_EN (1L<<16)
2618 #define BNX_RPM_SORT_USER2_MC_EN (1L<<17)
2619 #define BNX_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
2620 #define BNX_RPM_SORT_USER2_PROM_EN (1L<<19)
2621 #define BNX_RPM_SORT_USER2_VLAN_EN (0xfL<<20)
2622 #define BNX_RPM_SORT_USER2_PROM_VLAN (1L<<24)
2623 #define BNX_RPM_SORT_USER2_ENA (1L<<31)
2624
2625 #define BNX_RPM_SORT_USER3 0x0000182c
2626 #define BNX_RPM_SORT_USER3_PM_EN (0xffffL<<0)
2627 #define BNX_RPM_SORT_USER3_BC_EN (1L<<16)
2628 #define BNX_RPM_SORT_USER3_MC_EN (1L<<17)
2629 #define BNX_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
2630 #define BNX_RPM_SORT_USER3_PROM_EN (1L<<19)
2631 #define BNX_RPM_SORT_USER3_VLAN_EN (0xfL<<20)
2632 #define BNX_RPM_SORT_USER3_PROM_VLAN (1L<<24)
2633 #define BNX_RPM_SORT_USER3_ENA (1L<<31)
2634
2635 #define BNX_RPM_STAT_L2_FILTER_DISCARDS 0x00001840
2636 #define BNX_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844
2637 #define BNX_RPM_STAT_IFINFTQDISCARDS 0x00001848
2638 #define BNX_RPM_STAT_IFINMBUFDISCARD 0x0000184c
2639 #define BNX_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
2640 #define BNX_RPM_STAT_AC0 0x00001880
2641 #define BNX_RPM_STAT_AC1 0x00001884
2642 #define BNX_RPM_STAT_AC2 0x00001888
2643 #define BNX_RPM_STAT_AC3 0x0000188c
2644 #define BNX_RPM_STAT_AC4 0x00001890
2645 #define BNX_RPM_RC_CNTL_0 0x00001900
2646 #define BNX_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
2647 #define BNX_RPM_RC_CNTL_0_CLASS (0x7L<<8)
2648 #define BNX_RPM_RC_CNTL_0_PRIORITY (1L<<11)
2649 #define BNX_RPM_RC_CNTL_0_P4 (1L<<12)
2650 #define BNX_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13)
2651 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
2652 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
2653 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
2654 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
2655 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
2656 #define BNX_RPM_RC_CNTL_0_COMP (0x3L<<16)
2657 #define BNX_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
2658 #define BNX_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
2659 #define BNX_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
2660 #define BNX_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
2661 #define BNX_RPM_RC_CNTL_0_SBIT (1L<<19)
2662 #define BNX_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
2663 #define BNX_RPM_RC_CNTL_0_MAP (1L<<24)
2664 #define BNX_RPM_RC_CNTL_0_DISCARD (1L<<25)
2665 #define BNX_RPM_RC_CNTL_0_MASK (1L<<26)
2666 #define BNX_RPM_RC_CNTL_0_P1 (1L<<27)
2667 #define BNX_RPM_RC_CNTL_0_P2 (1L<<28)
2668 #define BNX_RPM_RC_CNTL_0_P3 (1L<<29)
2669 #define BNX_RPM_RC_CNTL_0_NBIT (1L<<30)
2670
2671 #define BNX_RPM_RC_VALUE_MASK_0 0x00001904
2672 #define BNX_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0)
2673 #define BNX_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16)
2674
2675 #define BNX_RPM_RC_CNTL_1 0x00001908
2676 #define BNX_RPM_RC_CNTL_1_A (0x3ffffL<<0)
2677 #define BNX_RPM_RC_CNTL_1_B (0xfffL<<19)
2678
2679 #define BNX_RPM_RC_VALUE_MASK_1 0x0000190c
2680 #define BNX_RPM_RC_CNTL_2 0x00001910
2681 #define BNX_RPM_RC_CNTL_2_A (0x3ffffL<<0)
2682 #define BNX_RPM_RC_CNTL_2_B (0xfffL<<19)
2683
2684 #define BNX_RPM_RC_VALUE_MASK_2 0x00001914
2685 #define BNX_RPM_RC_CNTL_3 0x00001918
2686 #define BNX_RPM_RC_CNTL_3_A (0x3ffffL<<0)
2687 #define BNX_RPM_RC_CNTL_3_B (0xfffL<<19)
2688
2689 #define BNX_RPM_RC_VALUE_MASK_3 0x0000191c
2690 #define BNX_RPM_RC_CNTL_4 0x00001920
2691 #define BNX_RPM_RC_CNTL_4_A (0x3ffffL<<0)
2692 #define BNX_RPM_RC_CNTL_4_B (0xfffL<<19)
2693
2694 #define BNX_RPM_RC_VALUE_MASK_4 0x00001924
2695 #define BNX_RPM_RC_CNTL_5 0x00001928
2696 #define BNX_RPM_RC_CNTL_5_A (0x3ffffL<<0)
2697 #define BNX_RPM_RC_CNTL_5_B (0xfffL<<19)
2698
2699 #define BNX_RPM_RC_VALUE_MASK_5 0x0000192c
2700 #define BNX_RPM_RC_CNTL_6 0x00001930
2701 #define BNX_RPM_RC_CNTL_6_A (0x3ffffL<<0)
2702 #define BNX_RPM_RC_CNTL_6_B (0xfffL<<19)
2703
2704 #define BNX_RPM_RC_VALUE_MASK_6 0x00001934
2705 #define BNX_RPM_RC_CNTL_7 0x00001938
2706 #define BNX_RPM_RC_CNTL_7_A (0x3ffffL<<0)
2707 #define BNX_RPM_RC_CNTL_7_B (0xfffL<<19)
2708
2709 #define BNX_RPM_RC_VALUE_MASK_7 0x0000193c
2710 #define BNX_RPM_RC_CNTL_8 0x00001940
2711 #define BNX_RPM_RC_CNTL_8_A (0x3ffffL<<0)
2712 #define BNX_RPM_RC_CNTL_8_B (0xfffL<<19)
2713
2714 #define BNX_RPM_RC_VALUE_MASK_8 0x00001944
2715 #define BNX_RPM_RC_CNTL_9 0x00001948
2716 #define BNX_RPM_RC_CNTL_9_A (0x3ffffL<<0)
2717 #define BNX_RPM_RC_CNTL_9_B (0xfffL<<19)
2718
2719 #define BNX_RPM_RC_VALUE_MASK_9 0x0000194c
2720 #define BNX_RPM_RC_CNTL_10 0x00001950
2721 #define BNX_RPM_RC_CNTL_10_A (0x3ffffL<<0)
2722 #define BNX_RPM_RC_CNTL_10_B (0xfffL<<19)
2723
2724 #define BNX_RPM_RC_VALUE_MASK_10 0x00001954
2725 #define BNX_RPM_RC_CNTL_11 0x00001958
2726 #define BNX_RPM_RC_CNTL_11_A (0x3ffffL<<0)
2727 #define BNX_RPM_RC_CNTL_11_B (0xfffL<<19)
2728
2729 #define BNX_RPM_RC_VALUE_MASK_11 0x0000195c
2730 #define BNX_RPM_RC_CNTL_12 0x00001960
2731 #define BNX_RPM_RC_CNTL_12_A (0x3ffffL<<0)
2732 #define BNX_RPM_RC_CNTL_12_B (0xfffL<<19)
2733
2734 #define BNX_RPM_RC_VALUE_MASK_12 0x00001964
2735 #define BNX_RPM_RC_CNTL_13 0x00001968
2736 #define BNX_RPM_RC_CNTL_13_A (0x3ffffL<<0)
2737 #define BNX_RPM_RC_CNTL_13_B (0xfffL<<19)
2738
2739 #define BNX_RPM_RC_VALUE_MASK_13 0x0000196c
2740 #define BNX_RPM_RC_CNTL_14 0x00001970
2741 #define BNX_RPM_RC_CNTL_14_A (0x3ffffL<<0)
2742 #define BNX_RPM_RC_CNTL_14_B (0xfffL<<19)
2743
2744 #define BNX_RPM_RC_VALUE_MASK_14 0x00001974
2745 #define BNX_RPM_RC_CNTL_15 0x00001978
2746 #define BNX_RPM_RC_CNTL_15_A (0x3ffffL<<0)
2747 #define BNX_RPM_RC_CNTL_15_B (0xfffL<<19)
2748
2749 #define BNX_RPM_RC_VALUE_MASK_15 0x0000197c
2750 #define BNX_RPM_RC_CONFIG 0x00001980
2751 #define BNX_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
2752 #define BNX_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
2753
2754 #define BNX_RPM_DEBUG0 0x00001984
2755 #define BNX_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
2756 #define BNX_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
2757 #define BNX_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
2758 #define BNX_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
2759 #define BNX_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
2760 #define BNX_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
2761 #define BNX_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
2762 #define BNX_RPM_DEBUG0_LLC_SNAP (1L<<22)
2763 #define BNX_RPM_DEBUG0_FM_STARTED (1L<<23)
2764 #define BNX_RPM_DEBUG0_DONE (1L<<24)
2765 #define BNX_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
2766 #define BNX_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
2767 #define BNX_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
2768 #define BNX_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
2769 #define BNX_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
2770
2771 #define BNX_RPM_DEBUG1 0x00001988
2772 #define BNX_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0)
2773 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
2774 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
2775 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
2776 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
2777 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
2778 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
2779 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
2780 #define BNX_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
2781 #define BNX_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
2782 #define BNX_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
2783 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
2784 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
2785 #define BNX_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
2786 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0)
2787 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0)
2788 #define BNX_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0)
2789 #define BNX_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16)
2790 #define BNX_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
2791 #define BNX_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
2792 #define BNX_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
2793 #define BNX_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
2794
2795 #define BNX_RPM_DEBUG2 0x0000198c
2796 #define BNX_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0)
2797 #define BNX_RPM_DEBUG2_IP_BCNT (0xffL<<16)
2798 #define BNX_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
2799 #define BNX_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
2800 #define BNX_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
2801 #define BNX_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
2802 #define BNX_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
2803 #define BNX_RPM_DEBUG2_FM_DISCARD (1L<<29)
2804 #define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
2805 #define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
2806
2807 #define BNX_RPM_DEBUG3 0x00001990
2808 #define BNX_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0)
2809 #define BNX_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
2810 #define BNX_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
2811 #define BNX_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
2812 #define BNX_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
2813 #define BNX_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
2814 #define BNX_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
2815 #define BNX_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
2816 #define BNX_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16)
2817 #define BNX_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
2818 #define BNX_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
2819 #define BNX_RPM_DEBUG3_DROP_NXT (1L<<23)
2820 #define BNX_RPM_DEBUG3_FTQ_FSM (0x3L<<24)
2821 #define BNX_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24)
2822 #define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24)
2823 #define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24)
2824 #define BNX_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26)
2825 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26)
2826 #define BNX_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26)
2827 #define BNX_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26)
2828 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26)
2829 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26)
2830 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26)
2831 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26)
2832 #define BNX_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26)
2833 #define BNX_RPM_DEBUG3_MBFREE_FSM (1L<<29)
2834 #define BNX_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
2835 #define BNX_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
2836 #define BNX_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
2837 #define BNX_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30)
2838 #define BNX_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30)
2839 #define BNX_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
2840
2841 #define BNX_RPM_DEBUG4 0x00001994
2842 #define BNX_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0)
2843 #define BNX_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25)
2844 #define BNX_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28)
2845 #define BNX_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
2846
2847 #define BNX_RPM_DEBUG5 0x00001998
2848 #define BNX_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0)
2849 #define BNX_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5)
2850 #define BNX_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10)
2851 #define BNX_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15)
2852 #define BNX_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
2853 #define BNX_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
2854 #define BNX_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
2855 #define BNX_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
2856 #define BNX_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
2857 #define BNX_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
2858 #define BNX_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
2859 #define BNX_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
2860 #define BNX_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
2861 #define BNX_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
2862 #define BNX_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
2863 #define BNX_RPM_DEBUG5_HOLDREG_RD (1L<<31)
2864
2865 #define BNX_RPM_DEBUG6 0x0000199c
2866 #define BNX_RPM_DEBUG6_ACPI_VEC (0xffffL<<0)
2867 #define BNX_RPM_DEBUG6_VEC (0xffffL<<16)
2868
2869 #define BNX_RPM_DEBUG7 0x000019a0
2870 #define BNX_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0)
2871
2872 #define BNX_RPM_DEBUG8 0x000019a4
2873 #define BNX_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0)
2874 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
2875 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
2876 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
2877 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
2878 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
2879 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
2880 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
2881 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
2882 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
2883 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
2884 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
2885 #define BNX_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
2886 #define BNX_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
2887 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
2888 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
2889 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
2890 #define BNX_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
2891 #define BNX_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
2892 #define BNX_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
2893 #define BNX_RPM_DEBUG8_EOF_DET (1L<<12)
2894 #define BNX_RPM_DEBUG8_SOF_DET (1L<<13)
2895 #define BNX_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
2896 #define BNX_RPM_DEBUG8_ALL_DONE (1L<<15)
2897 #define BNX_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16)
2898 #define BNX_RPM_DEBUG8_BYTE_CTR (0xffL<<24)
2899
2900 #define BNX_RPM_DEBUG9 0x000019a8
2901 #define BNX_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0)
2902 #define BNX_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
2903 #define BNX_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4)
2904 #define BNX_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
2905 #define BNX_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
2906 #define BNX_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
2907 #define BNX_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
2908
2909 #define BNX_RPM_ACPI_DBG_BUF_W00 0x000019c0
2910 #define BNX_RPM_ACPI_DBG_BUF_W01 0x000019c4
2911 #define BNX_RPM_ACPI_DBG_BUF_W02 0x000019c8
2912 #define BNX_RPM_ACPI_DBG_BUF_W03 0x000019cc
2913 #define BNX_RPM_ACPI_DBG_BUF_W10 0x000019d0
2914 #define BNX_RPM_ACPI_DBG_BUF_W11 0x000019d4
2915 #define BNX_RPM_ACPI_DBG_BUF_W12 0x000019d8
2916 #define BNX_RPM_ACPI_DBG_BUF_W13 0x000019dc
2917 #define BNX_RPM_ACPI_DBG_BUF_W20 0x000019e0
2918 #define BNX_RPM_ACPI_DBG_BUF_W21 0x000019e4
2919 #define BNX_RPM_ACPI_DBG_BUF_W22 0x000019e8
2920 #define BNX_RPM_ACPI_DBG_BUF_W23 0x000019ec
2921 #define BNX_RPM_ACPI_DBG_BUF_W30 0x000019f0
2922 #define BNX_RPM_ACPI_DBG_BUF_W31 0x000019f4
2923 #define BNX_RPM_ACPI_DBG_BUF_W32 0x000019f8
2924 #define BNX_RPM_ACPI_DBG_BUF_W33 0x000019fc
2925
2926
2927
2928
2929
2930
2931 #define BNX_RBUF_COMMAND 0x00200000
2932 #define BNX_RBUF_COMMAND_ENABLED (1L<<0)
2933 #define BNX_RBUF_COMMAND_FREE_INIT (1L<<1)
2934 #define BNX_RBUF_COMMAND_RAM_INIT (1L<<2)
2935 #define BNX_RBUF_COMMAND_OVER_FREE (1L<<4)
2936 #define BNX_RBUF_COMMAND_ALLOC_REQ (1L<<5)
2937
2938 #define BNX_RBUF_STATUS1 0x00200004
2939 #define BNX_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
2940
2941 #define BNX_RBUF_STATUS2 0x00200008
2942 #define BNX_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0)
2943 #define BNX_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16)
2944
2945 #define BNX_RBUF_CONFIG 0x0020000c
2946 #define BNX_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
2947 #define BNX_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
2948
2949 #define BNX_RBUF_FW_BUF_ALLOC 0x00200010
2950 #define BNX_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
2951
2952 #define BNX_RBUF_FW_BUF_FREE 0x00200014
2953 #define BNX_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
2954 #define BNX_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
2955 #define BNX_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
2956
2957 #define BNX_RBUF_FW_BUF_SEL 0x00200018
2958 #define BNX_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
2959 #define BNX_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
2960 #define BNX_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
2961
2962 #define BNX_RBUF_CONFIG2 0x0020001c
2963 #define BNX_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
2964 #define BNX_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
2965
2966 #define BNX_RBUF_CONFIG3 0x00200020
2967 #define BNX_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
2968 #define BNX_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
2969
2970 #define BNX_RBUF_PKT_DATA 0x00208000
2971 #define BNX_RBUF_CLIST_DATA 0x00210000
2972 #define BNX_RBUF_BUF_DATA 0x00220000
2973
2974
2975
2976
2977
2978
2979 #define BNX_RV2P_COMMAND 0x00002800
2980 #define BNX_RV2P_COMMAND_ENABLED (1L<<0)
2981 #define BNX_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
2982 #define BNX_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
2983 #define BNX_RV2P_COMMAND_ABORT0 (1L<<4)
2984 #define BNX_RV2P_COMMAND_ABORT1 (1L<<5)
2985 #define BNX_RV2P_COMMAND_ABORT2 (1L<<6)
2986 #define BNX_RV2P_COMMAND_ABORT3 (1L<<7)
2987 #define BNX_RV2P_COMMAND_ABORT4 (1L<<8)
2988 #define BNX_RV2P_COMMAND_ABORT5 (1L<<9)
2989 #define BNX_RV2P_COMMAND_PROC1_RESET (1L<<16)
2990 #define BNX_RV2P_COMMAND_PROC2_RESET (1L<<17)
2991 #define BNX_RV2P_COMMAND_CTXIF_RESET (1L<<18)
2992
2993 #define BNX_RV2P_STATUS 0x00002804
2994 #define BNX_RV2P_STATUS_ALWAYS_0 (1L<<0)
2995 #define BNX_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
2996 #define BNX_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
2997 #define BNX_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
2998 #define BNX_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
2999 #define BNX_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
3000 #define BNX_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
3001
3002 #define BNX_RV2P_CONFIG 0x00002808
3003 #define BNX_RV2P_CONFIG_STALL_PROC1 (1L<<0)
3004 #define BNX_RV2P_CONFIG_STALL_PROC2 (1L<<1)
3005 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
3006 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
3007 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
3008 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
3009 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
3010 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
3011 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
3012 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
3013 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
3014 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
3015 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
3016 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
3017 #define BNX_RV2P_CONFIG_PAGE_SIZE (0xfL<<24)
3018 #define BNX_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
3019 #define BNX_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
3020 #define BNX_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
3021 #define BNX_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
3022 #define BNX_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
3023 #define BNX_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
3024 #define BNX_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
3025 #define BNX_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
3026 #define BNX_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
3027 #define BNX_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
3028 #define BNX_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
3029 #define BNX_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
3030 #define BNX_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
3031
3032 #define BNX_RV2P_GEN_BFR_ADDR_0 0x00002810
3033 #define BNX_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16)
3034
3035 #define BNX_RV2P_GEN_BFR_ADDR_1 0x00002814
3036 #define BNX_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16)
3037
3038 #define BNX_RV2P_GEN_BFR_ADDR_2 0x00002818
3039 #define BNX_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16)
3040
3041 #define BNX_RV2P_GEN_BFR_ADDR_3 0x0000281c
3042 #define BNX_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16)
3043
3044 #define BNX_RV2P_INSTR_HIGH 0x00002830
3045 #define BNX_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
3046
3047 #define BNX_RV2P_INSTR_LOW 0x00002834
3048 #define BNX_RV2P_PROC1_ADDR_CMD 0x00002838
3049 #define BNX_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
3050 #define BNX_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
3051
3052 #define BNX_RV2P_PROC2_ADDR_CMD 0x0000283c
3053 #define BNX_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0)
3054 #define BNX_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
3055
3056 #define BNX_RV2P_PROC1_GRC_DEBUG 0x00002840
3057 #define BNX_RV2P_PROC2_GRC_DEBUG 0x00002844
3058 #define BNX_RV2P_GRC_PROC_DEBUG 0x00002848
3059 #define BNX_RV2P_DEBUG_VECT_PEEK 0x0000284c
3060 #define BNX_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3061 #define BNX_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3062 #define BNX_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3063 #define BNX_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3064 #define BNX_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3065 #define BNX_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3066
3067 #define BNX_RV2P_PFTQ_DATA 0x00002b40
3068 #define BNX_RV2P_PFTQ_CMD 0x00002b78
3069 #define BNX_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0)
3070 #define BNX_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
3071 #define BNX_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
3072 #define BNX_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10)
3073 #define BNX_RV2P_PFTQ_CMD_SFT_RESET (1L<<25)
3074 #define BNX_RV2P_PFTQ_CMD_RD_DATA (1L<<26)
3075 #define BNX_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27)
3076 #define BNX_RV2P_PFTQ_CMD_ADD_DATA (1L<<28)
3077 #define BNX_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29)
3078 #define BNX_RV2P_PFTQ_CMD_POP (1L<<30)
3079 #define BNX_RV2P_PFTQ_CMD_BUSY (1L<<31)
3080
3081 #define BNX_RV2P_PFTQ_CTL 0x00002b7c
3082 #define BNX_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
3083 #define BNX_RV2P_PFTQ_CTL_OVERFLOW (1L<<1)
3084 #define BNX_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2)
3085 #define BNX_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3086 #define BNX_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3087
3088 #define BNX_RV2P_TFTQ_DATA 0x00002b80
3089 #define BNX_RV2P_TFTQ_CMD 0x00002bb8
3090 #define BNX_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0)
3091 #define BNX_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
3092 #define BNX_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
3093 #define BNX_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10)
3094 #define BNX_RV2P_TFTQ_CMD_SFT_RESET (1L<<25)
3095 #define BNX_RV2P_TFTQ_CMD_RD_DATA (1L<<26)
3096 #define BNX_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27)
3097 #define BNX_RV2P_TFTQ_CMD_ADD_DATA (1L<<28)
3098 #define BNX_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29)
3099 #define BNX_RV2P_TFTQ_CMD_POP (1L<<30)
3100 #define BNX_RV2P_TFTQ_CMD_BUSY (1L<<31)
3101
3102 #define BNX_RV2P_TFTQ_CTL 0x00002bbc
3103 #define BNX_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
3104 #define BNX_RV2P_TFTQ_CTL_OVERFLOW (1L<<1)
3105 #define BNX_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2)
3106 #define BNX_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3107 #define BNX_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3108
3109 #define BNX_RV2P_MFTQ_DATA 0x00002bc0
3110 #define BNX_RV2P_MFTQ_CMD 0x00002bf8
3111 #define BNX_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0)
3112 #define BNX_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
3113 #define BNX_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
3114 #define BNX_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10)
3115 #define BNX_RV2P_MFTQ_CMD_SFT_RESET (1L<<25)
3116 #define BNX_RV2P_MFTQ_CMD_RD_DATA (1L<<26)
3117 #define BNX_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27)
3118 #define BNX_RV2P_MFTQ_CMD_ADD_DATA (1L<<28)
3119 #define BNX_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29)
3120 #define BNX_RV2P_MFTQ_CMD_POP (1L<<30)
3121 #define BNX_RV2P_MFTQ_CMD_BUSY (1L<<31)
3122
3123 #define BNX_RV2P_MFTQ_CTL 0x00002bfc
3124 #define BNX_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
3125 #define BNX_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
3126 #define BNX_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
3127 #define BNX_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3128 #define BNX_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3129
3130
3131
3132
3133
3134
3135
3136 #define BNX_MQ_COMMAND 0x00003c00
3137 #define BNX_MQ_COMMAND_ENABLED (1L<<0)
3138 #define BNX_MQ_COMMAND_OVERFLOW (1L<<4)
3139 #define BNX_MQ_COMMAND_WR_ERROR (1L<<5)
3140 #define BNX_MQ_COMMAND_RD_ERROR (1L<<6)
3141
3142 #define BNX_MQ_STATUS 0x00003c04
3143 #define BNX_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
3144 #define BNX_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
3145 #define BNX_MQ_STATUS_PCI_STALL_STAT (1L<<18)
3146
3147 #define BNX_MQ_CONFIG 0x00003c08
3148 #define BNX_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
3149 #define BNX_MQ_CONFIG_HALT_DIS (1L<<1)
3150 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
3151 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
3152 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
3153 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
3154 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
3155 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
3156 #define BNX_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
3157 #define BNX_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
3158
3159 #define BNX_MQ_ENQUEUE1 0x00003c0c
3160 #define BNX_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
3161 #define BNX_MQ_ENQUEUE1_CID (0x3fffL<<8)
3162 #define BNX_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
3163 #define BNX_MQ_ENQUEUE1_KNL_MODE (1L<<28)
3164
3165 #define BNX_MQ_ENQUEUE2 0x00003c10
3166 #define BNX_MQ_BAD_WR_ADDR 0x00003c14
3167 #define BNX_MQ_BAD_RD_ADDR 0x00003c18
3168 #define BNX_MQ_KNL_BYP_WIND_START 0x00003c1c
3169 #define BNX_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
3170
3171 #define BNX_MQ_KNL_WIND_END 0x00003c20
3172 #define BNX_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
3173
3174 #define BNX_MQ_KNL_WRITE_MASK1 0x00003c24
3175 #define BNX_MQ_KNL_TX_MASK1 0x00003c28
3176 #define BNX_MQ_KNL_CMD_MASK1 0x00003c2c
3177 #define BNX_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
3178 #define BNX_MQ_KNL_RX_V2P_MASK1 0x00003c34
3179 #define BNX_MQ_KNL_WRITE_MASK2 0x00003c38
3180 #define BNX_MQ_KNL_TX_MASK2 0x00003c3c
3181 #define BNX_MQ_KNL_CMD_MASK2 0x00003c40
3182 #define BNX_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
3183 #define BNX_MQ_KNL_RX_V2P_MASK2 0x00003c48
3184 #define BNX_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
3185 #define BNX_MQ_KNL_BYP_TX_MASK1 0x00003c50
3186 #define BNX_MQ_KNL_BYP_CMD_MASK1 0x00003c54
3187 #define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
3188 #define BNX_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
3189 #define BNX_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
3190 #define BNX_MQ_KNL_BYP_TX_MASK2 0x00003c64
3191 #define BNX_MQ_KNL_BYP_CMD_MASK2 0x00003c68
3192 #define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
3193 #define BNX_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
3194 #define BNX_MQ_MEM_WR_ADDR 0x00003c74
3195 #define BNX_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
3196
3197 #define BNX_MQ_MEM_WR_DATA0 0x00003c78
3198 #define BNX_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
3199
3200 #define BNX_MQ_MEM_WR_DATA1 0x00003c7c
3201 #define BNX_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
3202
3203 #define BNX_MQ_MEM_WR_DATA2 0x00003c80
3204 #define BNX_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
3205
3206 #define BNX_MQ_MEM_RD_ADDR 0x00003c84
3207 #define BNX_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
3208
3209 #define BNX_MQ_MEM_RD_DATA0 0x00003c88
3210 #define BNX_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
3211
3212 #define BNX_MQ_MEM_RD_DATA1 0x00003c8c
3213 #define BNX_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
3214
3215 #define BNX_MQ_MEM_RD_DATA2 0x00003c90
3216 #define BNX_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
3217
3218
3219
3220
3221
3222
3223
3224 #define BNX_TBDR_COMMAND 0x00005000
3225 #define BNX_TBDR_COMMAND_ENABLE (1L<<0)
3226 #define BNX_TBDR_COMMAND_SOFT_RST (1L<<1)
3227 #define BNX_TBDR_COMMAND_MSTR_ABORT (1L<<4)
3228
3229 #define BNX_TBDR_STATUS 0x00005004
3230 #define BNX_TBDR_STATUS_DMA_WAIT (1L<<0)
3231 #define BNX_TBDR_STATUS_FTQ_WAIT (1L<<1)
3232 #define BNX_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
3233 #define BNX_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
3234 #define BNX_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
3235 #define BNX_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
3236 #define BNX_TBDR_STATUS_BURST_CNT (1L<<6)
3237
3238 #define BNX_TBDR_CONFIG 0x00005008
3239 #define BNX_TBDR_CONFIG_MAX_BDS (0xffL<<0)
3240 #define BNX_TBDR_CONFIG_SWAP_MODE (1L<<8)
3241 #define BNX_TBDR_CONFIG_PRIORITY (1L<<9)
3242 #define BNX_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
3243 #define BNX_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
3244 #define BNX_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
3245 #define BNX_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
3246 #define BNX_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
3247 #define BNX_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
3248 #define BNX_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
3249 #define BNX_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
3250 #define BNX_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
3251 #define BNX_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
3252 #define BNX_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
3253 #define BNX_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
3254 #define BNX_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
3255 #define BNX_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
3256 #define BNX_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
3257
3258 #define BNX_TBDR_DEBUG_VECT_PEEK 0x0000500c
3259 #define BNX_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3260 #define BNX_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3261 #define BNX_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3262 #define BNX_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3263 #define BNX_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3264 #define BNX_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3265
3266 #define BNX_TBDR_FTQ_DATA 0x000053c0
3267 #define BNX_TBDR_FTQ_CMD 0x000053f8
3268 #define BNX_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
3269 #define BNX_TBDR_FTQ_CMD_WR_TOP (1L<<10)
3270 #define BNX_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
3271 #define BNX_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
3272 #define BNX_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
3273 #define BNX_TBDR_FTQ_CMD_RD_DATA (1L<<26)
3274 #define BNX_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
3275 #define BNX_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
3276 #define BNX_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
3277 #define BNX_TBDR_FTQ_CMD_POP (1L<<30)
3278 #define BNX_TBDR_FTQ_CMD_BUSY (1L<<31)
3279
3280 #define BNX_TBDR_FTQ_CTL 0x000053fc
3281 #define BNX_TBDR_FTQ_CTL_INTERVENE (1L<<0)
3282 #define BNX_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
3283 #define BNX_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3284 #define BNX_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3285 #define BNX_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3286
3287
3288
3289
3290
3291
3292
3293 #define BNX_TDMA_COMMAND 0x00005c00
3294 #define BNX_TDMA_COMMAND_ENABLED (1L<<0)
3295 #define BNX_TDMA_COMMAND_MASTER_ABORT (1L<<4)
3296 #define BNX_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
3297
3298 #define BNX_TDMA_STATUS 0x00005c04
3299 #define BNX_TDMA_STATUS_DMA_WAIT (1L<<0)
3300 #define BNX_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
3301 #define BNX_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
3302 #define BNX_TDMA_STATUS_LOCK_WAIT (1L<<3)
3303 #define BNX_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
3304 #define BNX_TDMA_STATUS_BURST_CNT (1L<<17)
3305
3306 #define BNX_TDMA_CONFIG 0x00005c08
3307 #define BNX_TDMA_CONFIG_ONE_DMA (1L<<0)
3308 #define BNX_TDMA_CONFIG_ONE_RECORD (1L<<1)
3309 #define BNX_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)
3310 #define BNX_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
3311 #define BNX_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4)
3312 #define BNX_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4)
3313 #define BNX_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4)
3314 #define BNX_TDMA_CONFIG_LINE_SZ (0xfL<<8)
3315 #define BNX_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
3316 #define BNX_TDMA_CONFIG_LINE_SZ_128 (4L<<8)
3317 #define BNX_TDMA_CONFIG_LINE_SZ_256 (6L<<8)
3318 #define BNX_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
3319 #define BNX_TDMA_CONFIG_ALIGN_ENA (1L<<15)
3320 #define BNX_TDMA_CONFIG_CHK_L2_BD (1L<<16)
3321 #define BNX_TDMA_CONFIG_FIFO_CMP (0xfL<<20)
3322
3323 #define BNX_TDMA_PAYLOAD_PROD 0x00005c0c
3324 #define BNX_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3)
3325
3326 #define BNX_TDMA_DBG_WATCHDOG 0x00005c10
3327 #define BNX_TDMA_DBG_TRIGGER 0x00005c14
3328 #define BNX_TDMA_DMAD_FSM 0x00005c80
3329 #define BNX_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
3330 #define BNX_TDMA_DMAD_FSM_PUSH (0xfL<<4)
3331 #define BNX_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8)
3332 #define BNX_TDMA_DMAD_FSM_ARB_CTX (1L<<12)
3333 #define BNX_TDMA_DMAD_FSM_DR_INTF (1L<<16)
3334 #define BNX_TDMA_DMAD_FSM_DMAD (0x7L<<20)
3335 #define BNX_TDMA_DMAD_FSM_BD (0xfL<<24)
3336
3337 #define BNX_TDMA_DMAD_STATUS 0x00005c84
3338 #define BNX_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0)
3339 #define BNX_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4)
3340 #define BNX_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8)
3341 #define BNX_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12)
3342
3343 #define BNX_TDMA_DR_INTF_FSM 0x00005c88
3344 #define BNX_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0)
3345 #define BNX_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4)
3346 #define BNX_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8)
3347 #define BNX_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12)
3348 #define BNX_TDMA_DR_INTF_FSM_DMAD (0x7L<<16)
3349
3350 #define BNX_TDMA_DR_INTF_STATUS 0x00005c8c
3351 #define BNX_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0)
3352 #define BNX_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4)
3353 #define BNX_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8)
3354 #define BNX_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12)
3355 #define BNX_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16)
3356
3357 #define BNX_TDMA_FTQ_DATA 0x00005fc0
3358 #define BNX_TDMA_FTQ_CMD 0x00005ff8
3359 #define BNX_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0)
3360 #define BNX_TDMA_FTQ_CMD_WR_TOP (1L<<10)
3361 #define BNX_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
3362 #define BNX_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10)
3363 #define BNX_TDMA_FTQ_CMD_SFT_RESET (1L<<25)
3364 #define BNX_TDMA_FTQ_CMD_RD_DATA (1L<<26)
3365 #define BNX_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27)
3366 #define BNX_TDMA_FTQ_CMD_ADD_DATA (1L<<28)
3367 #define BNX_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29)
3368 #define BNX_TDMA_FTQ_CMD_POP (1L<<30)
3369 #define BNX_TDMA_FTQ_CMD_BUSY (1L<<31)
3370
3371 #define BNX_TDMA_FTQ_CTL 0x00005ffc
3372 #define BNX_TDMA_FTQ_CTL_INTERVENE (1L<<0)
3373 #define BNX_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
3374 #define BNX_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3375 #define BNX_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3376 #define BNX_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3377
3378
3379
3380
3381
3382
3383
3384 #define BNX_HC_COMMAND 0x00006800
3385 #define BNX_HC_COMMAND_ENABLE (1L<<0)
3386 #define BNX_HC_COMMAND_SKIP_ABORT (1L<<4)
3387 #define BNX_HC_COMMAND_COAL_NOW (1L<<16)
3388 #define BNX_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
3389 #define BNX_HC_COMMAND_STATS_NOW (1L<<18)
3390 #define BNX_HC_COMMAND_FORCE_INT (0x3L<<19)
3391 #define BNX_HC_COMMAND_FORCE_INT_NULL (0L<<19)
3392 #define BNX_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
3393 #define BNX_HC_COMMAND_FORCE_INT_LOW (2L<<19)
3394 #define BNX_HC_COMMAND_FORCE_INT_FREE (3L<<19)
3395 #define BNX_HC_COMMAND_CLR_STAT_NOW (1L<<21)
3396
3397 #define BNX_HC_STATUS 0x00006804
3398 #define BNX_HC_STATUS_MASTER_ABORT (1L<<0)
3399 #define BNX_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
3400 #define BNX_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
3401 #define BNX_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
3402 #define BNX_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
3403 #define BNX_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)
3404 #define BNX_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20)
3405 #define BNX_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23)
3406 #define BNX_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24)
3407 #define BNX_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25)
3408
3409 #define BNX_HC_CONFIG 0x00006808
3410 #define BNX_HC_CONFIG_COLLECT_STATS (1L<<0)
3411 #define BNX_HC_CONFIG_RX_TMR_MODE (1L<<1)
3412 #define BNX_HC_CONFIG_TX_TMR_MODE (1L<<2)
3413 #define BNX_HC_CONFIG_COM_TMR_MODE (1L<<3)
3414 #define BNX_HC_CONFIG_CMD_TMR_MODE (1L<<4)
3415 #define BNX_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
3416 #define BNX_HC_CONFIG_STATUS_PRIORITY (1L<<6)
3417 #define BNX_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
3418
3419 #define BNX_HC_ATTN_BITS_ENABLE 0x0000680c
3420 #define BNX_HC_STATUS_ADDR_L 0x00006810
3421 #define BNX_HC_STATUS_ADDR_H 0x00006814
3422 #define BNX_HC_STATISTICS_ADDR_L 0x00006818
3423 #define BNX_HC_STATISTICS_ADDR_H 0x0000681c
3424 #define BNX_HC_TX_QUICK_CONS_TRIP 0x00006820
3425 #define BNX_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
3426 #define BNX_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16)
3427
3428 #define BNX_HC_COMP_PROD_TRIP 0x00006824
3429 #define BNX_HC_COMP_PROD_TRIP_VALUE (0xffL<<0)
3430 #define BNX_HC_COMP_PROD_TRIP_INT (0xffL<<16)
3431
3432 #define BNX_HC_RX_QUICK_CONS_TRIP 0x00006828
3433 #define BNX_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
3434 #define BNX_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16)
3435
3436 #define BNX_HC_RX_TICKS 0x0000682c
3437 #define BNX_HC_RX_TICKS_VALUE (0x3ffL<<0)
3438 #define BNX_HC_RX_TICKS_INT (0x3ffL<<16)
3439
3440 #define BNX_HC_TX_TICKS 0x00006830
3441 #define BNX_HC_TX_TICKS_VALUE (0x3ffL<<0)
3442 #define BNX_HC_TX_TICKS_INT (0x3ffL<<16)
3443
3444 #define BNX_HC_COM_TICKS 0x00006834
3445 #define BNX_HC_COM_TICKS_VALUE (0x3ffL<<0)
3446 #define BNX_HC_COM_TICKS_INT (0x3ffL<<16)
3447
3448 #define BNX_HC_CMD_TICKS 0x00006838
3449 #define BNX_HC_CMD_TICKS_VALUE (0x3ffL<<0)
3450 #define BNX_HC_CMD_TICKS_INT (0x3ffL<<16)
3451
3452 #define BNX_HC_PERIODIC_TICKS 0x0000683c
3453 #define BNX_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
3454
3455 #define BNX_HC_STAT_COLLECT_TICKS 0x00006840
3456 #define BNX_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
3457
3458 #define BNX_HC_STATS_TICKS 0x00006844
3459 #define BNX_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
3460
3461 #define BNX_HC_STAT_MEM_DATA 0x0000684c
3462 #define BNX_HC_STAT_GEN_SEL_0 0x00006850
3463 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
3464 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
3465 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
3466 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
3467 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
3468 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
3469 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
3470 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
3471 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
3472 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
3473 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
3474 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
3475 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
3476 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
3477 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
3478 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
3479 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
3480 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
3481 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
3482 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
3483 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
3484 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
3485 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
3486 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
3487 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
3488 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
3489 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
3490 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
3491 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
3492 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
3493 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
3494 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
3495 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
3496 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
3497 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
3498 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
3499 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
3500 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
3501 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
3502 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
3503 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
3504 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
3505 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
3506 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
3507 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
3508 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
3509 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
3510 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
3511 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
3512 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
3513 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
3514 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
3515 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
3516 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
3517 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
3518 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
3519 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
3520 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
3521 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
3522 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
3523 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
3524 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
3525 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
3526 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
3527 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
3528 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
3529 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
3530 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
3531 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
3532 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
3533 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
3534 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
3535 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
3536 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
3537 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
3538 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
3539 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
3540 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
3541 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
3542 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
3543 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
3544 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
3545 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
3546 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
3547 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
3548 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
3549 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
3550 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0)
3551 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0)
3552 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
3553 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
3554 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
3555 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0)
3556 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0)
3557 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
3558 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
3559 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
3560 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
3561 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
3562 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
3563 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
3564 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
3565 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
3566 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
3567 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
3568 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
3569 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
3570 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
3571 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
3572 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
3573 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
3574 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
3575 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
3576 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
3577 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
3578 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
3579 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
3580 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
3581 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
3582 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
3583 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
3584 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
3585 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
3586 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
3587 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
3588 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
3589
3590 #define BNX_HC_STAT_GEN_SEL_1 0x00006854
3591 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
3592 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
3593 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
3594 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
3595
3596 #define BNX_HC_STAT_GEN_SEL_2 0x00006858
3597 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
3598 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
3599 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
3600 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
3601
3602 #define BNX_HC_STAT_GEN_SEL_3 0x0000685c
3603 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
3604 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
3605 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
3606 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
3607
3608 #define BNX_HC_STAT_GEN_STAT0 0x00006888
3609 #define BNX_HC_STAT_GEN_STAT1 0x0000688c
3610 #define BNX_HC_STAT_GEN_STAT2 0x00006890
3611 #define BNX_HC_STAT_GEN_STAT3 0x00006894
3612 #define BNX_HC_STAT_GEN_STAT4 0x00006898
3613 #define BNX_HC_STAT_GEN_STAT5 0x0000689c
3614 #define BNX_HC_STAT_GEN_STAT6 0x000068a0
3615 #define BNX_HC_STAT_GEN_STAT7 0x000068a4
3616 #define BNX_HC_STAT_GEN_STAT8 0x000068a8
3617 #define BNX_HC_STAT_GEN_STAT9 0x000068ac
3618 #define BNX_HC_STAT_GEN_STAT10 0x000068b0
3619 #define BNX_HC_STAT_GEN_STAT11 0x000068b4
3620 #define BNX_HC_STAT_GEN_STAT12 0x000068b8
3621 #define BNX_HC_STAT_GEN_STAT13 0x000068bc
3622 #define BNX_HC_STAT_GEN_STAT14 0x000068c0
3623 #define BNX_HC_STAT_GEN_STAT15 0x000068c4
3624 #define BNX_HC_STAT_GEN_STAT_AC0 0x000068c8
3625 #define BNX_HC_STAT_GEN_STAT_AC1 0x000068cc
3626 #define BNX_HC_STAT_GEN_STAT_AC2 0x000068d0
3627 #define BNX_HC_STAT_GEN_STAT_AC3 0x000068d4
3628 #define BNX_HC_STAT_GEN_STAT_AC4 0x000068d8
3629 #define BNX_HC_STAT_GEN_STAT_AC5 0x000068dc
3630 #define BNX_HC_STAT_GEN_STAT_AC6 0x000068e0
3631 #define BNX_HC_STAT_GEN_STAT_AC7 0x000068e4
3632 #define BNX_HC_STAT_GEN_STAT_AC8 0x000068e8
3633 #define BNX_HC_STAT_GEN_STAT_AC9 0x000068ec
3634 #define BNX_HC_STAT_GEN_STAT_AC10 0x000068f0
3635 #define BNX_HC_STAT_GEN_STAT_AC11 0x000068f4
3636 #define BNX_HC_STAT_GEN_STAT_AC12 0x000068f8
3637 #define BNX_HC_STAT_GEN_STAT_AC13 0x000068fc
3638 #define BNX_HC_STAT_GEN_STAT_AC14 0x00006900
3639 #define BNX_HC_STAT_GEN_STAT_AC15 0x00006904
3640 #define BNX_HC_VIS 0x00006908
3641 #define BNX_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
3642 #define BNX_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
3643 #define BNX_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
3644 #define BNX_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
3645 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
3646 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
3647 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
3648 #define BNX_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
3649 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
3650 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
3651 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
3652 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
3653 #define BNX_HC_VIS_DMA_STAT_STATE (0xfL<<8)
3654 #define BNX_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
3655 #define BNX_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8)
3656 #define BNX_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8)
3657 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8)
3658 #define BNX_HC_VIS_DMA_STAT_STATE_COMP (4L<<8)
3659 #define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8)
3660 #define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8)
3661 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8)
3662 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8)
3663 #define BNX_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8)
3664 #define BNX_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8)
3665 #define BNX_HC_VIS_DMA_MSI_STATE (0x7L<<12)
3666 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15)
3667 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
3668 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15)
3669 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15)
3670
3671 #define BNX_HC_VIS_1 0x0000690c
3672 #define BNX_HC_VIS_1_HW_INTACK_STATE (1L<<4)
3673 #define BNX_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
3674 #define BNX_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4)
3675 #define BNX_HC_VIS_1_SW_INTACK_STATE (1L<<5)
3676 #define BNX_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
3677 #define BNX_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5)
3678 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6)
3679 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
3680 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6)
3681 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7)
3682 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
3683 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7)
3684 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17)
3685 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
3686 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17)
3687 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17)
3688 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17)
3689 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17)
3690 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
3691 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
3692 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17)
3693 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21)
3694 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
3695 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21)
3696 #define BNX_HC_VIS_1_INT_GEN_STATE (1L<<23)
3697 #define BNX_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
3698 #define BNX_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23)
3699 #define BNX_HC_VIS_1_STAT_CHAN_ID (0x7L<<24)
3700 #define BNX_HC_VIS_1_INT_B (1L<<27)
3701
3702 #define BNX_HC_DEBUG_VECT_PEEK 0x00006910
3703 #define BNX_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3704 #define BNX_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3705 #define BNX_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3706 #define BNX_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3707 #define BNX_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3708 #define BNX_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3709
3710
3711
3712
3713
3714
3715
3716 #define BNX_TXP_CPU_MODE 0x00045000
3717 #define BNX_TXP_CPU_MODE_LOCAL_RST (1L<<0)
3718 #define BNX_TXP_CPU_MODE_STEP_ENA (1L<<1)
3719 #define BNX_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3720 #define BNX_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3721 #define BNX_TXP_CPU_MODE_MSG_BIT1 (1L<<6)
3722 #define BNX_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3723 #define BNX_TXP_CPU_MODE_SOFT_HALT (1L<<10)
3724 #define BNX_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3725 #define BNX_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3726 #define BNX_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3727 #define BNX_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3728
3729 #define BNX_TXP_CPU_STATE 0x00045004
3730 #define BNX_TXP_CPU_STATE_BREAKPOINT (1L<<0)
3731 #define BNX_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3732 #define BNX_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3733 #define BNX_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3734 #define BNX_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3735 #define BNX_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3736 #define BNX_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3737 #define BNX_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3738 #define BNX_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
3739 #define BNX_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3740 #define BNX_TXP_CPU_STATE_INTERRRUPT (1L<<12)
3741 #define BNX_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3742 #define BNX_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3743 #define BNX_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
3744
3745 #define BNX_TXP_CPU_EVENT_MASK 0x00045008
3746 #define BNX_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3747 #define BNX_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3748 #define BNX_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3749 #define BNX_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3750 #define BNX_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3751 #define BNX_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3752 #define BNX_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3753 #define BNX_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3754 #define BNX_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3755 #define BNX_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3756 #define BNX_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3757
3758 #define BNX_TXP_CPU_PROGRAM_COUNTER 0x0004501c
3759 #define BNX_TXP_CPU_INSTRUCTION 0x00045020
3760 #define BNX_TXP_CPU_DATA_ACCESS 0x00045024
3761 #define BNX_TXP_CPU_INTERRUPT_ENABLE 0x00045028
3762 #define BNX_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
3763 #define BNX_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
3764 #define BNX_TXP_CPU_HW_BREAKPOINT 0x00045034
3765 #define BNX_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3766 #define BNX_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3767
3768 #define BNX_TXP_CPU_DEBUG_VECT_PEEK 0x00045038
3769 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3770 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3771 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3772 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3773 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3774 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3775
3776 #define BNX_TXP_CPU_LAST_BRANCH_ADDR 0x00045048
3777 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3778 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3779 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3780 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3781
3782 #define BNX_TXP_CPU_REG_FILE 0x00045200
3783 #define BNX_TXP_FTQ_DATA 0x000453c0
3784 #define BNX_TXP_FTQ_CMD 0x000453f8
3785 #define BNX_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3786 #define BNX_TXP_FTQ_CMD_WR_TOP (1L<<10)
3787 #define BNX_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
3788 #define BNX_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
3789 #define BNX_TXP_FTQ_CMD_SFT_RESET (1L<<25)
3790 #define BNX_TXP_FTQ_CMD_RD_DATA (1L<<26)
3791 #define BNX_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
3792 #define BNX_TXP_FTQ_CMD_ADD_DATA (1L<<28)
3793 #define BNX_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
3794 #define BNX_TXP_FTQ_CMD_POP (1L<<30)
3795 #define BNX_TXP_FTQ_CMD_BUSY (1L<<31)
3796
3797 #define BNX_TXP_FTQ_CTL 0x000453fc
3798 #define BNX_TXP_FTQ_CTL_INTERVENE (1L<<0)
3799 #define BNX_TXP_FTQ_CTL_OVERFLOW (1L<<1)
3800 #define BNX_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3801 #define BNX_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3802 #define BNX_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3803
3804 #define BNX_TXP_SCRATCH 0x00060000
3805
3806
3807
3808
3809
3810
3811 #define BNX_TPAT_CPU_MODE 0x00085000
3812 #define BNX_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
3813 #define BNX_TPAT_CPU_MODE_STEP_ENA (1L<<1)
3814 #define BNX_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3815 #define BNX_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3816 #define BNX_TPAT_CPU_MODE_MSG_BIT1 (1L<<6)
3817 #define BNX_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7)
3818 #define BNX_TPAT_CPU_MODE_SOFT_HALT (1L<<10)
3819 #define BNX_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3820 #define BNX_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3821 #define BNX_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3822 #define BNX_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3823
3824 #define BNX_TPAT_CPU_STATE 0x00085004
3825 #define BNX_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
3826 #define BNX_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2)
3827 #define BNX_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3828 #define BNX_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3829 #define BNX_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3830 #define BNX_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6)
3831 #define BNX_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
3832 #define BNX_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3833 #define BNX_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
3834 #define BNX_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3835 #define BNX_TPAT_CPU_STATE_INTERRRUPT (1L<<12)
3836 #define BNX_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3837 #define BNX_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15)
3838 #define BNX_TPAT_CPU_STATE_BLOCKED_READ (1L<<31)
3839
3840 #define BNX_TPAT_CPU_EVENT_MASK 0x00085008
3841 #define BNX_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3842 #define BNX_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3843 #define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3844 #define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3845 #define BNX_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3846 #define BNX_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3847 #define BNX_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3848 #define BNX_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3849 #define BNX_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3850 #define BNX_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3851 #define BNX_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3852
3853 #define BNX_TPAT_CPU_PROGRAM_COUNTER 0x0008501c
3854 #define BNX_TPAT_CPU_INSTRUCTION 0x00085020
3855 #define BNX_TPAT_CPU_DATA_ACCESS 0x00085024
3856 #define BNX_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
3857 #define BNX_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
3858 #define BNX_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
3859 #define BNX_TPAT_CPU_HW_BREAKPOINT 0x00085034
3860 #define BNX_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3861 #define BNX_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3862
3863 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038
3864 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3865 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3866 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3867 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3868 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3869 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3870
3871 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048
3872 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3873 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3874 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3875 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3876
3877 #define BNX_TPAT_CPU_REG_FILE 0x00085200
3878 #define BNX_TPAT_FTQ_DATA 0x000853c0
3879 #define BNX_TPAT_FTQ_CMD 0x000853f8
3880 #define BNX_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
3881 #define BNX_TPAT_FTQ_CMD_WR_TOP (1L<<10)
3882 #define BNX_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
3883 #define BNX_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
3884 #define BNX_TPAT_FTQ_CMD_SFT_RESET (1L<<25)
3885 #define BNX_TPAT_FTQ_CMD_RD_DATA (1L<<26)
3886 #define BNX_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27)
3887 #define BNX_TPAT_FTQ_CMD_ADD_DATA (1L<<28)
3888 #define BNX_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29)
3889 #define BNX_TPAT_FTQ_CMD_POP (1L<<30)
3890 #define BNX_TPAT_FTQ_CMD_BUSY (1L<<31)
3891
3892 #define BNX_TPAT_FTQ_CTL 0x000853fc
3893 #define BNX_TPAT_FTQ_CTL_INTERVENE (1L<<0)
3894 #define BNX_TPAT_FTQ_CTL_OVERFLOW (1L<<1)
3895 #define BNX_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3896 #define BNX_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3897 #define BNX_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3898
3899 #define BNX_TPAT_SCRATCH 0x000a0000
3900
3901
3902
3903
3904
3905
3906 #define BNX_RXP_CPU_MODE 0x000c5000
3907 #define BNX_RXP_CPU_MODE_LOCAL_RST (1L<<0)
3908 #define BNX_RXP_CPU_MODE_STEP_ENA (1L<<1)
3909 #define BNX_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3910 #define BNX_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3911 #define BNX_RXP_CPU_MODE_MSG_BIT1 (1L<<6)
3912 #define BNX_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3913 #define BNX_RXP_CPU_MODE_SOFT_HALT (1L<<10)
3914 #define BNX_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3915 #define BNX_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3916 #define BNX_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3917 #define BNX_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3918
3919 #define BNX_RXP_CPU_STATE 0x000c5004
3920 #define BNX_RXP_CPU_STATE_BREAKPOINT (1L<<0)
3921 #define BNX_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3922 #define BNX_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3923 #define BNX_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3924 #define BNX_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3925 #define BNX_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3926 #define BNX_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3927 #define BNX_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3928 #define BNX_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
3929 #define BNX_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3930 #define BNX_RXP_CPU_STATE_INTERRRUPT (1L<<12)
3931 #define BNX_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3932 #define BNX_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3933 #define BNX_RXP_CPU_STATE_BLOCKED_READ (1L<<31)
3934
3935 #define BNX_RXP_CPU_EVENT_MASK 0x000c5008
3936 #define BNX_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3937 #define BNX_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3938 #define BNX_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3939 #define BNX_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3940 #define BNX_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3941 #define BNX_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3942 #define BNX_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3943 #define BNX_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3944 #define BNX_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3945 #define BNX_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3946 #define BNX_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3947
3948 #define BNX_RXP_CPU_PROGRAM_COUNTER 0x000c501c
3949 #define BNX_RXP_CPU_INSTRUCTION 0x000c5020
3950 #define BNX_RXP_CPU_DATA_ACCESS 0x000c5024
3951 #define BNX_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
3952 #define BNX_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
3953 #define BNX_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
3954 #define BNX_RXP_CPU_HW_BREAKPOINT 0x000c5034
3955 #define BNX_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3956 #define BNX_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3957
3958 #define BNX_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038
3959 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3960 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3961 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3962 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3963 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3964 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3965
3966 #define BNX_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048
3967 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3968 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3969 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3970 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3971
3972 #define BNX_RXP_CPU_REG_FILE 0x000c5200
3973 #define BNX_RXP_CFTQ_DATA 0x000c5380
3974 #define BNX_RXP_CFTQ_CMD 0x000c53b8
3975 #define BNX_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
3976 #define BNX_RXP_CFTQ_CMD_WR_TOP (1L<<10)
3977 #define BNX_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
3978 #define BNX_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
3979 #define BNX_RXP_CFTQ_CMD_SFT_RESET (1L<<25)
3980 #define BNX_RXP_CFTQ_CMD_RD_DATA (1L<<26)
3981 #define BNX_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27)
3982 #define BNX_RXP_CFTQ_CMD_ADD_DATA (1L<<28)
3983 #define BNX_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29)
3984 #define BNX_RXP_CFTQ_CMD_POP (1L<<30)
3985 #define BNX_RXP_CFTQ_CMD_BUSY (1L<<31)
3986
3987 #define BNX_RXP_CFTQ_CTL 0x000c53bc
3988 #define BNX_RXP_CFTQ_CTL_INTERVENE (1L<<0)
3989 #define BNX_RXP_CFTQ_CTL_OVERFLOW (1L<<1)
3990 #define BNX_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2)
3991 #define BNX_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3992 #define BNX_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3993
3994 #define BNX_RXP_FTQ_DATA 0x000c53c0
3995 #define BNX_RXP_FTQ_CMD 0x000c53f8
3996 #define BNX_RXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3997 #define BNX_RXP_FTQ_CMD_WR_TOP (1L<<10)
3998 #define BNX_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
3999 #define BNX_RXP_FTQ_CMD_WR_TOP_1 (1L<<10)
4000 #define BNX_RXP_FTQ_CMD_SFT_RESET (1L<<25)
4001 #define BNX_RXP_FTQ_CMD_RD_DATA (1L<<26)
4002 #define BNX_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
4003 #define BNX_RXP_FTQ_CMD_ADD_DATA (1L<<28)
4004 #define BNX_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
4005 #define BNX_RXP_FTQ_CMD_POP (1L<<30)
4006 #define BNX_RXP_FTQ_CMD_BUSY (1L<<31)
4007
4008 #define BNX_RXP_FTQ_CTL 0x000c53fc
4009 #define BNX_RXP_FTQ_CTL_INTERVENE (1L<<0)
4010 #define BNX_RXP_FTQ_CTL_OVERFLOW (1L<<1)
4011 #define BNX_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4012 #define BNX_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4013 #define BNX_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4014
4015 #define BNX_RXP_SCRATCH 0x000e0000
4016
4017
4018
4019
4020
4021
4022 #define BNX_COM_CPU_MODE 0x00105000
4023 #define BNX_COM_CPU_MODE_LOCAL_RST (1L<<0)
4024 #define BNX_COM_CPU_MODE_STEP_ENA (1L<<1)
4025 #define BNX_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
4026 #define BNX_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
4027 #define BNX_COM_CPU_MODE_MSG_BIT1 (1L<<6)
4028 #define BNX_COM_CPU_MODE_INTERRUPT_ENA (1L<<7)
4029 #define BNX_COM_CPU_MODE_SOFT_HALT (1L<<10)
4030 #define BNX_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
4031 #define BNX_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
4032 #define BNX_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
4033 #define BNX_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
4034
4035 #define BNX_COM_CPU_STATE 0x00105004
4036 #define BNX_COM_CPU_STATE_BREAKPOINT (1L<<0)
4037 #define BNX_COM_CPU_STATE_BAD_INST_HALTED (1L<<2)
4038 #define BNX_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
4039 #define BNX_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
4040 #define BNX_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
4041 #define BNX_COM_CPU_STATE_BAD_pc_HALTED (1L<<6)
4042 #define BNX_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
4043 #define BNX_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
4044 #define BNX_COM_CPU_STATE_SOFT_HALTED (1L<<10)
4045 #define BNX_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
4046 #define BNX_COM_CPU_STATE_INTERRRUPT (1L<<12)
4047 #define BNX_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
4048 #define BNX_COM_CPU_STATE_INST_FETCH_STALL (1L<<15)
4049 #define BNX_COM_CPU_STATE_BLOCKED_READ (1L<<31)
4050
4051 #define BNX_COM_CPU_EVENT_MASK 0x00105008
4052 #define BNX_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
4053 #define BNX_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
4054 #define BNX_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
4055 #define BNX_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
4056 #define BNX_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
4057 #define BNX_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
4058 #define BNX_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
4059 #define BNX_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
4060 #define BNX_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
4061 #define BNX_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
4062 #define BNX_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
4063
4064 #define BNX_COM_CPU_PROGRAM_COUNTER 0x0010501c
4065 #define BNX_COM_CPU_INSTRUCTION 0x00105020
4066 #define BNX_COM_CPU_DATA_ACCESS 0x00105024
4067 #define BNX_COM_CPU_INTERRUPT_ENABLE 0x00105028
4068 #define BNX_COM_CPU_INTERRUPT_VECTOR 0x0010502c
4069 #define BNX_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
4070 #define BNX_COM_CPU_HW_BREAKPOINT 0x00105034
4071 #define BNX_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4072 #define BNX_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4073
4074 #define BNX_COM_CPU_DEBUG_VECT_PEEK 0x00105038
4075 #define BNX_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4076 #define BNX_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4077 #define BNX_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4078 #define BNX_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4079 #define BNX_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4080 #define BNX_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4081
4082 #define BNX_COM_CPU_LAST_BRANCH_ADDR 0x00105048
4083 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4084 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4085 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4086 #define BNX_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4087
4088 #define BNX_COM_CPU_REG_FILE 0x00105200
4089 #define BNX_COM_COMXQ_FTQ_DATA 0x00105340
4090 #define BNX_COM_COMXQ_FTQ_CMD 0x00105378
4091 #define BNX_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4092 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
4093 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4094 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4095 #define BNX_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)
4096 #define BNX_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26)
4097 #define BNX_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4098 #define BNX_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28)
4099 #define BNX_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4100 #define BNX_COM_COMXQ_FTQ_CMD_POP (1L<<30)
4101 #define BNX_COM_COMXQ_FTQ_CMD_BUSY (1L<<31)
4102
4103 #define BNX_COM_COMXQ_FTQ_CTL 0x0010537c
4104 #define BNX_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
4105 #define BNX_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1)
4106 #define BNX_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4107 #define BNX_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4108 #define BNX_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4109
4110 #define BNX_COM_COMTQ_FTQ_DATA 0x00105380
4111 #define BNX_COM_COMTQ_FTQ_CMD 0x001053b8
4112 #define BNX_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4113 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
4114 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4115 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4116 #define BNX_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25)
4117 #define BNX_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26)
4118 #define BNX_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4119 #define BNX_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28)
4120 #define BNX_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4121 #define BNX_COM_COMTQ_FTQ_CMD_POP (1L<<30)
4122 #define BNX_COM_COMTQ_FTQ_CMD_BUSY (1L<<31)
4123
4124 #define BNX_COM_COMTQ_FTQ_CTL 0x001053bc
4125 #define BNX_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
4126 #define BNX_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1)
4127 #define BNX_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4128 #define BNX_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4129 #define BNX_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4130
4131 #define BNX_COM_COMQ_FTQ_DATA 0x001053c0
4132 #define BNX_COM_COMQ_FTQ_CMD 0x001053f8
4133 #define BNX_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4134 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
4135 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4136 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4137 #define BNX_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25)
4138 #define BNX_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26)
4139 #define BNX_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4140 #define BNX_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28)
4141 #define BNX_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4142 #define BNX_COM_COMQ_FTQ_CMD_POP (1L<<30)
4143 #define BNX_COM_COMQ_FTQ_CMD_BUSY (1L<<31)
4144
4145 #define BNX_COM_COMQ_FTQ_CTL 0x001053fc
4146 #define BNX_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
4147 #define BNX_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1)
4148 #define BNX_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4149 #define BNX_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4150 #define BNX_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4151
4152 #define BNX_COM_SCRATCH 0x00120000
4153
4154
4155
4156
4157
4158
4159 #define BNX_CP_CPU_MODE 0x00185000
4160 #define BNX_CP_CPU_MODE_LOCAL_RST (1L<<0)
4161 #define BNX_CP_CPU_MODE_STEP_ENA (1L<<1)
4162 #define BNX_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
4163 #define BNX_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
4164 #define BNX_CP_CPU_MODE_MSG_BIT1 (1L<<6)
4165 #define BNX_CP_CPU_MODE_INTERRUPT_ENA (1L<<7)
4166 #define BNX_CP_CPU_MODE_SOFT_HALT (1L<<10)
4167 #define BNX_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
4168 #define BNX_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
4169 #define BNX_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
4170 #define BNX_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
4171
4172 #define BNX_CP_CPU_STATE 0x00185004
4173 #define BNX_CP_CPU_STATE_BREAKPOINT (1L<<0)
4174 #define BNX_CP_CPU_STATE_BAD_INST_HALTED (1L<<2)
4175 #define BNX_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
4176 #define BNX_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
4177 #define BNX_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
4178 #define BNX_CP_CPU_STATE_BAD_pc_HALTED (1L<<6)
4179 #define BNX_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
4180 #define BNX_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
4181 #define BNX_CP_CPU_STATE_SOFT_HALTED (1L<<10)
4182 #define BNX_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
4183 #define BNX_CP_CPU_STATE_INTERRRUPT (1L<<12)
4184 #define BNX_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
4185 #define BNX_CP_CPU_STATE_INST_FETCH_STALL (1L<<15)
4186 #define BNX_CP_CPU_STATE_BLOCKED_READ (1L<<31)
4187
4188 #define BNX_CP_CPU_EVENT_MASK 0x00185008
4189 #define BNX_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
4190 #define BNX_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
4191 #define BNX_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
4192 #define BNX_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
4193 #define BNX_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
4194 #define BNX_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
4195 #define BNX_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
4196 #define BNX_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
4197 #define BNX_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
4198 #define BNX_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
4199 #define BNX_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
4200
4201 #define BNX_CP_CPU_PROGRAM_COUNTER 0x0018501c
4202 #define BNX_CP_CPU_INSTRUCTION 0x00185020
4203 #define BNX_CP_CPU_DATA_ACCESS 0x00185024
4204 #define BNX_CP_CPU_INTERRUPT_ENABLE 0x00185028
4205 #define BNX_CP_CPU_INTERRUPT_VECTOR 0x0018502c
4206 #define BNX_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
4207 #define BNX_CP_CPU_HW_BREAKPOINT 0x00185034
4208 #define BNX_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4209 #define BNX_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4210
4211 #define BNX_CP_CPU_DEBUG_VECT_PEEK 0x00185038
4212 #define BNX_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4213 #define BNX_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4214 #define BNX_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4215 #define BNX_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4216 #define BNX_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4217 #define BNX_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4218
4219 #define BNX_CP_CPU_LAST_BRANCH_ADDR 0x00185048
4220 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4221 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4222 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4223 #define BNX_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4224
4225 #define BNX_CP_CPU_REG_FILE 0x00185200
4226 #define BNX_CP_CPQ_FTQ_DATA 0x001853c0
4227 #define BNX_CP_CPQ_FTQ_CMD 0x001853f8
4228 #define BNX_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4229 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
4230 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4231 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4232 #define BNX_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)
4233 #define BNX_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26)
4234 #define BNX_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4235 #define BNX_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28)
4236 #define BNX_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4237 #define BNX_CP_CPQ_FTQ_CMD_POP (1L<<30)
4238 #define BNX_CP_CPQ_FTQ_CMD_BUSY (1L<<31)
4239
4240 #define BNX_CP_CPQ_FTQ_CTL 0x001853fc
4241 #define BNX_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
4242 #define BNX_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1)
4243 #define BNX_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4244 #define BNX_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4245 #define BNX_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4246
4247 #define BNX_CP_SCRATCH 0x001a0000
4248
4249
4250
4251
4252
4253
4254 #define BNX_MCP_CPU_MODE 0x00145000
4255 #define BNX_MCP_CPU_MODE_LOCAL_RST (1L<<0)
4256 #define BNX_MCP_CPU_MODE_STEP_ENA (1L<<1)
4257 #define BNX_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
4258 #define BNX_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
4259 #define BNX_MCP_CPU_MODE_MSG_BIT1 (1L<<6)
4260 #define BNX_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7)
4261 #define BNX_MCP_CPU_MODE_SOFT_HALT (1L<<10)
4262 #define BNX_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
4263 #define BNX_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
4264 #define BNX_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
4265 #define BNX_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
4266
4267 #define BNX_MCP_CPU_STATE 0x00145004
4268 #define BNX_MCP_CPU_STATE_BREAKPOINT (1L<<0)
4269 #define BNX_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2)
4270 #define BNX_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
4271 #define BNX_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
4272 #define BNX_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
4273 #define BNX_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6)
4274 #define BNX_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
4275 #define BNX_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
4276 #define BNX_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
4277 #define BNX_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
4278 #define BNX_MCP_CPU_STATE_INTERRRUPT (1L<<12)
4279 #define BNX_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
4280 #define BNX_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15)
4281 #define BNX_MCP_CPU_STATE_BLOCKED_READ (1L<<31)
4282
4283 #define BNX_MCP_CPU_EVENT_MASK 0x00145008
4284 #define BNX_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
4285 #define BNX_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
4286 #define BNX_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
4287 #define BNX_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
4288 #define BNX_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
4289 #define BNX_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
4290 #define BNX_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
4291 #define BNX_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
4292 #define BNX_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
4293 #define BNX_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
4294 #define BNX_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
4295
4296 #define BNX_MCP_CPU_PROGRAM_COUNTER 0x0014501c
4297 #define BNX_MCP_CPU_INSTRUCTION 0x00145020
4298 #define BNX_MCP_CPU_DATA_ACCESS 0x00145024
4299 #define BNX_MCP_CPU_INTERRUPT_ENABLE 0x00145028
4300 #define BNX_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
4301 #define BNX_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
4302 #define BNX_MCP_CPU_HW_BREAKPOINT 0x00145034
4303 #define BNX_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4304 #define BNX_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4305
4306 #define BNX_MCP_CPU_DEBUG_VECT_PEEK 0x00145038
4307 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4308 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4309 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4310 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4311 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4312 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4313
4314 #define BNX_MCP_CPU_LAST_BRANCH_ADDR 0x00145048
4315 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4316 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4317 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4318 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4319
4320 #define BNX_MCP_CPU_REG_FILE 0x00145200
4321 #define BNX_MCP_MCPQ_FTQ_DATA 0x001453c0
4322 #define BNX_MCP_MCPQ_FTQ_CMD 0x001453f8
4323 #define BNX_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4324 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
4325 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4326 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4327 #define BNX_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
4328 #define BNX_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
4329 #define BNX_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
4330 #define BNX_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
4331 #define BNX_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
4332 #define BNX_MCP_MCPQ_FTQ_CMD_POP (1L<<30)
4333 #define BNX_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31)
4334
4335 #define BNX_MCP_MCPQ_FTQ_CTL 0x001453fc
4336 #define BNX_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
4337 #define BNX_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
4338 #define BNX_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4339 #define BNX_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4340 #define BNX_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4341
4342 #define BNX_MCP_ROM 0x00150000
4343 #define BNX_MCP_SCRATCH 0x00160000
4344
4345 #define BNX_SHM_HDR_SIGNATURE BNX_MCP_SCRATCH
4346 #define BNX_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000
4347 #define BNX_SHM_HDR_SIGNATURE_SIG 0x53530000
4348 #define BNX_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff
4349 #define BNX_SHM_HDR_SIGNATURE_VER_ONE 0x00000001
4350
4351 #define BNX_SHM_HDR_ADDR_0 BNX_MCP_SCRATCH + 4
4352 #define BNX_SHM_HDR_ADDR_1 BNX_MCP_SCRATCH + 8
4353
4354
4355
4356
4357
4358 #define NUM_MC_HASH_REGISTERS 8
4359
4360
4361
4362 #define PHY_BCM5706_PHY_ID 0x00206160
4363
4364 #define PHY_ID(id) ((id) & 0xfffffff0)
4365 #define PHY_REV_ID(id) ((id) & 0xf)
4366
4367
4368
4369 #define BCM5708S_UP1 0xb
4370
4371 #define BCM5708S_UP1_2G5 0x1
4372
4373 #define BCM5708S_BLK_ADDR 0x1f
4374
4375 #define BCM5708S_BLK_ADDR_DIG 0x0000
4376 #define BCM5708S_BLK_ADDR_DIG3 0x0002
4377 #define BCM5708S_BLK_ADDR_TX_MISC 0x0005
4378
4379
4380 #define BCM5708S_1000X_CTL1 0x10
4381
4382 #define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001
4383 #define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010
4384
4385 #define BCM5708S_1000X_CTL2 0x11
4386
4387 #define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001
4388
4389 #define BCM5708S_1000X_STAT1 0x14
4390
4391 #define BCM5708S_1000X_STAT1_SGMII 0x0001
4392 #define BCM5708S_1000X_STAT1_LINK 0x0002
4393 #define BCM5708S_1000X_STAT1_FD 0x0004
4394 #define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018
4395 #define BCM5708S_1000X_STAT1_SPEED_10 0x0000
4396 #define BCM5708S_1000X_STAT1_SPEED_100 0x0008
4397 #define BCM5708S_1000X_STAT1_SPEED_1G 0x0010
4398 #define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018
4399 #define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020
4400 #define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040
4401
4402
4403 #define BCM5708S_DIG_3_0 0x10
4404
4405 #define BCM5708S_DIG_3_0_USE_IEEE 0x0001
4406
4407
4408 #define BCM5708S_TX_ACTL1 0x15
4409
4410 #define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30
4411
4412 #define BCM5708S_TX_ACTL3 0x17
4413
4414 #define RX_COPY_THRESH 92
4415
4416 #define DMA_READ_CHANS 5
4417 #define DMA_WRITE_CHANS 3
4418
4419
4420
4421 #define BCM_PAGE_BITS PAGE_SHIFT
4422 #define BCM_PAGE_SIZE PAGE_SIZE
4423
4424 #define TX_PAGES 2
4425 #define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd))
4426 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1)
4427 #define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES)
4428 #define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES)
4429 #define MAX_TX_BD (TOTAL_TX_BD - 1)
4430 #define BNX_TX_SLACK_SPACE 16
4431
4432 #define RX_PAGES 2
4433 #define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd))
4434 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1)
4435 #define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES)
4436 #define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES)
4437 #define MAX_RX_BD (TOTAL_RX_BD - 1)
4438 #define BNX_RX_SLACK_SPACE (MAX_RX_BD - 8)
4439
4440 #define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \
4441 (USABLE_TX_BD_PER_PAGE - 1)) ? \
4442 (x) + 2 : (x) + 1
4443
4444 #define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD)
4445
4446 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)
4447 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
4448
4449 #define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \
4450 (USABLE_RX_BD_PER_PAGE - 1)) ? \
4451 (x) + 2 : (x) + 1
4452
4453 #define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD)
4454
4455 #define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> 8)
4456 #define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE)
4457
4458
4459 #define CTX_SHIFT 7
4460 #define CTX_SIZE (1 << CTX_SHIFT)
4461 #define CTX_MASK (CTX_SIZE - 1)
4462 #define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT)
4463 #define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT)
4464
4465 #define PHY_CTX_SHIFT 6
4466 #define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT)
4467 #define PHY_CTX_MASK (PHY_CTX_SIZE - 1)
4468 #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT)
4469 #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT)
4470
4471 #define MB_KERNEL_CTX_SHIFT 8
4472 #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT)
4473 #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1)
4474 #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
4475
4476 #define MAX_CID_CNT 0x4000
4477 #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
4478 #define INVALID_CID_ADDR 0xffffffff
4479
4480 #define TX_CID 16
4481 #define RX_CID 0
4482
4483 #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
4484 #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
4485
4486
4487
4488
4489
4490 struct cpu_reg {
4491 u_int32_t mode;
4492 u_int32_t mode_value_halt;
4493 u_int32_t mode_value_sstep;
4494
4495 u_int32_t state;
4496 u_int32_t state_value_clear;
4497
4498 u_int32_t gpr0;
4499 u_int32_t evmask;
4500 u_int32_t pc;
4501 u_int32_t inst;
4502 u_int32_t bp;
4503
4504 u_int32_t spad_base;
4505
4506 u_int32_t mips_view_base;
4507 };
4508
4509 struct fw_info {
4510 u_int32_t ver_major;
4511 u_int32_t ver_minor;
4512 u_int32_t ver_fix;
4513
4514 u_int32_t start_addr;
4515
4516
4517 u_int32_t text_addr;
4518 u_int32_t text_len;
4519 u_int32_t text_index;
4520 u_int32_t *text;
4521
4522
4523 u_int32_t data_addr;
4524 u_int32_t data_len;
4525 u_int32_t data_index;
4526 u_int32_t *data;
4527
4528
4529 u_int32_t sbss_addr;
4530 u_int32_t sbss_len;
4531 u_int32_t sbss_index;
4532 u_int32_t *sbss;
4533
4534
4535 u_int32_t bss_addr;
4536 u_int32_t bss_len;
4537 u_int32_t bss_index;
4538 u_int32_t *bss;
4539
4540
4541 u_int32_t rodata_addr;
4542 u_int32_t rodata_len;
4543 u_int32_t rodata_index;
4544 u_int32_t *rodata;
4545 };
4546
4547 #define RV2P_PROC1 0
4548 #define RV2P_PROC2 1
4549
4550 #define BNX_MIREG(x) ((x & 0x1F) << 16)
4551 #define BNX_MIPHY(x) ((x & 0x1F) << 21)
4552 #define BNX_PHY_TIMEOUT 50
4553
4554 #define BNX_NVRAM_SIZE 0x200
4555 #define BNX_NVRAM_MAGIC 0x669955aa
4556 #define BNX_CRC32_RESIDUAL 0xdebb20e3
4557
4558 #define BNX_TX_TIMEOUT 5
4559
4560 #define BNX_MAX_SEGMENTS 8
4561 #define BNX_DMA_ALIGN 8
4562 #define BNX_DMA_BOUNDARY 0
4563
4564 #define BNX_MIN_MTU 60
4565 #define BNX_MIN_ETHER_MTU 64
4566
4567 #define BNX_MAX_STD_MTU 1500
4568 #define BNX_MAX_STD_ETHER_MTU 1518
4569 #define BNX_MAX_STD_ETHER_MTU_VLAN 1522
4570
4571 #define BNX_MAX_JUMBO_MTU 9000
4572 #define BNX_MAX_JUMBO_ETHER_MTU 9018
4573 #define BNX_MAX_JUMBO_ETHER_MTU_VLAN 9022
4574
4575 #define BNX_MAX_MRU MCLBYTES
4576 #define BNX_MAX_JUMBO_MRU 9216
4577
4578
4579
4580
4581
4582 #define BNX_STATUS_BLK_SZ sizeof(struct status_block)
4583 #define BNX_STATS_BLK_SZ sizeof(struct statistics_block)
4584 #define BNX_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
4585 #define BNX_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
4586
4587 struct bnx_softc
4588 {
4589 struct device bnx_dev;
4590 struct arpcom arpcom;
4591
4592 struct pci_attach_args bnx_pa;
4593 pci_intr_handle_t bnx_ih;
4594
4595 struct ifmedia bnx_ifmedia;
4596
4597 bus_space_tag_t bnx_btag;
4598 bus_space_handle_t bnx_bhandle;
4599 bus_size_t bnx_size;
4600
4601 void *bnx_intrhand;
4602 void *bnx_powerhook;
4603 void *bnx_shutdownhook;
4604
4605
4606 u_int32_t bnx_chipid;
4607
4608
4609 u_int32_t bnx_flags;
4610 #define BNX_PCIX_FLAG 0x01
4611 #define BNX_PCI_32BIT_FLAG 0x02
4612 #define BNX_ONE_TDMA_FLAG 0x04
4613 #define BNX_NO_WOL_FLAG 0x08
4614 #define BNX_USING_DAC_FLAG 0x10
4615 #define BNX_USING_MSI_FLAG 0x20
4616 #define BNX_MFW_ENABLE_FLAG 0x40
4617 #define BNX_ACTIVE_FLAG 0x80
4618
4619
4620 u_int32_t bnx_phy_flags;
4621 #define BNX_PHY_SERDES_FLAG 1
4622 #define BNX_PHY_CRC_FIX_FLAG 2
4623 #define BNX_PHY_PARALLEL_DETECT_FLAG 4
4624 #define BNX_PHY_2_5G_CAPABLE_FLAG 8
4625 #define BNX_PHY_INT_MODE_MASK_FLAG 0x300
4626 #define BNX_PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
4627 #define BNX_PHY_INT_MODE_LINK_READY_FLAG 0x200
4628
4629 int bnx_if_flags;
4630
4631 u_int16_t bus_speed_mhz;
4632 struct flash_spec *bnx_flash_info;
4633 u_int32_t bnx_flash_size;
4634 u_int32_t bnx_shmem_base;
4635 char * bnx_name;
4636
4637
4638 u_int32_t bnx_fw_ver;
4639
4640
4641
4642 u_int16_t bnx_fw_timed_out;
4643
4644
4645
4646 u_int16_t bnx_fw_wr_seq;
4647
4648
4649
4650
4651 u_int16_t bnx_fw_drv_pulse_wr_seq;
4652
4653
4654 u_char eaddr[6];
4655
4656
4657
4658
4659 u_int16_t bnx_tx_quick_cons_trip_int;
4660 u_int16_t bnx_tx_quick_cons_trip;
4661 u_int16_t bnx_rx_quick_cons_trip_int;
4662 u_int16_t bnx_rx_quick_cons_trip;
4663 u_int16_t bnx_comp_prod_trip_int;
4664 u_int16_t bnx_comp_prod_trip;
4665 u_int16_t bnx_tx_ticks_int;
4666 u_int16_t bnx_tx_ticks;
4667 u_int16_t bnx_rx_ticks_int;
4668 u_int16_t bnx_rx_ticks;
4669 u_int16_t bnx_com_ticks_int;
4670 u_int16_t bnx_com_ticks;
4671 u_int16_t bnx_cmd_ticks_int;
4672 u_int16_t bnx_cmd_ticks;
4673 u_int32_t bnx_stats_ticks;
4674
4675
4676 int bnx_phy_addr;
4677
4678
4679 struct mii_data bnx_mii;
4680
4681
4682 u_int16_t rx_prod;
4683 u_int16_t rx_cons;
4684 u_int32_t rx_prod_bseq;
4685 u_int16_t tx_prod;
4686 u_int16_t tx_cons;
4687 u_int32_t tx_prod_bseq;
4688
4689 int bnx_link;
4690 struct timeout bnx_timeout;
4691
4692
4693 u_int32_t max_frame_size;
4694 int mbuf_alloc_size;
4695
4696
4697 u_int32_t rx_mode;
4698
4699
4700 bus_dma_tag_t bnx_dmatag;
4701
4702
4703 bus_dma_segment_t tx_bd_chain_seg[TX_PAGES];
4704 int tx_bd_chain_rseg[TX_PAGES];
4705 bus_dmamap_t tx_bd_chain_map[TX_PAGES];
4706 struct tx_bd *tx_bd_chain[TX_PAGES];
4707 bus_addr_t tx_bd_chain_paddr[TX_PAGES];
4708
4709
4710 bus_dma_segment_t rx_bd_chain_seg[TX_PAGES];
4711 int rx_bd_chain_rseg[TX_PAGES];
4712 bus_dmamap_t rx_bd_chain_map[RX_PAGES];
4713 struct rx_bd *rx_bd_chain[RX_PAGES];
4714 bus_addr_t rx_bd_chain_paddr[RX_PAGES];
4715
4716
4717 bus_dma_segment_t status_seg;
4718 int status_rseg;
4719 bus_dmamap_t status_map;
4720 struct status_block *status_block;
4721 bus_addr_t status_block_paddr;
4722
4723
4724 u_int16_t last_status_idx;
4725 u_int16_t hw_rx_cons;
4726 u_int16_t hw_tx_cons;
4727
4728
4729 bus_dma_segment_t stats_seg;
4730 int stats_rseg;
4731 bus_dmamap_t stats_map;
4732 struct statistics_block *stats_block;
4733 bus_addr_t stats_block_paddr;
4734
4735
4736 bus_dma_segment_t rx_mbuf_seg;
4737 int rx_mbuf_rseg;
4738 bus_dma_segment_t tx_mbuf_seg;
4739 int tx_mbuf_rseg;
4740
4741
4742 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD];
4743 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD];
4744
4745
4746 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD];
4747 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD];
4748
4749
4750 u_int16_t free_rx_bd;
4751 u_int16_t used_tx_bd;
4752
4753
4754 u_int64_t stat_IfHCInOctets;
4755 u_int64_t stat_IfHCInBadOctets;
4756 u_int64_t stat_IfHCOutOctets;
4757 u_int64_t stat_IfHCOutBadOctets;
4758 u_int64_t stat_IfHCInUcastPkts;
4759 u_int64_t stat_IfHCInMulticastPkts;
4760 u_int64_t stat_IfHCInBroadcastPkts;
4761 u_int64_t stat_IfHCOutUcastPkts;
4762 u_int64_t stat_IfHCOutMulticastPkts;
4763 u_int64_t stat_IfHCOutBroadcastPkts;
4764
4765 u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
4766 u_int32_t stat_Dot3StatsCarrierSenseErrors;
4767 u_int32_t stat_Dot3StatsFCSErrors;
4768 u_int32_t stat_Dot3StatsAlignmentErrors;
4769 u_int32_t stat_Dot3StatsSingleCollisionFrames;
4770 u_int32_t stat_Dot3StatsMultipleCollisionFrames;
4771 u_int32_t stat_Dot3StatsDeferredTransmissions;
4772 u_int32_t stat_Dot3StatsExcessiveCollisions;
4773 u_int32_t stat_Dot3StatsLateCollisions;
4774 u_int32_t stat_EtherStatsCollisions;
4775 u_int32_t stat_EtherStatsFragments;
4776 u_int32_t stat_EtherStatsJabbers;
4777 u_int32_t stat_EtherStatsUndersizePkts;
4778 u_int32_t stat_EtherStatsOverrsizePkts;
4779 u_int32_t stat_EtherStatsPktsRx64Octets;
4780 u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets;
4781 u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets;
4782 u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets;
4783 u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets;
4784 u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets;
4785 u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets;
4786 u_int32_t stat_EtherStatsPktsTx64Octets;
4787 u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets;
4788 u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets;
4789 u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets;
4790 u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets;
4791 u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets;
4792 u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets;
4793 u_int32_t stat_XonPauseFramesReceived;
4794 u_int32_t stat_XoffPauseFramesReceived;
4795 u_int32_t stat_OutXonSent;
4796 u_int32_t stat_OutXoffSent;
4797 u_int32_t stat_FlowControlDone;
4798 u_int32_t stat_MacControlFramesReceived;
4799 u_int32_t stat_XoffStateEntered;
4800 u_int32_t stat_IfInFramesL2FilterDiscards;
4801 u_int32_t stat_IfInRuleCheckerDiscards;
4802 u_int32_t stat_IfInFTQDiscards;
4803 u_int32_t stat_IfInMBUFDiscards;
4804 u_int32_t stat_IfInRuleCheckerP4Hit;
4805 u_int32_t stat_CatchupInRuleCheckerDiscards;
4806 u_int32_t stat_CatchupInFTQDiscards;
4807 u_int32_t stat_CatchupInMBUFDiscards;
4808 u_int32_t stat_CatchupInRuleCheckerP4Hit;
4809
4810 #ifdef BNX_DEBUG
4811
4812 int tx_mbuf_alloc;
4813 int rx_mbuf_alloc;
4814
4815
4816 u_int32_t interrupts_generated;
4817 u_int32_t interrupts_handled;
4818 u_int32_t rx_interrupts;
4819 u_int32_t tx_interrupts;
4820
4821 u_int32_t rx_low_watermark;
4822 u_int32_t tx_hi_watermark;
4823 u_int32_t mbuf_alloc_failed;
4824 u_int32_t l2fhdr_status_errors;
4825 u_int32_t unexpected_attentions;
4826 u_int32_t lost_status_block_updates;
4827 #endif
4828 };
4829
4830 #endif
4831
4832 struct bnx_firmware_header {
4833 int bnx_COM_b06FwReleaseMajor;
4834 int bnx_COM_b06FwReleaseMinor;
4835 int bnx_COM_b06FwReleaseFix;
4836 u_int32_t bnx_COM_b06FwStartAddr;
4837 u_int32_t bnx_COM_b06FwTextAddr;
4838 int bnx_COM_b06FwTextLen;
4839 u_int32_t bnx_COM_b06FwDataAddr;
4840 int bnx_COM_b06FwDataLen;
4841 u_int32_t bnx_COM_b06FwRodataAddr;
4842 int bnx_COM_b06FwRodataLen;
4843 u_int32_t bnx_COM_b06FwBssAddr;
4844 int bnx_COM_b06FwBssLen;
4845 u_int32_t bnx_COM_b06FwSbssAddr;
4846 int bnx_COM_b06FwSbssLen;
4847
4848 int bnx_RXP_b06FwReleaseMajor;
4849 int bnx_RXP_b06FwReleaseMinor;
4850 int bnx_RXP_b06FwReleaseFix;
4851 u_int32_t bnx_RXP_b06FwStartAddr;
4852 u_int32_t bnx_RXP_b06FwTextAddr;
4853 int bnx_RXP_b06FwTextLen;
4854 u_int32_t bnx_RXP_b06FwDataAddr;
4855 int bnx_RXP_b06FwDataLen;
4856 u_int32_t bnx_RXP_b06FwRodataAddr;
4857 int bnx_RXP_b06FwRodataLen;
4858 u_int32_t bnx_RXP_b06FwBssAddr;
4859 int bnx_RXP_b06FwBssLen;
4860 u_int32_t bnx_RXP_b06FwSbssAddr;
4861 int bnx_RXP_b06FwSbssLen;
4862
4863 int bnx_TPAT_b06FwReleaseMajor;
4864 int bnx_TPAT_b06FwReleaseMinor;
4865 int bnx_TPAT_b06FwReleaseFix;
4866 u_int32_t bnx_TPAT_b06FwStartAddr;
4867 u_int32_t bnx_TPAT_b06FwTextAddr;
4868 int bnx_TPAT_b06FwTextLen;
4869 u_int32_t bnx_TPAT_b06FwDataAddr;
4870 int bnx_TPAT_b06FwDataLen;
4871 u_int32_t bnx_TPAT_b06FwRodataAddr;
4872 int bnx_TPAT_b06FwRodataLen;
4873 u_int32_t bnx_TPAT_b06FwBssAddr;
4874 int bnx_TPAT_b06FwBssLen;
4875 u_int32_t bnx_TPAT_b06FwSbssAddr;
4876 int bnx_TPAT_b06FwSbssLen;
4877
4878 int bnx_TXP_b06FwReleaseMajor;
4879 int bnx_TXP_b06FwReleaseMinor;
4880 int bnx_TXP_b06FwReleaseFix;
4881 u_int32_t bnx_TXP_b06FwStartAddr;
4882 u_int32_t bnx_TXP_b06FwTextAddr;
4883 int bnx_TXP_b06FwTextLen;
4884 u_int32_t bnx_TXP_b06FwDataAddr;
4885 int bnx_TXP_b06FwDataLen;
4886 u_int32_t bnx_TXP_b06FwRodataAddr;
4887 int bnx_TXP_b06FwRodataLen;
4888 u_int32_t bnx_TXP_b06FwBssAddr;
4889 int bnx_TXP_b06FwBssLen;
4890 u_int32_t bnx_TXP_b06FwSbssAddr;
4891 int bnx_TXP_b06FwSbssLen;
4892
4893 int bnx_rv2p_proc1len;
4894 int bnx_rv2p_proc2len;
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913 };
4914
4915 #endif