REG_RD            661 dev/pci/if_bnx.c 	sc->bnx_chipid =  REG_RD(sc, BNX_MISC_ID);
REG_RD            698 dev/pci/if_bnx.c 	val = REG_RD(sc, BNX_PCICFG_MISC_STATUS);
REG_RD            704 dev/pci/if_bnx.c 		clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS);
REG_RD           1098 dev/pci/if_bnx.c 		val = REG_RD(sc, BNX_EMAC_MDIO_MODE);
REG_RD           1102 dev/pci/if_bnx.c 		REG_RD(sc, BNX_EMAC_MDIO_MODE);
REG_RD           1115 dev/pci/if_bnx.c 		val = REG_RD(sc, BNX_EMAC_MDIO_COMM);
REG_RD           1119 dev/pci/if_bnx.c 			val = REG_RD(sc, BNX_EMAC_MDIO_COMM);
REG_RD           1131 dev/pci/if_bnx.c 		val = REG_RD(sc, BNX_EMAC_MDIO_COMM);
REG_RD           1138 dev/pci/if_bnx.c 		val = REG_RD(sc, BNX_EMAC_MDIO_MODE);
REG_RD           1142 dev/pci/if_bnx.c 		REG_RD(sc, BNX_EMAC_MDIO_MODE);
REG_RD           1177 dev/pci/if_bnx.c 		val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE);
REG_RD           1181 dev/pci/if_bnx.c 		REG_RD(sc, BNX_EMAC_MDIO_MODE);
REG_RD           1194 dev/pci/if_bnx.c 		val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM);
REG_RD           1207 dev/pci/if_bnx.c 		val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE);
REG_RD           1211 dev/pci/if_bnx.c 		REG_RD(sc, BNX_EMAC_MDIO_MODE);
REG_RD           1276 dev/pci/if_bnx.c 		val = REG_RD(sc, BNX_NVM_SW_ARB);
REG_RD           1313 dev/pci/if_bnx.c 		val = REG_RD(sc, BNX_NVM_SW_ARB);
REG_RD           1344 dev/pci/if_bnx.c 	val = REG_RD(sc, BNX_MISC_CFG);
REG_RD           1357 dev/pci/if_bnx.c 			val = REG_RD(sc, BNX_NVM_COMMAND);
REG_RD           1387 dev/pci/if_bnx.c 	val = REG_RD(sc, BNX_MISC_CFG);
REG_RD           1408 dev/pci/if_bnx.c 	val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE);
REG_RD           1429 dev/pci/if_bnx.c 	val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE);
REG_RD           1476 dev/pci/if_bnx.c 		val = REG_RD(sc, BNX_NVM_COMMAND);
REG_RD           1529 dev/pci/if_bnx.c 		val = REG_RD(sc, BNX_NVM_COMMAND);
REG_RD           1531 dev/pci/if_bnx.c 			val = REG_RD(sc, BNX_NVM_READ);
REG_RD           1591 dev/pci/if_bnx.c 		if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE)
REG_RD           1623 dev/pci/if_bnx.c 	val = REG_RD(sc, BNX_NVM_CFG1);
REG_RD           2924 dev/pci/if_bnx.c 	REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS);
REG_RD           2961 dev/pci/if_bnx.c 	val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS);
REG_RD           2977 dev/pci/if_bnx.c 	val = REG_RD(sc, BNX_MISC_ID);
REG_RD           2987 dev/pci/if_bnx.c 		val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG);
REG_RD           3004 dev/pci/if_bnx.c 	val = REG_RD(sc, BNX_PCI_SWAP_DIAG0);
REG_RD           3095 dev/pci/if_bnx.c 	val = REG_RD(sc, BNX_MQ_CONFIG);
REG_RD           3108 dev/pci/if_bnx.c 	val = REG_RD(sc, BNX_TBDR_CONFIG);
REG_RD           3220 dev/pci/if_bnx.c 	REG_RD(sc, BNX_MISC_ENABLE_SET_BITS);
REG_RD           4159 dev/pci/if_bnx.c 	REG_RD(sc, BNX_PCICFG_INT_ACK_CMD);
REG_RD           4179 dev/pci/if_bnx.c 	val = REG_RD(sc, BNX_HC_COMMAND);
REG_RD           4290 dev/pci/if_bnx.c 	REG_RD(sc, BNX_MISC_ENABLE_SET_BITS);
REG_RD           4679 dev/pci/if_bnx.c 	    (REG_RD(sc, BNX_PCICFG_MISC_STATUS) &
REG_RD           5771 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS);
REG_RD           5775 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_DMA_STATUS);
REG_RD           5778 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_CTX_STATUS);
REG_RD           5781 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_EMAC_STATUS);
REG_RD           5785 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_RPM_STATUS);
REG_RD           5788 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_TBDR_STATUS);
REG_RD           5792 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_TDMA_STATUS);
REG_RD           5796 dev/pci/if_bnx.c 	val1 = REG_RD(sc, BNX_HC_STATUS);
REG_RD           5811 dev/pci/if_bnx.c 		    i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
REG_RD           5812 dev/pci/if_bnx.c 		    REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
REG_RD            669 dev/pci/if_bnxreg.h #define BNX_SETBIT(sc, reg, x)		REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
REG_RD            670 dev/pci/if_bnxreg.h #define BNX_CLRBIT(sc, reg, x)		REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))