bnx_shmem_base    687 dev/pci/if_bnx.c 		sc->bnx_shmem_base = REG_RD_IND(sc, BNX_SHM_HDR_ADDR_0);
bnx_shmem_base    689 dev/pci/if_bnx.c 		sc->bnx_shmem_base = HOST_VIEW_SHMEM_BASE;
bnx_shmem_base    691 dev/pci/if_bnx.c 	DBPRINT(sc, BNX_INFO, "bnx_shmem_base = 0x%08X\n", sc->bnx_shmem_base);
bnx_shmem_base    843 dev/pci/if_bnx.c 			val = REG_RD_IND(sc, sc->bnx_shmem_base +
bnx_shmem_base   1697 dev/pci/if_bnx.c 	val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_SHARED_HW_CFG_CONFIG2);
bnx_shmem_base   2450 dev/pci/if_bnx.c 	REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data);
bnx_shmem_base   2455 dev/pci/if_bnx.c 		val = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_FW_MB);
bnx_shmem_base   2470 dev/pci/if_bnx.c 		REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_MB, msg_data);
bnx_shmem_base   2858 dev/pci/if_bnx.c 	mac_hi = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_UPPER);
bnx_shmem_base   2859 dev/pci/if_bnx.c 	mac_lo = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_HW_CFG_MAC_LOWER);
bnx_shmem_base   2973 dev/pci/if_bnx.c 	REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_RESET_SIGNATURE,
bnx_shmem_base   3183 dev/pci/if_bnx.c 	reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE);
bnx_shmem_base   3200 dev/pci/if_bnx.c 	reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_PORT_FEATURE);
bnx_shmem_base   3207 dev/pci/if_bnx.c 	sc->bnx_fw_ver = REG_RD_IND(sc, sc->bnx_shmem_base +
bnx_shmem_base   5069 dev/pci/if_bnx.c 	REG_WR_IND(sc, sc->bnx_shmem_base + BNX_DRV_PULSE_MB, msg);
bnx_shmem_base   4634 dev/pci/if_bnxreg.h 	u_int32_t					bnx_shmem_base;		/* Shared Memory base address */