REG_WR 1071 dev/pci/if_bnx.c REG_WR(sc, BNX_CTX_DATA_ADR, offset); REG_WR 1072 dev/pci/if_bnx.c REG_WR(sc, BNX_CTX_DATA, val); REG_WR 1101 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MDIO_MODE, val); REG_WR 1110 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MDIO_COMM, val); REG_WR 1141 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MDIO_MODE, val); REG_WR 1180 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); REG_WR 1189 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); REG_WR 1210 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); REG_WR 1274 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2); REG_WR 1310 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2); REG_WR 1345 dev/pci/if_bnx.c REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI); REG_WR 1350 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); REG_WR 1351 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_COMMAND, REG_WR 1388 dev/pci/if_bnx.c REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN); REG_WR 1410 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_ACCESS_ENABLE, REG_WR 1432 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_ACCESS_ENABLE, REG_WR 1466 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); REG_WR 1467 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); REG_WR 1468 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_COMMAND, cmd); REG_WR 1519 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); REG_WR 1520 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); REG_WR 1521 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_COMMAND, cmd); REG_WR 1580 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE); REG_WR 1583 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_WRITE, val32); REG_WR 1584 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE); REG_WR 1585 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_COMMAND, cmd); REG_WR 1676 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_CFG1, flash->config1); REG_WR 1677 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_CFG2, flash->config2); REG_WR 1678 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_CFG3, flash->config3); REG_WR 1679 dev/pci/if_bnx.c REG_WR(sc, BNX_NVM_WRITE1, flash->write1); REG_WR 2494 dev/pci/if_bnx.c REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code); REG_WR 2496 dev/pci/if_bnx.c REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code); REG_WR 2501 dev/pci/if_bnx.c REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val); REG_WR 2505 dev/pci/if_bnx.c REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val); REG_WR 2511 dev/pci/if_bnx.c REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET); REG_WR 2513 dev/pci/if_bnx.c REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET); REG_WR 2826 dev/pci/if_bnx.c REG_WR(sc, BNX_CTX_VIRT_ADDR, 0x00); REG_WR 2827 dev/pci/if_bnx.c REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); REG_WR 2833 dev/pci/if_bnx.c REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr); REG_WR 2834 dev/pci/if_bnx.c REG_WR(sc, BNX_CTX_PAGE_TBL, pcid_addr); REG_WR 2894 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MAC_MATCH0, val); REG_WR 2899 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MAC_MATCH1, val); REG_WR 2923 dev/pci/if_bnx.c REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff); REG_WR 2956 dev/pci/if_bnx.c REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, REG_WR 2983 dev/pci/if_bnx.c REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val); REG_WR 3037 dev/pci/if_bnx.c REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); REG_WR 3065 dev/pci/if_bnx.c REG_WR(sc, BNX_DMA_CONFIG, val); REG_WR 3077 dev/pci/if_bnx.c REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, REG_WR 3098 dev/pci/if_bnx.c REG_WR(sc, BNX_MQ_CONFIG, val); REG_WR 3101 dev/pci/if_bnx.c REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val); REG_WR 3102 dev/pci/if_bnx.c REG_WR(sc, BNX_MQ_KNL_WIND_END, val); REG_WR 3105 dev/pci/if_bnx.c REG_WR(sc, BNX_RV2P_CONFIG, val); REG_WR 3111 dev/pci/if_bnx.c REG_WR(sc, BNX_TBDR_CONFIG, val); REG_WR 3139 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val); REG_WR 3145 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK); REG_WR 3148 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_STATUS_ADDR_L, (u_int32_t)(sc->status_block_paddr)); REG_WR 3149 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_STATUS_ADDR_H, REG_WR 3153 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_STATISTICS_ADDR_L, REG_WR 3155 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_STATISTICS_ADDR_H, REG_WR 3159 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int REG_WR 3161 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int REG_WR 3163 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) | REG_WR 3165 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) | REG_WR 3167 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) | REG_WR 3169 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) | REG_WR 3171 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) | REG_WR 3173 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00)); REG_WR 3174 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ REG_WR 3175 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_CONFIG, REG_WR 3180 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW); REG_WR 3216 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); REG_WR 3219 dev/pci/if_bnx.c REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, 0x5ffffff); REG_WR 3575 dev/pci/if_bnx.c REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); REG_WR 3708 dev/pci/if_bnx.c REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD, REG_WR 3712 dev/pci/if_bnx.c REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD, REG_WR 3719 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE); REG_WR 4027 dev/pci/if_bnx.c REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); REG_WR 4158 dev/pci/if_bnx.c REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT); REG_WR 4173 dev/pci/if_bnx.c REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | REG_WR 4176 dev/pci/if_bnx.c REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | REG_WR 4180 dev/pci/if_bnx.c REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW); REG_WR 4232 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu | REG_WR 4283 dev/pci/if_bnx.c REG_WR(sc, BNX_RV2P_CONFIG, val); REG_WR 4286 dev/pci/if_bnx.c REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, REG_WR 4515 dev/pci/if_bnx.c REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); REG_WR 4684 dev/pci/if_bnx.c REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, REG_WR 4753 dev/pci/if_bnx.c REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, REG_WR 4756 dev/pci/if_bnx.c REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, REG_WR 4811 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), REG_WR 4832 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4), REG_WR 4844 dev/pci/if_bnx.c REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode); REG_WR 4848 dev/pci/if_bnx.c REG_WR(sc, BNX_RPM_SORT_USER0, 0x0); REG_WR 4849 dev/pci/if_bnx.c REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode); REG_WR 4850 dev/pci/if_bnx.c REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA); REG_WR 669 dev/pci/if_bnxreg.h #define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) REG_WR 670 dev/pci/if_bnxreg.h #define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))