root/arch/i386/pci/elan520.c

DEFINITIONS

1. elansc_match
2. elansc_attach
3. elansc_tc_read
4. elansc_wdogctl
5. elansc_wdogctl_cb
6. elansc_update_cpuspeed
7. elansc_setperf
8. elansc_cpuspeed
9. elansc_gpio_pin_read
10. elansc_gpio_pin_write
11. elansc_gpio_pin_ctl

    1 /*      $OpenBSD: elan520.c,v 1.13 2007/05/23 11:55:11 markus Exp $     */
    2 /*      $NetBSD: elan520.c,v 1.4 2002/10/02 05:47:15 thorpej Exp $      */
    4 /*-
    5  * Copyright (c) 2002 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Jason R. Thorpe.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by the NetBSD
   22  *      Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   40 /*
   41  * Device driver for the AMD Elan SC520 System Controller.  This attaches
   42  * where the "pchb" driver might normally attach, and provides support for
   43  * extra features on the SC520, such as the watchdog timer and GPIO.
   44  */
   46 #include <sys/param.h>
   47 #include <sys/systm.h>
   48 #include <sys/device.h>
   49 #include <sys/gpio.h>
   50 #include <sys/sysctl.h>
   51 #include <sys/time.h>
   52 #include <sys/timetc.h>
   54 #include <machine/bus.h>
   56 #include <dev/pci/pcivar.h>
   57 #include <dev/pci/pcidevs.h>
   59 #include <dev/gpio/gpiovar.h>
   61 #include <arch/i386/pci/elan520reg.h>
   63 struct elansc_softc {
   64         struct device           sc_dev;
bus_space_tag_t         sc_memt;
bus_space_handle_t      sc_memh;
   68         /* GPIO interface */
   69         struct gpio_chipset_tag sc_gpio_gc;
gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS];
   72         /* GP timer */
   73         struct timecounter      sc_tc;
   74 } *elansc;
   76 int     elansc_match(struct device *, void *, void *);
   77 void    elansc_attach(struct device *, struct device *, void *);
   78 void    elansc_update_cpuspeed(void);
   79 void    elansc_setperf(int);
   80 int     elansc_cpuspeed(int *);
   82 void    elansc_wdogctl(struct elansc_softc *, int, uint16_t);
   83 #define elansc_wdogctl_reset(sc)        elansc_wdogctl(sc, 1, 0)
   84 #define elansc_wdogctl_write(sc, val)   elansc_wdogctl(sc, 0, val)
   85 int     elansc_wdogctl_cb(void *, int);
   87 int     elansc_gpio_pin_read(void *, int);
   88 void    elansc_gpio_pin_write(void *, int, int);
   89 void    elansc_gpio_pin_ctl(void *, int, int);
u_int   elansc_tc_read(struct timecounter *);
   93 struct cfattach elansc_ca = {
   94         sizeof(struct elansc_softc), elansc_match, elansc_attach
   95 };
   97 struct cfdriver elansc_cd = {
NULL, "elansc", DV_DULL
   99 };
  101 static int cpuspeed;
  103 int
elansc_match(struct device *parent, void *match, void *aux)
  105 {
  106         struct pci_attach_args *pa = aux;
  108         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_ELANSC520)
  110                 return (10);    /* beat pchb */
  112         return (0);
  113 }
  115 static const char *elansc_speeds[] = {
  116         "(reserved 00)",
  117         "100MHz",
  118         "133MHz",
  119         "(reserved 11)",
  120 };
  122 #define RSTBITS "\20\x07SCP\x06HRST\x05SRST\x04WDT\x03SD\x02PRGRST\x01PWRGOOD"
  124 void
elansc_attach(struct device *parent, struct device *self, void *aux)
  126 {
  127         struct elansc_softc *sc = (void *) self;
  128         struct pci_attach_args *pa = aux;
  129         struct gpiobus_attach_args gba;
  130         struct timecounter *tc;
uint16_t rev, data;
uint8_t ressta, cpuctl, tmr;
  133         int pin, reg, shift;
sc->sc_memt = pa->pa_memt;
  136         if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, NBPG, 0,
  137             &sc->sc_memh) != 0) {
printf(": unable to map registers\n");
  139                 return;
  140         }
rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID);
cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL);
ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA);
printf(": product %d stepping %d.%d, CPU clock %s, reset %b\n",
  147             (rev & REVID_PRODID) >> REVID_PRODID_SHIFT,
  148             (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT,
  149             (rev & REVID_MINSTEP),
elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK],
ressta, RSTBITS);
  153         /*
  154          * Determine cause of the last reset, and issue a warning if it
  155          * was due to watchdog expiry.
  156          */
  157         if (ressta & RESSTA_WDT_RST_DET)
printf("%s: WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n",
sc->sc_dev.dv_xname);
bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta);
  162         /* Set up the watchdog registers with some defaults. */
elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30);
  165         /* ...and clear it. */
elansc_wdogctl_reset(sc);
wdog_register(sc, elansc_wdogctl_cb);
elansc = sc;
cpu_setperf = elansc_setperf;
cpu_cpuspeed = elansc_cpuspeed;
elansc_update_cpuspeed();
  174         /* Initialize GPIO pins array */
  175         for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) {
sc->sc_gpio_pins[pin].pin_num = pin;
sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT |
GPIO_PIN_OUTPUT;
  180                 /* Read initial state */
reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16);
shift = pin % 16;
data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
  184                 if ((data & (1 << shift)) == 0)
sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT;
  186                 else
sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT;
  188                 if (elansc_gpio_pin_read(sc, pin) == 0)
sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW;
  190                 else
sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH;
  192         }
  194         /* Create controller tag */
sc->sc_gpio_gc.gp_cookie = sc;
sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read;
sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write;
sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl;
gba.gba_name = "gpio";
gba.gba_gc = &sc->sc_gpio_gc;
gba.gba_pins = sc->sc_gpio_pins;
gba.gba_npins = ELANSC_PIO_NPINS;
  205         /* Attach GPIO framework */
config_found(&sc->sc_dev, &gba, gpiobus_print);
  208         /* Disable GP1/2, clear the current count, and set the period to max */
bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR1CTL,
GPTMRCTL_ENB_WR | GPTMRCTL_CONT_CMP |
GPTMRCTL_PSC_SEL | GPTMRCTL_RTG);
bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR1CNT, 0);
bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR1MAXCMPA, 0);
bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR2CTL,
GPTMRCTL_ENB_WR | GPTMRCTL_CONT_CMP);
bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR2CNT, 0);
bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR2MAXCMPA, 0);
tmr = bus_space_read_1(sc->sc_memt, sc->sc_memh, SWTMRCFG);
  222         /* Enable GP1/2 */
bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR1CTL,
GPTMRCTL_ENB | GPTMRCTL_ENB_WR | GPTMRCTL_CONT_CMP |
GPTMRCTL_PSC_SEL | GPTMRCTL_RTG);
bus_space_write_2(sc->sc_memt, sc->sc_memh, GPTMR2CTL,
GPTMRCTL_ENB | GPTMRCTL_ENB_WR | GPTMRCTL_CONT_CMP);
  229         /* Attach timer */
tc = &sc->sc_tc;
tc->tc_get_timecount = elansc_tc_read;
tc->tc_poll_pps = NULL;
tc->tc_counter_mask = ~0;
tc->tc_frequency = (tmr & 1) ? (33000000 / 4) : (33333333 / 4);
tc->tc_name = sc->sc_dev.dv_xname;
tc->tc_quality = 1000;
tc->tc_priv = sc;
tc_init(tc);
  239 }
u_int
elansc_tc_read(struct timecounter *tc)
  243 {
  244         struct elansc_softc *sc = tc->tc_priv;
u_int32_t m1, m2, l;
  247         do {
m1 = bus_space_read_2(sc->sc_memt, sc->sc_memh, GPTMR1CNT);
l = bus_space_read_2(sc->sc_memt, sc->sc_memh, GPTMR2CNT);
m2 = bus_space_read_2(sc->sc_memt, sc->sc_memh, GPTMR1CNT);
  251         } while (m1 != m2);
  253         return ((m1 << 16) | l);
  254 }
  256 void
elansc_wdogctl(struct elansc_softc *sc, int do_reset, uint16_t val)
  258 {
  259         int s;
uint8_t echo_mode;
s = splhigh();
  264         /* Switch off GP bus echo mode. */
echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO);
bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO,
echo_mode & ~GPECHO_GP_ECHO_ENB);
  269         if (do_reset) {
  270                 /* Reset the watchdog. */
bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
WDTMRCTL_RESET1);
bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
WDTMRCTL_RESET2);
  275         } else {
  276                 /* Unlock the register. */
bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
WDTMRCTL_UNLOCK1);
bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
WDTMRCTL_UNLOCK2);
  282                 /* Write the value. */
bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
val);
  285         }
  287         /* Switch GP bus echo mode back. */
bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, echo_mode);
splx(s);
  291 }
  293 static const struct {
  294         int     period;         /* whole seconds */
uint16_t exp;           /* exponent select */
  296 } elansc_wdog_periods[] = {
  297         { 1,    WDTMRCTL_EXP_SEL25 },
  298         { 2,    WDTMRCTL_EXP_SEL26 },
  299         { 4,    WDTMRCTL_EXP_SEL27 },
  300         { 8,    WDTMRCTL_EXP_SEL28 },
  301         { 16,   WDTMRCTL_EXP_SEL29 },
  302         { 32,   WDTMRCTL_EXP_SEL30 },
  303 };
  305 int
elansc_wdogctl_cb(void *self, int period)
  307 {
  308         struct elansc_softc *sc = self;
  309         int i;
  311         if (period == 0) {
elansc_wdogctl_write(sc,
WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30);
  314         } else {
  315                 for (i = 0; i < (sizeof(elansc_wdog_periods) /
  316                     sizeof(elansc_wdog_periods[0])) - 1; i++)
  317                         if (elansc_wdog_periods[i].period >= period)
  318                                 break;
period = elansc_wdog_periods[i].period;
elansc_wdogctl_write(sc, WDTMRCTL_ENB |
WDTMRCTL_WRST_ENB | elansc_wdog_periods[i].exp);
elansc_wdogctl_reset(sc);
  323         }
  324         return (period);
  325 }
  327 void
elansc_update_cpuspeed(void)
  329 {
  330 #ifdef I586_CPU
  331         static const int elansc_mhz[] = { 0, 100, 133, 999 };
  332 #endif
uint8_t cpuctl;
cpuctl = bus_space_read_1(elansc->sc_memt, elansc->sc_memh,
MMCR_CPUCTL);
  337 #ifdef I586_CPU
cpuspeed = elansc_mhz[cpuctl & CPUCTL_CPU_CLK_SPD_MASK];
  339 #endif
  340 }
  342 void
elansc_setperf(int level)
  344 {
uint32_t eflags;
uint8_t cpuctl, speed;
level = (level > 50) ? 100 : 0;
cpuctl = bus_space_read_1(elansc->sc_memt, elansc->sc_memh,
MMCR_CPUCTL);
speed = (level == 100) ? 2 : 1;
  353         if ((cpuctl & CPUCTL_CPU_CLK_SPD_MASK) == speed)
  354                 return;
eflags = read_eflags();
disable_intr();
bus_space_write_1(elansc->sc_memt, elansc->sc_memh, MMCR_CPUCTL,
  359             (cpuctl & ~CPUCTL_CPU_CLK_SPD_MASK) | speed);
enable_intr();
write_eflags(eflags);
elansc_update_cpuspeed();
  364 }
  366 int
elansc_cpuspeed(int *freq)
  368 {
  369         *freq = cpuspeed;
  370         return (0);
  371 }
  373 int
elansc_gpio_pin_read(void *arg, int pin)
  375 {
  376         struct elansc_softc *sc = arg;
  377         int reg, shift;
u_int16_t data;
reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16);
shift = pin % 16;
data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
  384         return ((data >> shift) & 0x1);
  385 }
  387 void
elansc_gpio_pin_write(void *arg, int pin, int value)
  389 {
  390         struct elansc_softc *sc = arg;
  391         int reg, shift;
u_int16_t data;
reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16);
shift = pin % 16;
data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
  397         if (value == 0)
data &= ~(1 << shift);
  399         else if (value == 1)
data |= (1 << shift);
bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data);
  403 }
  405 void
elansc_gpio_pin_ctl(void *arg, int pin, int flags)
  407 {
  408         struct elansc_softc *sc = arg;
  409         int reg, shift;
u_int16_t data;
reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16);
shift = pin % 16;
data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
  415         if (flags & GPIO_PIN_INPUT)
data &= ~(1 << shift);
  417         if (flags & GPIO_PIN_OUTPUT)
data |= (1 << shift);
bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data);
  421 }