1 /* $OpenBSD: elan520reg.h,v 1.3 2007/05/23 11:55:11 markus Exp $ */
2 /* $NetBSD: elan520reg.h,v 1.1 2002/08/12 01:03:14 thorpej Exp $ */
3
4 /*-
5 * Copyright (c) 2002 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * Register definitions for the AMD Elan SC520 System Controller.
42 */
43
44 #ifndef _I386_PCI_ELAN520REG_H_
45 #define _I386_PCI_ELAN520REG_H_
46
47 #define MMCR_BASE_ADDR 0xfffef000
48
49 /*
50 * Am5x86 CPU Registers.
51 */
52 #define MMCR_REVID 0x0000
53 #define MMCR_CPUCTL 0x0002
54
55 #define REVID_PRODID 0xff00 /* product ID */
56 #define REVID_PRODID_SHIFT 8
57 #define REVID_MAJSTEP 0x00f0 /* stepping major */
58 #define REVID_MAJSTEP_SHIFT 4
59 #define REVID_MINSTEP 0x000f /* stepping minor */
60
61 #define PRODID_ELAN_SC520 0x00 /* Elan SC520 */
62
63 #define CPUCTL_CPU_CLK_SPD_MASK 0x03 /* CPU clock speed */
64 #define CPUCTL_CACHE_WR_MODE 0x10 /* cache mode (0 = wb, 1 = wt) */
65
66 /*
67 * General Purpose Bus Registers
68 */
69 #define MMCR_GPECHO 0x0c00 /* GP echo mode */
70 #define MMCR_GPCSDW 0x0c01 /* GP chip sel data width */
71 #define MMCR_CPCSQUAL 0x0c02 /* GP chip sel qualification */
72 #define MMCR_GPCSRT 0x0c08 /* GP chip sel recovery time */
73 #define MMCR_GPCSPW 0x0c09 /* GP chip sel pulse width */
74 #define MMCR_GPCSOFF 0x0c0a /* GP chip sel offset */
75 #define MMCR_GPRDW 0x0c0b /* GP read pulse width */
76 #define MMCR_GPRDOFF 0x0c0c /* GP read offset */
77 #define MMCR_GPWRW 0x0c0d /* GP write pulse width */
78 #define MMCR_GPWROFF 0x0c0e /* GP write offset */
79 #define MMCR_GPALEW 0x0c0f /* GPALE pulse width */
80 #define MMCR_GPALEOFF 0x0c10 /* GPALE offset */
81
82 #define GPECHO_GP_ECHO_ENB 0x01 /* GP bus echo mode enable */
83
84 /*
85 * Programmable Input/Output Registers
86 */
87 #define MMCR_PIOPFS15_0 0x0c20 /* PIO15-PIO0 pin func sel */
88 #define MMCR_PIOPFS31_16 0x0c22 /* PIO31-PIO16 pin func sel */
89 #define MMCR_CSPFS 0x0c24 /* chip sel pin func sel */
90 #define MMCR_CLKSEL 0x0c26 /* clock select */
91 #define MMCR_DSCTL 0x0c28 /* drive strength control */
92 #define MMCR_PIODIR15_0 0x0c2a /* PIO15-PIO0 direction */
93 #define MMCR_PIODIR31_16 0x0c2c /* PIO31-PIO16 direction */
94 #define MMCR_PIODATA15_0 0x0c30 /* PIO15-PIO0 data */
95 #define MMCR_PIODATA31_16 0x0c32 /* PIO31-PIO16 data */
96 #define MMCR_PIOSET15_0 0x0c34 /* PIO15-PIO0 set */
97 #define MMCR_PIOSET31_16 0x0c36 /* PIO31-PIO16 set */
98 #define MMCR_PIOCLR15_0 0x0c38 /* PIO15-PIO0 clear */
99 #define MMCR_PIOCLR31_16 0x0c3a /* PIO31-PIO16 clear */
100
101 #define ELANSC_PIO_NPINS 32 /* total number of PIO pins */
102
103 /*
104 * Watchdog Timer Registers.
105 */
106 #define MMCR_WDTMRCTL 0x0cb0 /* watchdog timer control */
107 #define MMCR_WDTMRCNTL 0x0cb2 /* watchdog timer count low */
108 #define MMCR_WDTMRCNTH 0x0cb4 /* watchdog timer count high */
109
110 #define WDTMRCTL_EXP_SEL_MASK 0x00ff /* exponent select */
111 #define WDTMRCTL_EXP_SEL14 0x0001 /* 496us/492us */
112 #define WDTMRCTL_EXP_SEL24 0x0002 /* 508ms/503ms */
113 #define WDTMRCTL_EXP_SEL25 0x0004 /* 1.02s/1.01s */
114 #define WDTMRCTL_EXP_SEL26 0x0008 /* 2.03s/2.01s */
115 #define WDTMRCTL_EXP_SEL27 0x0010 /* 4.07s/4.03s */
116 #define WDTMRCTL_EXP_SEL28 0x0020 /* 8.13s/8.05s */
117 #define WDTMRCTL_EXP_SEL29 0x0040 /* 16.27s/16.11s */
118 #define WDTMRCTL_EXP_SEL30 0x0080 /* 32.54s/32.21s */
119 #define WDTMRCTL_IRQ_FLG 0x1000 /* interrupt request */
120 #define WDTMRCTL_WRST_ENB 0x4000 /* watchdog timer reset enable */
121 #define WDTMRCTL_ENB 0x8000 /* watchdog timer enable */
122
123 #define WDTMRCTL_UNLOCK1 0x3333
124 #define WDTMRCTL_UNLOCK2 0xcccc
125
126 #define WDTMRCTL_RESET1 0xaaaa
127 #define WDTMRCTL_RESET2 0x5555
128
129 /*
130 * Reset Generation Registers.
131 */
132 #define MMCR_SYSINFO 0x0d70 /* system board information */
133 #define MMCR_RESCFG 0x0d72 /* reset configuration */
134 #define MMCR_RESSTA 0x0d74 /* reset status */
135
136 #define RESCFG_SYS_RST 0x01 /* software system reset */
137 #define RESCFG_GP_RST 0x02 /* assert GP bus reset */
138 #define RESCFG_PRG_RST_ENB 0x04 /* programmable reset enable */
139 #define RESCFG_ICE_ON_RST 0x08 /* enter AMDebug(tm) on reset */
140
141 #define RESSTA_PWRGOOD_DET 0x01 /* POWERGOOD reset detect */
142 #define RESSTA_PRGRST_DET 0x02 /* programmable reset detect */
143 #define RESSTA_SD_RST_DET 0x04 /* CPU shutdown reset detect */
144 #define RESSTA_WDT_RST_DET 0x08 /* watchdog timer reset detect */
145 #define RESSTA_ICE_SRST_DET 0x10 /* AMDebug(tm) soft reset detect */
146 #define RESSTA_ICE_HRST_DET 0x20 /* AMDebug(tm) soft reset detect */
147 #define RESSTA_SCP_RST 0x40 /* SCP reset detect */
148
149 /*
150 * General-Purpose Timers
151 */
152 #define SWTMRCFG 0xc64 /* Software Timer Configuration */
153 #define GPTMR0CTL 0xc72 /* GP Timer 0 mode/control */
154 #define GPTMR0CNT 0xc74 /* GP Timer 0 current count value */
155 #define GPTMR0MAXCMPA 0xc76 /* GP Timer 0 maxcount value A */
156 #define GPTMR0MAXCMPB 0xc78 /* GP Timer 0 maxcount value B */
157 #define GPTMR1CTL 0xc7a /* GP Timer 1 mode/control */
158 #define GPTMR1CNT 0xc7c /* GP Timer 1 current count value */
159 #define GPTMR1MAXCMPA 0xc7e /* GP Timer 1 maxcount value A */
160 #define GPTMR1MAXCMPB 0xc80 /* GP Timer 1 maxcount value B */
161 #define GPTMR2CTL 0xc82 /* GP Timer 2 mode/control */
162 #define GPTMR2CNT 0xc84 /* GP Timer 2 current count value */
163 #define GPTMR2MAXCMPA 0xc8e /* GP Timer 2 maxcount value A */
164 #define GPTMRCTL_CONT_CMP 0x0001 /* GP Timer continuous mode */
165 #define GPTMRCTL_RTG 0x0010 /* GP Timer retrigger */
166 #define GPTMRCTL_PSC_SEL 0x0008 /* GP Timer prescaler */
167 #define GPTMRCTL_ENB 0x8000 /* GP Timer enable */
168 #define GPTMRCTL_ENB_WR 0x4000 /* GP Timer enable bit write */
169
170 #endif /* _I386_PCI_ELAN520REG_H_ */