1 /* $OpenBSD: ncr5380var.h,v 1.11 2006/12/13 21:12:58 miod Exp $ */
2 /* $NetBSD: ncr5380var.h,v 1.6 1996/05/10 18:04:06 gwr Exp $ */
3
4 /*
5 * Copyright (c) 1995 David Jones, Gordon W. Ross
6 * Copyright (c) 1994 Jarle Greipsland
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the authors may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 * 4. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by
22 * David Jones and Gordon Ross
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 /*
37 * This file defines the interface between the machine-dependent
38 * module and the machine-independent ncr5380sbc.c module.
39 */
40
41 #define SCI_CLR_INTR(sc) (*(sc)->sci_iack)
42 #define SCI_BUSY(sc) (*sc->sci_bus_csr & SCI_BUS_BSY)
43
44 /* These are NOT arbitrary, but map to bits in sci_tcmd */
45 #define PHASE_DATA_OUT 0x0
46 #define PHASE_DATA_IN 0x1
47 #define PHASE_COMMAND 0x2
48 #define PHASE_STATUS 0x3
49 #define PHASE_UNSPEC1 0x4
50 #define PHASE_UNSPEC2 0x5
51 #define PHASE_MSG_OUT 0x6
52 #define PHASE_MSG_IN 0x7
53
54 /*
55 * This illegal phase is used to prevent the 5380 from having
56 * a phase-match condition when we don't want one, such as
57 * when setting up the DMA engine or whatever...
58 */
59 #define PHASE_INVALID PHASE_UNSPEC1
60
61
62 /* Per-request state. This is required in order to support reselection. */
63 struct sci_req {
64 struct scsi_xfer *sr_xs; /* Pointer to xfer struct, NULL=unused */
65 int sr_target, sr_lun; /* For fast access */
66 void *sr_dma_hand; /* Current DMA hnadle */
67 u_char *sr_dataptr; /* Saved data pointer */
68 int sr_datalen;
69 int sr_flags; /* Internal error code */
70 #define SR_IMMED 1 /* Immediate command */
71 #define SR_SENSE 2 /* We are getting sense */
72 #define SR_OVERDUE 4 /* Timeout while not current */
73 #define SR_ERROR 8 /* Error occurred */
74 int sr_status; /* Status code from last cmd */
75
76 struct timeout sr_timeout;
77 };
78 #define SCI_OPENINGS 16 /* How many commands we can enqueue. */
79
80
81 struct ncr5380_softc {
82 struct device sc_dev;
83 struct scsi_link sc_link;
84
85 /* Pointers to 5380 registers. See ncr5380reg.h */
86 volatile u_char *sci_r0;
87 volatile u_char *sci_r1;
88 volatile u_char *sci_r2;
89 volatile u_char *sci_r3;
90 volatile u_char *sci_r4;
91 volatile u_char *sci_r5;
92 volatile u_char *sci_r6;
93 volatile u_char *sci_r7;
94
95 /* Functions set from MD code */
96 int (*sc_pio_out)(struct ncr5380_softc *,
97 int, int, u_char *);
98 int (*sc_pio_in)(struct ncr5380_softc *,
99 int, int, u_char *);
100 void (*sc_dma_alloc)(struct ncr5380_softc *);
101 void (*sc_dma_free)(struct ncr5380_softc *);
102
103 void (*sc_dma_setup)(struct ncr5380_softc *);
104 void (*sc_dma_start)(struct ncr5380_softc *);
105 void (*sc_dma_poll)(struct ncr5380_softc *);
106 void (*sc_dma_stop)(struct ncr5380_softc *);
107
108 void (*sc_intr_on)(struct ncr5380_softc *);
109 void (*sc_intr_off)(struct ncr5380_softc *);
110
111 int sc_flags; /* Misc. flags and capabilities */
112 #define NCR5380_PERMIT_RESELECT 1 /* Allow disconnect/reselect */
113 #define NCR5380_FORCE_POLLING 2 /* Do not use interrupts. */
114
115 /* Set bits in this to disable disconnect per-target. */
116 int sc_no_disconnect;
117
118 /* Set bits in this to disable parity for some target. */
119 int sc_parity_disable;
120
121 int sc_min_dma_len; /* Smaller than this is done with PIO */
122
123 /* Begin MI shared data */
124
125 int sc_state;
126 #define NCR_IDLE 0 /* Ready for new work. */
127 #define NCR_WORKING 0x01 /* Some command is in progress. */
128 #define NCR_ABORTING 0x02 /* Bailing out */
129 #define NCR_DOINGDMA 0x04 /* The FIFO data path is active! */
130 #define NCR_DROP_MSGIN 0x10 /* Discard all msgs (parity err detected) */
131
132 /* The request that has the bus now. */
133 struct sci_req *sc_current;
134
135 /* Active data pointer for current SCSI command. */
136 u_char *sc_dataptr;
137 int sc_datalen;
138
139 /* Begin MI private data */
140
141 /* The number of operations in progress on the bus */
142 volatile int sc_ncmds;
143
144 /* Ring buffer of pending/active requests */
145 struct sci_req sc_ring[SCI_OPENINGS];
146 int sc_rr; /* Round-robin scan pointer */
147
148 /* Active requests, by target/LUN */
149 struct sci_req *sc_matrix[8][8];
150
151 /* Message stuff */
152 int sc_prevphase;
153
154 u_int sc_msgpriq; /* Messages we want to send */
155 u_int sc_msgoutq; /* Messages sent during last MESSAGE OUT */
156 u_int sc_msgout; /* Message last transmitted */
157 #define SEND_DEV_RESET 0x01
158 #define SEND_PARITY_ERROR 0x02
159 #define SEND_ABORT 0x04
160 #define SEND_REJECT 0x08
161 #define SEND_INIT_DET_ERR 0x10
162 #define SEND_IDENTIFY 0x20
163 #define SEND_SDTR 0x40
164 #define SEND_WDTR 0x80
165 #define NCR_MAX_MSG_LEN 8
166 u_char sc_omess[NCR_MAX_MSG_LEN];
167 u_char *sc_omp; /* Outgoing message pointer */
168 u_char sc_imess[NCR_MAX_MSG_LEN];
169 u_char *sc_imp; /* Incoming message pointer */
170 };
171
172 void ncr5380_init(struct ncr5380_softc *);
173 void ncr5380_reset_scsibus(struct ncr5380_softc *);
174 int ncr5380_intr(struct ncr5380_softc *);
175 int ncr5380_scsi_cmd(struct scsi_xfer *);
176 int ncr5380_pio_in(struct ncr5380_softc *, int, int, u_char *);
177 int ncr5380_pio_out(struct ncr5380_softc *, int, int, u_char *);
178
179 #ifdef NCR5380_DEBUG
180 struct ncr5380_softc *ncr5380_debug_sc;
181 void ncr5380_trace(char *msg, long val);
182 #define NCR_TRACE(msg, val) ncr5380_trace(msg, val)
183 #else /* NCR5380_DEBUG */
184 #define NCR_TRACE(msg, val) /* nada */
185 #endif /* NCR5380_DEBUG */