root/dev/pci/if_san_te1.h

INCLUDED FROM

DEFINITIONS

1. sdla_te_cfg_t
2. pmc_pmon_t
3. te_signaling_perm_t
4. te_signaling_cfg_t
5. te_signaling_status_t
6. sdla_te_softc_t

    1 /*      $OpenBSD: if_san_te1.h,v 1.5 2005/04/01 21:42:36 canacar Exp $  */
    3 /*-
    4  * Copyright (c) 2001-2004 Sangoma Technologies (SAN)
    5  * All rights reserved.  www.sangoma.com
    6  *
    7  * This code is written by Alex Feldman <al.feldman@sangoma.com> for SAN.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above
   15  *    copyright notice, this list of conditions and the following disclaimer
   16  *    in the documentation and/or other materials provided with the
   17  *    distribution.
   18  * 3. Neither the name of Sangoma Technologies nor the names of its
   19  *    contributors may be used to endorse or promote products derived
   20  *    from this software without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY SANGOMA TECHNOLOGIES AND CONTRIBUTORS
   23  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   24  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   25  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  */
   35 #ifndef __IF_SANTE1_H
   36 #    define     __IF_SANTE1_H
   38 #ifdef SDLA_TE1
   39 # define EXTERN
   40 #else
   41 # define EXTERN extern
   42 #endif
   44 # include <dev/pci/if_san_front_end.h>
   47 #define REG_GLOBAL_CFG                  0x00
   48 #define BIT_GLOBAL_PIO_OE               0x80
   49 #define BIT_GLOBAL_PIO                  0x40
   50 #define BIT_GLOBAL_TRKEN                0x04
   51 #define BIT_GLOBAL_E1                   0x01
   53 #define REG_RLPS_ALOS_DET_PER_0 0x01
   55 #define REG_RECEIVE_OPT                 0x02
   56 #define BIT_RECEIVE_OPT_UNF             0x40
   58 #define REG_TX_TIMING_OPT               0x06
   59 #define BIT_TX_PLLREF1                  0x08
   60 #define BIT_TX_PLLREF0                  0x04
   61 #define BIT_TX_TXELSTBYP                0x01
   63 #define REG_MASTER_DIAG                 0x0A
   64 #define BIT_MASTER_DIAG_PAYLB           0x20
   65 #define BIT_MASTER_DIAG_LINELB          0x10
   66 #define BIT_MASTER_DIAG_DDLB            0x04
   68 #define REG_RESET                       0x0E
   69 #define BIT_RESET                       0x01
   71 #define REG_PRGD_CTRL                   0x0F
   72 #define BIT_PRGD_CTRL_HDLC3             0x80
   73 #define BIT_PRGD_CTRL_HDLC2             0x40
   74 #define BIT_PRGD_CTRL_HDLC1             0x20
   75 #define BIT_PRGD_CTRL_Nx56k_GEN         0x10
   76 #define BIT_PRGD_CTRL_Nx56k_DET         0x08
   77 #define BIT_PRGD_CTRL_RXPATGEN          0x04
   78 #define BIT_PRGD_CTRL_UNF_GEN           0x02
   79 #define BIT_PRGD_CTRL_UNF_DET           0x01
   81 #define REG_CDRC_CFG                    0x10
   82 #define BIT_CDRC_CFG_AMI                0x80
   83 #define BIT_CDRC_CFG_LOS1               0x40
   84 #define BIT_CDRC_CFG_LOS0               0x20
   86 #define REG_CDRC_INT_STATUS             0x12
   87 #define BIT_CDRC_INT_STATUS_LCVI        0x80
   88 #define BIT_CDRC_INT_STATUS_LOSI        0x40
   89 #define BIT_CDRC_INT_STATUS_LCSDI       0x20
   90 #define BIT_CDRC_INT_STATUS_ZNDI        0x10
   91 #define BIT_CDRC_INT_STATUS_LOSV        0x01
   93 #define REG_ALTLOS_STATUS               0x13
   94 #define BIT_ALTLOS_STATUS_ALTLOSE       0x80
   95 #define BIT_ALTLOS_STATUS_ALTLOSI       0x40
   96 #define BIT_ALTLOS_STATUS_ALTLOS        0x01
   98 #define REG_RJAT_CFG                    0x17
   99 #define BIT_RJAT_CENT                   0x10
  101 #define REG_TJAT_CFG                    0x1B
  102 #define BIT_TJAT_CENT                   0x10
  104 #define REG_RX_ELST_CFG                 0x1C
  105 #define MASK_RX_ELST_CFG                0x03
  106 #define BIT_RX_ELST_IR                  0x02
  107 #define BIT_RX_ELST_OR                  0x01
  109 #define REG_TX_ELST_CFG                 0x20
  110 #define MASK_TX_ELST_CFG                0x03
  111 #define BIT_TX_ELST_IR                  0x02
  112 #define BIT_TX_ELST_OR                  0x01
  114 #define REG_BRIF_CFG                    0x30
  115 #define BIT_BRIF_NXDS0_1                0x80
  116 #define BIT_BRIF_NXDS0_0                0x40
  117 #define BIT_BRIF_CMODE                  0x20
  118 #define BIT_BRIF_RATE0                  0x01
  120 #define REG_BRIF_FR_PULSE_CFG           0x31
  121 #define BIT_BRIF_FPMODE                 0x20
  122 #define BIT_BRIF_ROHM                   0x08
  124 #define REG_BRIF_DATA_CFG               0x32
  125 #define BIT_BRIF_DATA_TRI_0             0x01
  127 #define REG_BTIF_CFG                    0x40
  128 #define BIT_BTIF_NXDS0_1                0x80
  129 #define BIT_BTIF_NXDS0_0                0x40
  130 #define BIT_BTIF_CMODE                  0x20
  131 #define BIT_BTIF_DE                     0x10
  132 #define BIT_BTIF_FE                     0x08
  133 #define BIT_BTIF_RATE0                  0x01
  135 #define REG_BTIF_FR_PULSE_CFG           0x41
  136 #define BIT_BTIF_FPMODE                 0x01
  138 #define REG_BTIF_CFG_STATUS             0x42
  139 #define BIT_BTIF_CFG_STATUS_TPTYP       0x80
  140 #define BIT_BTIF_CFG_STATUS_TPTYE       0x40
  141 #define BIT_BTIF_CFG_STATUS_TDI         0x20
  142 #define BIT_BTIF_CFG_STATUS_TSIGI       0x10
  143 #define BIT_BTIF_CFG_STATUS_PTY_EXTD    0x08
  145 #define REG_BTIF_BIT_OFF                0x44
  146 #define BIT_BTIF_BIT_OFF_BOFF_EN        0x08
  147 #define BIT_BTIF_BIT_OFF_BOFF_2         0x04
  148 #define BIT_BTIF_BIT_OFF_BOFF_1         0x02
  149 #define BIT_BTIF_BIT_OFF_BOFF_0         0x01
  151 #define REG_T1_FRMR_CFG                 0x48
  152 #define BIT_T1_FRMR_ESF                 0x20
  153 #define BIT_T1_FRMR_ESFFA               0x10
  154 #define BIT_T1_FRMR_FMS1                0x08
  155 #define BIT_T1_FRMR_FMS0                0x04
  157 #define REG_SIGX_CFG                    0x50
  158 #define BIT_SIGX_ESF                    0x04
  159 #define BIT_SIGX_IND                    0x02
  160 #define BIT_SIGX_PCCE                   0x01
  161 #define BIT_SIGX_SIGE                   0x20
  162 #define BIT_SIGX_COSS                   0x40
  163 #define MASK_SIGX_COSS_30_25            0x3F
  165 #define REG_SIGX_TIMESLOT_IND_STATUS    0x51
  166 #define BIT_SIGX_BUSY                   0x80
  167 #define REG_SIGX_TIMESLOT_IND_ACCESS    0x52
  168 #define BIT_SIGX_TS_IND_ACCESS_READ     0x80
  169 #define REG_SIGX_TIMESLOT_IND_DATA_BUFFER 0x53
  170 #define REG_SIGX_SIGDATA                0x20
  171 #define BIT_SIGX_SIGDATA_A              0x08
  172 #define BIT_SIGX_SIGDATA_B              0x04
  173 #define BIT_SIGX_SIGDATA_C              0x02
  174 #define BIT_SIGX_SIGDATA_D              0x01
  176 #define REG_SIGX_CHANCFG                0x40
  177 #define BIT_SIGX_CHANCFG_RINV1          0x08
  178 #define BIT_SIGX_CHANCFG_RINV0          0x04
  179 #define BIT_SIGX_CHANCFG_RFIX           0x04
  180 #define BIT_SIGX_CHANCFG_RPOL           0x02
  181 #define BIT_SIGX_CHANCFG_RDEBE          0x01
  183 #define REG_T1_XBAS_CFG                 0x54
  184 #define BIT_T1_XBAS_ZCS0                0x01
  185 #define BIT_T1_XBAS_ZCS1                0x02
  186 #define BIT_T1_XBAS_B8ZS                0x20
  187 #define BIT_T1_XBAS_ESF                 0x10
  189 #define REG_T1_XBAS_ALARM_TX            0x55
  190 #define BIT_T1_XBAS_ALARM_TX_XYEL       0x02
  191 #define BIT_T1_XBAS_ALARM_TX_XAIS       0x01
  193 /* PMON Framing Bit Error Count */
  194 #define REG_PMON_BIT_ERROR              0x59
  195 #define BITS_PMON_BIT_ERROR             0x7F
  196 /* PMON OOF/COFA/Far End Block Error Count LSB */
  197 #define REG_PMON_OOF_FEB_LSB_ERROR      0x5A
  198 /* PMON OOF/COFA/Far End Block Error Count MSB */
  199 #define REG_PMON_OOF_FEB_MSB_ERROR      0x5B
  200 #define BITS_PMON_OOF_FEB_MSB_ERROR     0x03
  201 /* PMON Bit Error/CRC Error Count LSB */
  202 #define REG_PMON_BIT_CRC_LSB_ERROR      0x5C
  203 /* PMON Bit Error/CRC Error Count MSB */
  204 #define REG_PMON_BIT_CRC_MSB_ERROR      0x5D
  205 #define BITS_PMON_BIT_CRC_MSB_ERROR     0x03
  206 /* PMON LCV Count LSB */
  207 #define REG_PMON_LCV_LSB_COUNT          0x5E
  208 /* PMON LCV Count MSB */
  209 #define REG_PMON_LCV_MSB_COUNT          0x5F
  210 #define BITS_PMON_LCV_MSB_COUNT         0x1F
  212 #define REG_T1_ALMI_CFG                 0x60
  213 #define BIT_T1_ALMI_CFG_ESF             0x10
  214 #define BIT_T1_ALMI_CFG_FMS1            0x08
  215 #define BIT_T1_ALMI_CFG_FMS0            0x04
  217 #define REG_T1_ALMI_DET_STATUS          0x63
  218 #define BIT_T1_ALMI_DET_STATUS_REDD     0x04
  219 #define BIT_T1_ALMI_DET_STATUS_YELD     0x02
  220 #define BIT_T1_ALMI_DET_STATUS_AISD     0x01
  222 /* T1 XBOC Code */
  223 #define REG_T1_XBOC_CODE                0x67
  224 #define MASK_T1_XBOC_CODE               0x3F
  226 /* T1 RBOC Enable */
  227 #define REG_T1_RBOC_ENABLE              0x6A
  228 #define BIT_T1_RBOC_ENABLE_IDLE         0x04
  229 #define BIT_T1_RBOC_ENABLE_AVC          0x02
  230 #define BIT_T1_RBOC_ENABLE_BOCE         0x01
  232 /* T1 RBOC Code Status */
  233 #define REG_T1_RBOC_CODE_STATUS         0x6B
  234 #define BIT_T1_RBOC_CODE_STATUS_IDLEI   0x80
  235 #define BIT_T1_RBOC_CODE_STATUS_BOCI    0x40
  236 #define MASK_T1_RBOC_CODE_STATUS        0x3F
  238 /* TPSC Indirect Register Access */
  239 #define REG_TPSC_CFG                                    0x6C
  240 #define MASK_TPSC_CFG                                   0x03
  241 #define BIT_TPSC_IND                                    0x02
  242 #define BIT_TPSC_PCCE                                   0x01
  243 #define REG_TPSC_MICRO_ACCESS_STATUS                    0x6D
  244 #define BIT_TPSC_BUSY                                   0x80
  245 #define REG_TPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL       0x6E
  246 #define REG_TPSC_CHANNEL_INDIRECT_DATA_BUFFER           0x6F
  247 #define REG_TPSC_DATA_CTRL_BYTE                         0x20
  248 #define MASK_TPSC_DATA_CTRL_BYTE                        0xFC
  249 #define BIT_TPSC_DATA_CTRL_BYTE_INVERT                  0x80
  250 #define BIT_TPSC_DATA_CTRL_BYTE_IDLE_DS0                0x40
  251 #define BIT_TPSC_DATA_CTRL_BYTE_SIGNINV                 0x10
  252 #define BIT_TPSC_DATA_CTRL_BYTE_LOOP                    0x04
  253 #define BIT_TPSC_DATA_CTRL_BYTE_ZCS0                    0x02
  254 #define BIT_TPSC_DATA_CTRL_BYTE_ZCS1                    0x01
  255 #define REG_TPSC_IDLE_CODE_BYTE                         0x40
  256 #define REG_TPSC_SIGNALING_BYTE                         0x60
  257 #define REG_TPSC_E1_CTRL_BYTE                           0x60
  258 #define BIT_TPSC_E1_CTRL_BYTE_SUBS                      0x80
  259 #define BIT_TPSC_E1_CTRL_BYTE_DS0                       0x40
  260 #define BIT_TPSC_E1_CTRL_BYTE_DS1                       0x20
  261 #define BIT_TPSC_E1_CTRL_BYTE_A                         0x08
  262 #define BIT_TPSC_E1_CTRL_BYTE_B                         0x04
  263 #define BIT_TPSC_E1_CTRL_BYTE_C                         0x02
  264 #define BIT_TPSC_E1_CTRL_BYTE_D                         0x01
  265 #define BIT_TPSC_SIGNALING_BYTE_SIGC_0                  0x80
  266 #define BIT_TPSC_SIGNALING_BYTE_SIGC_1                  0x40
  267 #define BIT_TPSC_SIGNALING_BYTE_DS1                     0x20
  268 #define BIT_TPSC_SIGNALING_BYTE_A                       0x08
  269 #define BIT_TPSC_SIGNALING_BYTE_B                       0x04
  270 #define BIT_TPSC_SIGNALING_BYTE_C                       0x02
  271 #define BIT_TPSC_SIGNALING_BYTE_D                       0x01
  273 /* RPSC Indirect Register Access */
  274 #define REG_RPSC_CFG                                    0x70
  275 #define MASK_RPSC_CFG                                   0x03
  276 #define BIT_RPSC_IND                                    0x02
  277 #define BIT_RPSC_PCCE                                   0x01
  278 #define REG_RPSC_MICRO_ACCESS_STATUS                    0x71
  279 #define BIT_RPSC_BUSY                                   0x80
  280 #define REG_RPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL       0x72
  281 #define REG_RPSC_CHANNEL_INDIRECT_DATA_BUFFER           0x73
  282 #define REG_RPSC_DATA_CTRL_BYTE                         0x20
  283 #define MASK_RPSC_DATA_CTRL_BYTE                        0xFC
  284 #define BIT_RPSC_DATA_CTRL_BYTE_DTRKC                   0x40
  285 #define BIT_RPSC_DATA_CTRL_BYTE_SIGNINV                 0x04
  286 #define REG_RPSC_DATA_COND_BYTE                         0x40
  287 #define REG_RPSC_SIGNALING_BYTE                         0x60
  288 #define BIT_RPSC_SIGNALING_BYTE_A                       0x08
  289 #define BIT_RPSC_SIGNALING_BYTE_B                       0x04
  290 #define BIT_RPSC_SIGNALING_BYTE_C                       0x02
  291 #define BIT_RPSC_SIGNALING_BYTE_D                       0x01
  293 #define REG_E1_TRAN_CFG                 0x80
  294 #define BIT_E1_TRAN_AMI                 0x80
  295 #define BIT_E1_TRAN_GENCRC              0x10
  296 #define BIT_E1_TRAN_FDIS                0x08
  297 #define BIT_E1_TRAN_FEBEDIS             0x04
  298 #define BIT_E1_TRAN_INDIS               0x02
  299 #define BIT_E1_TRAN_XDIS                0x01
  301 #define REG_E1_FRMR_CFG                 0x90
  302 #define BIT_E1_FRMR_CRCEN               0x80
  303 #define BIT_E1_FRMR_CASDIS              0x40
  304 #define BIT_E1_FRMR_REFCRCEN            0x02
  306 /* E1 FRMR Maintenance Mode Options */
  307 #define REG_E1_FRMR_MAINT_OPT           0x91
  308 #define BIT_E1_FRMR_MAINT_OPT_AISC      0x02
  310 /* E1 FRMR framing status */
  311 #define REG_E1_FRMR_FR_STATUS           0x96
  312 #define BIT_E1_FRMR_FR_STATUS_C2NCIWV   0x80
  313 #define BIT_E1_FRMR_FR_STATUS_OOFV      0x40
  314 #define BIT_E1_FRMR_FR_STATUS_OOSMFV    0x20
  315 #define BIT_E1_FRMR_FR_STATUS_OOCMFV    0x10
  316 #define BIT_E1_FRMR_FR_STATUS_OOOFV     0x08
  317 #define BIT_E1_FRMR_FR_STATUS_RAICCRCV  0x04
  318 #define BIT_E1_FRMR_FR_STATUS_CFEBEV    0x02
  319 #define BIT_E1_FRMR_FR_STATUS_V52LINKV  0x01
  321 /* E1 FRMR Maintenance/Alram Status */
  322 #define REG_E1_FRMR_MAINT_STATUS        0x97
  323 #define BIT_E1_FRMR_MAINT_STATUS_RAIV   0x80
  324 #define BIT_E1_FRMR_MAINT_STATUS_RED    0x08
  325 #define BIT_E1_FRMR_MAINT_STATUS_AIS    0x04
  327  /* TDPR Configuration */
  328 #define REG_TDPR_CFG                    0xA8
  329 #define BIT_TDPR_CFG_EN                 0x01
  331 /* TDPR Transmit Data */
  332 #define REG_TDPR_TX_DATA                0xAD
  334 /* RDLC Configuration */
  335 #define REG_RDLC_CFG                    0xC0
  336 #define BIT_RDLC_CFG_EN                 0x01
  338 /* RDLC Interrupt Control */
  339 #define REG_RDLC_INT_CTRL               0xC1
  340 #define BIT_RDLC_INT_CTRL_INTE          0x80
  342 /* RDLC Status */
  343 #define REG_RDLC_STATUS                 0xC2
  344 #define BIT_RDLC_STATUS_PKIN            0x10
  345 #define BIT_RDLC_STATUS_INTR            0x01
  347 /* RDLC Data */
  348 #define REG_RDLC_DATA                   0xC3
  350 #define REG_CSU_CFG                     0xD6
  351 #define MASK_CSU_CFG                    0xC7
  352 #define BIT_CSU_MODE2                   0x04
  353 #define BIT_CSU_MODE1                   0x02
  354 #define BIT_CSU_MODE0                   0x01
  356 /* RLPS Equalization Indirect Data (MSB) */
  357 #define REG_RLPS_IND_DATA_1             0xD8
  358 /* RLPS Equalization Indirect Data */
  359 #define REG_RLPS_IND_DATA_2             0xD9
  360 /* RLPS Equalization Indirect Data */
  361 #define REG_RLPS_IND_DATA_3             0xDA
  362 /* RLPS Equalization Indirect Data (LSB) */
  363 #define REG_RLPS_IND_DATA_4             0xDB
  365 #define REG_EQ_VREF                             0xDC
  367 #define REG_RLPS_FUSE_CTRL_STAT 0xDD
  369 #define REG_XLPG_LINE_CFG               0xF0
  370 #define REG_PRGD_INT_STATUS_EN          0xE1
  371 #define BIT_PRGD_INT_STATUS_EN_SYNCE    0x80
  372 #define BIT_PRGD_INT_STATUS_EN_BEE      0x40
  373 #define BIT_PRGD_INT_STATUS_EN_XFERE    0x20
  374 #define BIT_PRGD_INT_STATUS_EN_SYNCV    0x10
  375 #define BIT_PRGD_INT_STATUS_EN_SYNCI    0x08
  376 #define BIT_PRGD_INT_STATUS_EN_BEI      0x04
  377 #define BIT_PRGD_INT_STATUS_EN_XFERI    0x02
  378 #define BIT_PRGD_INT_STATUS_EN_OVR      0x01
  380 #define REG_XLPG_WAVEFORM_ADDR  0xF2
  382 #define REG_XLPG_WAVEFORM_DATA  0xF3
  384 #define REG_XLPG_TPC                    0xF4
  385 #define BIT_XLPG_TPC_0                  0x01
  387 #define REG_XLPG_TNC                    0xF5
  388 #define BIT_XLPG_TNC_0                  0x01
  390 #define REG_RLPS_CFG_STATUS             0xF8
  391 #define BIT_RLPS_CFG_STATUS_ALOSI       0x80
  392 #define BIT_RLPS_CFG_STATUS_ALOSV       0x40
  393 #define BIT_RLPS_CFG_STATUS_ALOSE       0x20
  394 #define BIT_RLPS_CFG_STATUS_LONGE       0x01
  396 #define REG_RLPS_ALOS_DET_CLR_THR       0xF9
  397 #define BIT_RLPS_ALOS_CLR_THR_2         0x40
  398 #define BIT_RLPS_ALOS_CLR_THR_1         0x20
  399 #define BIT_RLPS_ALOS_CLR_THR_0         0x10
  400 #define BIT_RLPS_ALOS_DET_THR_2         0x04
  401 #define BIT_RLPS_ALOS_DET_THR_1         0x02
  402 #define BIT_RLPS_ALOS_DET_THR_0         0x01
  404 #define REG_RLPS_ALOS_DET_PER   0xFA
  406 #define REG_RLPS_ALOS_CLR_PER   0xFB
  407 #define BIT_RLPS_ALOS_CLR_PER_0 0x01
  409 /* RLPS Equalization Indirect Address    */
  410 #define REG_RLPS_EQ_ADDR                0xFC
  412 /* RLPS Equalization Read/Write Select   */
  413 #define REG_RLPS_EQ_RWB                 0xFD
  414 #define BIT_RLPS_EQ_RWB                 0x80
  416 #define REG_RLPS_EQ_STATUS              0xFE
  418 #define REG_RLPS_EQ_CFG                 0xFF
  419 #define MASK_RLPS_EQ_CFG                0xC7
  420 #define BIT_RLPS_EQ_RESERVED            0x08
  421 #define BIT_RLPS_EQ_FREQ_1              0x02
  422 #define BIT_RLPS_EQ_FREQ_0              0x01
  424 /********************************************/
  425 /************ Interrupt Register ************/
  426 /********************************************/
  427 #define REG_INT_SRC_1                   0x07
  428 #define BITS_TX_INT_SRC_1               0x0C
  429 #define BITS_RX_INT_SRC_1               0xF3
  430 #define BIT_INT_SRC_1_PMON              0x80
  431 #define BIT_INT_SRC_1_PRGD              0x40
  432 #define BIT_INT_SRC_1_FRMR              0x20
  433 #define BIT_INT_SRC_1_SIGX              0x10
  434 #define BIT_INT_SRC_1_APRM              0x08
  435 #define BIT_INT_SRC_1_TJAT              0x04
  436 #define BIT_INT_SRC_1_RJAT              0x02
  437 #define BIT_INT_SRC_1_CDRC              0x01
  439 #define REG_INT_SRC_2                   0x08
  440 #define BITS_TX_INT_SRC_2               0x0F
  441 #define BITS_RX_INT_SRC_2               0xF0
  442 #define BIT_INT_SRC_2_RX_ELST           0x80
  443 #define BIT_INT_SRC_2_RDLC_3            0x40
  444 #define BIT_INT_SRC_2_RDLC_2            0x20
  445 #define BIT_INT_SRC_2_RDLC_1            0x10
  446 #define BIT_INT_SRC_2_TX_ELST           0x08
  447 #define BIT_INT_SRC_2_TDPR_3            0x04
  448 #define BIT_INT_SRC_2_TDPR_2            0x02
  449 #define BIT_INT_SRC_2_TDPR_1            0x01
  451 #define REG_INT_SRC_3                   0x09
  452 #define BITS_TX_INT_SRC_3               0x15
  453 #define BITS_RX_INT_SRC_3               0xEA
  454 #define BIT_INT_SRC_3_IBCD              0x80
  455 #define BIT_INT_SRC_3_PDVD              0x40
  456 #define BIT_INT_SRC_3_RBOC              0x20
  457 #define BIT_INT_SRC_3_XPDE              0x10
  458 #define BIT_INT_SRC_3_ALMI              0x08
  459 #define BIT_INT_SRC_3_TRAN              0x04
  460 #define BIT_INT_SRC_3_RLPS              0x02
  461 #define BIT_INT_SRC_3_BTIF              0x01
  463 #define REG_CDRC_INT_EN                 0x11
  464 #define BIT_CDRC_INT_EN_LCVE            0x80
  465 #define BIT_CDRC_INT_EN_LOSE            0x40
  466 #define BIT_CDRC_INT_EN_LCSDE           0x20
  467 #define BIT_CDRC_INT_EN_ZNDE            0x10
  469 #define REG_CDRC_INT_STATUS             0x12
  470 #define BIT_CDRC_INT_STATUS_LCVI        0x80
  471 #define BIT_CDRC_INT_STATUS_LOSI        0x40
  472 #define BIT_CDRC_INT_STATUS_LCSDI       0x20
  473 #define BIT_CDRC_INT_STATUS_ZNDI        0x10
  474 #define BIT_CDRC_INT_STATUS_LOSV        0x01
  476 #define REG_RJAT_INT_STATUS             0x14
  477 #define BIT_RJAT_INT_STATUS_OVRI        0x02
  478 #define BIT_RJAT_INT_STATUS_UNDI        0x01
  480 #define REG_TJAT_INT_STATUS             0x18
  481 #define BIT_TJAT_INT_STATUS_OVRI        0x02
  482 #define BIT_TJAT_INT_STATUS_UNDI        0x01
  484 #define REG_RX_ELST_INT_EN_STATUS       0x1D
  485 #define BIT_RX_ELST_INT_EN_STATUS_SLIPE 0x04
  486 #define BIT_RX_ELST_INT_EN_STATUS_SLIPD 0x02
  487 #define BIT_RX_ELST_INT_EN_STATUS_SLIPI 0x01
  489 #define REG_TX_ELST_INT_EN_STATUS       0x21
  490 #define BIT_TX_ELST_INT_EN_STATUS_SLIPE 0x04
  491 #define BIT_TX_ELST_INT_EN_STATUS_SLIPD 0x02
  492 #define BIT_TX_ELST_INT_EN_STATUS_SLIPI 0x01
  494 #define REG_T1_FRMR_INT_EN              0x49
  495 #define BIT_T1_FRMR_INT_EN_COFAE        0x20
  496 #define BIT_T1_FRMR_INT_EN_FERE         0x10
  497 #define BIT_T1_FRMR_INT_EN_BEEE         0x08
  498 #define BIT_T1_FRMR_INT_EN_SFEE         0x04
  499 #define BIT_T1_FRMR_INT_EN_MFPE         0x02
  500 #define BIT_T1_FRMR_INT_EN_INFRE        0x01
  502 #define REG_T1_FRMR_INT_STATUS          0x4A
  503 #define BIT_T1_FRMR_INT_STATUS_COFAI    0x80
  504 #define BIT_T1_FRMR_INT_STATUS_FERI     0x40
  505 #define BIT_T1_FRMR_INT_STATUS_BEEI     0x20
  506 #define BIT_T1_FRMR_INT_STATUS_SFEI     0x10
  507 #define BIT_T1_FRMR_INT_STATUS_MFPI     0x08
  508 #define BIT_T1_FRMR_INT_STATUS_INFRI    0x04
  509 #define BIT_T1_FRMR_INT_STATUS_MFP      0x02
  510 #define BIT_T1_FRMR_INT_STATUS_INFR     0x01
  512 #define REG_IBCD_CFG                    0x4C
  513 #define BIT_IBCD_CFG_DSEL1              0x08
  514 #define BIT_IBCD_CFG_DSEL0              0x04
  515 #define BIT_IBCD_CFG_ASEL1              0x02
  516 #define BIT_IBCD_CFG_ASEL0              0x01
  518 #define REG_IBCD_INT_EN_STATUS          0x4D
  519 #define BIT_IBCD_INT_EN_STATUS_LBACP    0x80
  520 #define BIT_IBCD_INT_EN_STATUS_LBDCP    0x40
  521 #define BIT_IBCD_INT_EN_STATUS_LBAE     0x20
  522 #define BIT_IBCD_INT_EN_STATUS_LBDE     0x10
  523 #define BIT_IBCD_INT_EN_STATUS_LBAI     0x08
  524 #define BIT_IBCD_INT_EN_STATUS_LBDI     0x04
  525 #define BIT_IBCD_INT_EN_STATUS_LBA      0x02
  526 #define BIT_IBCD_INT_EN_STATUS_LBD      0x01
  528 #define REG_IBCD_ACTIVATE_CODE          0x4E
  529 #define BIT_IBCD_ACTIVATE_CODE_ACT7     0x80
  530 #define BIT_IBCD_ACTIVATE_CODE_ACT6     0x40
  531 #define BIT_IBCD_ACTIVATE_CODE_ACT5     0x20
  532 #define BIT_IBCD_ACTIVATE_CODE_ACT4     0x10
  533 #define BIT_IBCD_ACTIVATE_CODE_ACT3     0x08
  534 #define BIT_IBCD_ACTIVATE_CODE_ACT2     0x04
  535 #define BIT_IBCD_ACTIVATE_CODE_ACT1     0x02
  536 #define BIT_IBCD_ACTIVATE_CODE_ACT0     0x01
  538 #define REG_IBCD_DEACTIVATE_CODE        0x4F
  539 #define BIT_IBCD_DEACTIVATE_CODE_DACT7  0x80
  540 #define BIT_IBCD_DEACTIVATE_CODE_DACT6  0x40
  541 #define BIT_IBCD_DEACTIVATE_CODE_DACT5  0x20
  542 #define BIT_IBCD_DEACTIVATE_CODE_DACT4  0x10
  543 #define BIT_IBCD_DEACTIVATE_CODE_DACT3  0x08
  544 #define BIT_IBCD_DEACTIVATE_CODE_DACT2  0x04
  545 #define BIT_IBCD_DEACTIVATE_CODE_DACT1  0x02
  546 #define BIT_IBCD_DEACTIVATE_CODE_DACT0  0x01
  548 #define REG_PMON_INT_EN_STATUS          0x58
  549 #define BIT_PMON_INT_EN_STATUS_INTE     0x04
  550 #define BIT_PMON_INT_EN_STATUS_XFER     0x02
  551 #define BIT_PMON_INT_EN_STATUS_OVR      0x01
  553 #define REG_T1_ALMI_INT_EN              0x61
  554 #define BIT_T1_ALMI_INT_EN_FASTD        0x10
  555 #define BIT_T1_ALMI_INT_EN_ACCEL        0x08
  556 #define BIT_T1_ALMI_INT_EN_YELE         0x04
  557 #define BIT_T1_ALMI_INT_EN_REDE         0x02
  558 #define BIT_T1_ALMI_INT_EN_AISE         0x01
  560 #define REG_T1_ALMI_INT_STATUS          0x62
  561 #define BIT_T1_ALMI_INT_STATUS_YELI     0x20
  562 #define BIT_T1_ALMI_INT_STATUS_REDI     0x10
  563 #define BIT_T1_ALMI_INT_STATUS_AISI     0x08
  564 #define BIT_T1_ALMI_INT_STATUS_YEL      0x04
  565 #define BIT_T1_ALMI_INT_STATUS_RED      0x02
  566 #define BIT_T1_ALMI_INT_STATUS_AIS      0x01
  568 #define REG_PDVD_INT_EN_STATUS          0x65
  569 #define BIT_PDVD_INT_EN_STATUS_PDV      0x10
  570 #define BIT_PDVD_INT_EN_STATUS_Z16DI    0x08
  571 #define BIT_PDVD_INT_EN_STATUS_PDVI     0x04
  572 #define BIT_PDVD_INT_EN_STATUS_Z16DE    0x02
  573 #define BIT_PDVD_INT_EN_STATUS_PDVE     0x01
  575 #define REG_XPDE_INT_EN_STATUS          0x69
  576 #define BIT_XPDE_INT_EN_STATUS_STUFE    0x80
  577 #define BIT_XPDE_INT_EN_STATUS_STUFF    0x40
  578 #define BIT_XPDE_INT_EN_STATUS_STUFI    0x20
  579 #define BIT_XPDE_INT_EN_STATUS_PDV      0x10
  580 #define BIT_XPDE_INT_EN_STATUS_Z16DI    0x08
  581 #define BIT_XPDE_INT_EN_STATUS_PDVI     0x04
  582 #define BIT_XPDE_INT_EN_STATUS_Z16DE    0x02
  583 #define BIT_XPDE_INT_EN_STATUS_PDVE     0x01
  585 #define REG_T1_APRM_INT_STATUS          0x7A
  586 #define BIT_T1_APRM_INT_STATUS_INTR     0x01
  588 #define REG_E1_TRAN_INT_EN              0x84
  589 #define BIT_E1_TRAN_INT_EN_SIGMFE       0x10
  590 #define BIT_E1_TRAN_INT_EN_NFASE        0x08
  591 #define BIT_E1_TRAN_INT_EN_MFE          0x04
  592 #define BIT_E1_TRAN_INT_EN_SMFE         0x02
  593 #define BIT_E1_TRAN_INT_EN_FRME         0x01
  595 #define REG_E1_TRAN_INT_STATUS          0x85
  596 #define BIT_E1_TRAN_INT_STATUS_SIGMFI   0x10
  597 #define BIT_E1_TRAN_INT_STATUS_NFASI    0x08
  598 #define BIT_E1_TRAN_INT_STATUS_MFI      0x04
  599 #define BIT_E1_TRAN_INT_STATUS_SMFI     0x02
  600 #define BIT_E1_TRAN_INT_STATUS_FRMI     0x01
  602 #define REG_E1_FRMR_FRM_STAT_INT_EN             0x92
  603 #define BIT_E1_FRMR_FRM_STAT_INT_EN_C2NCIWE     0x80
  604 #define BIT_E1_FRMR_FRM_STAT_INT_EN_OOFE        0x40
  605 #define BIT_E1_FRMR_FRM_STAT_INT_EN_OOSMFE      0x20
  606 #define BIT_E1_FRMR_FRM_STAT_INT_EN_OOCMFE      0x10
  607 #define BIT_E1_FRMR_FRM_STAT_INT_EN_COFAE       0x08
  608 #define BIT_E1_FRMR_FRM_STAT_INT_EN_FERE        0x04
  609 #define BIT_E1_FRMR_FRM_STAT_INT_EN_SMFERE      0x02
  610 #define BIT_E1_FRMR_FRM_STAT_INT_EN_CMFERE      0x01
  612 #define REG_E1_FRMR_M_A_INT_EN          0x93
  613 #define BIT_E1_FRMR_M_A_INT_EN_RAIE     0x80
  614 #define BIT_E1_FRMR_M_A_INT_EN_RMAIE    0x40
  615 #define BIT_E1_FRMR_M_A_INT_EN_AISDE    0x20
  616 #define BIT_E1_FRMR_M_A_INT_EN_REDE     0x08
  617 #define BIT_E1_FRMR_M_A_INT_EN_AISE     0x04
  618 #define BIT_E1_FRMR_M_A_INT_EN_FEBEE    0x02
  619 #define BIT_E1_FRMR_M_A_INT_EN_CRCEE    0x01
  621 /* E1 FRMR Framing status Interrupt Indication */
  622 #define REG_E1_FRMR_FRM_STAT_INT_IND            0x94
  623 #define BIT_E1_FRMR_FRM_STAT_INT_IND_C2NCIWI    0x80
  624 #define BIT_E1_FRMR_FRM_STAT_INT_IND_OOFI       0x40
  625 #define BIT_E1_FRMR_FRM_STAT_INT_IND_OOSMFI     0x20
  626 #define BIT_E1_FRMR_FRM_STAT_INT_IND_OOCMFI     0x10
  627 #define BIT_E1_FRMR_FRM_STAT_INT_IND_COFAI      0x08
  628 #define BIT_E1_FRMR_FRM_STAT_INT_IND_FERI       0x04
  629 #define BIT_E1_FRMR_FRM_STAT_INT_IND_SMFERI     0x02
  630 #define BIT_E1_FRMR_FRM_STAT_INT_IND_CMFERI     0x01
  632 #define REG_E1_FRMR_M_A_INT_IND         0x95
  633 #define BIT_E1_FRMR_M_A_INT_IND_RAII    0x80
  634 #define BIT_E1_FRMR_M_A_INT_IND_FMAII   0x40
  635 #define BIT_E1_FRMR_M_A_INT_IND_AISDI   0x20
  636 #define BIT_E1_FRMR_M_A_INT_IND_REDI    0x08
  637 #define BIT_E1_FRMR_M_A_INT_IND_AISI    0x04
  638 #define BIT_E1_FRMR_M_A_INT_IND_FEBEI   0x02
  639 #define BIT_E1_FRMR_M_A_INT_IND_CRCEI   0x01
  641 #define REG_E1_FRMR_P_A_INT_EN          0x9E
  642 #define BIT_E1_FRMR_P_A_INT_EN_OOOFE    0x80
  643 #define BIT_E1_FRMR_P_A_INT_EN_RAICCRCE 0x40
  644 #define BIT_E1_FRMR_P_A_INT_EN_CFEBEE   0x20
  645 #define BIT_E1_FRMR_P_A_INT_EN_V52LINKE 0x10
  646 #define BIT_E1_FRMR_P_A_INT_EN_IFPE     0x08
  647 #define BIT_E1_FRMR_P_A_INT_EN_ICSMFPE  0x04
  648 #define BIT_E1_FRMR_P_A_INT_EN_ICMFPE   0x02
  649 #define BIT_E1_FRMR_P_A_INT_EN_ISMFPE   0x01
  651 #define REG_E1_FRMR_P_A_INT_STAT                0x9F
  652 #define BIT_E1_FRMR_P_A_INT_STAT_OOOFI          0x80
  653 #define BIT_E1_FRMR_P_A_INT_STAT_RAICCRCI       0x40
  654 #define BIT_E1_FRMR_P_A_INT_STAT_CFEBEI         0x20
  655 #define BIT_E1_FRMR_P_A_INT_STAT_V52LINKI       0x10
  656 #define BIT_E1_FRMR_P_A_INT_STAT_IFPI           0x08
  657 #define BIT_E1_FRMR_P_A_INT_STAT_ICSMFPI        0x04
  658 #define BIT_E1_FRMR_P_A_INT_STAT_ICMFPI         0x02
  659 #define BIT_E1_FRMR_P_A_INT_STAT_ISMFPI         0x01
  662 /*The line code */
  663 #define WAN_LC_AMI           0x01
  664 #define WAN_LC_B8ZS          0x02
  665 #define WAN_LC_HDB3          0x03
  667 /* Framing mode (T1/E1)/Unframed */
  668 #define WAN_FR_ESF           0x01
  669 #define WAN_FR_D4            0x02
  670 #define WAN_FR_ESF_JAPAN     0x03
  671 #define WAN_FR_CRC4          0x04
  672 #define WAN_FR_NCRC4         0x05
  673 #define WAN_FR_UNFRAMED 0x06
  675 /* For T1 only */
  676 #define WAN_T1_LBO_0_DB      0x01
  677 #define WAN_T1_LBO_75_DB     0x02
  678 #define WAN_T1_LBO_15_DB     0x03
  679 #define WAN_T1_LBO_225_DB    0x04
  680 #define WAN_T1_0_110         0x05
  681 #define WAN_T1_110_220       0x06
  682 #define WAN_T1_220_330       0x07
  683 #define WAN_T1_330_440       0x08
  684 #define WAN_T1_440_550       0x09
  685 #define WAN_T1_550_660       0x0A
  687 /* For E1 only */
  688 #define WAN_E1_120           0x0B
  689 #define WAN_E1_75            0x0C
  691 /* Clocking Master/Normal */
  692 #define WAN_NORMAL_CLK  0x01
  693 #define WAN_MASTER_CLK  0x02
  695 #define NUM_OF_T1_CHANNELS      24
  696 #define NUM_OF_E1_TIMESLOTS     31
  697 #define NUM_OF_E1_CHANNELS      32
  698 #define ENABLE_ALL_CHANNELS     0xFFFFFFFF
  700 #define E1_FRAMING_TIMESLOT     0
  701 #define E1_SIGNALING_TIMESLOT   16
  703 /* Alram bit mask */
  704 #define BIT_ALOS_ALARM          0x0001
  705 #define BIT_LOS_ALARM           0x0002
  706 #define BIT_ALTLOS_ALARM        0x0004
  707 #define BIT_OOF_ALARM           0x0008
  708 #define BIT_RED_ALARM           0x0010
  709 #define BIT_AIS_ALARM           0x0020
  710 #define BIT_OOSMF_ALARM         0x0040
  711 #define BIT_OOCMF_ALARM         0x0080
  712 #define BIT_OOOF_ALARM          0x0100
  713 #define BIT_RAI_ALARM           0x0200
  714 #define BIT_YEL_ALARM           0x0400
  715 #define BIT_LOOPUP_CODE         0x2000
  716 #define BIT_LOOPDOWN_CODE       0x4000
  717 #define BIT_TE1_ALARM           0x8000  /* for Windows only */
  719 /* Performamce monitor counter defines */
  720 #define frm_bit_error           pmon1   /* E1/T1   */
  721 #define oof_errors              pmon2   /* T1 only */
  722 #define far_end_blk_errors      pmon2   /* E1 only */
  723 #define bit_errors              pmon3   /* T1 only */
  724 #define crc_errors              pmon3   /* E1 only */
  725 #define lcv                     pmon4   /* E1/T1   */
  727 /* Line loopback modes */
  728 #define WAN_TE1_LINELB_MODE     0x01
  729 #define WAN_TE1_PAYLB_MODE      0x02
  730 #define WAN_TE1_DDLB_MODE       0x03
  731 #define WAN_TE1_TX_LB_MODE      0x04
  733 /* Line loopback activate/deactive modes */
  734 #define WAN_TE1_ACTIVATE_LB     0x01
  735 #define WAN_TE1_DEACTIVATE_LB   0x02
  737 /* Loopback commands (T1.107-1995 p.44) */
  738 #define LINELB_TE1_TIMER        40      /* 40ms */
  739 #define LINELB_CODE_CNT         10      /* no. of repetitions for lb_code */
  740 #define LINELB_CHANNEL_CNT      10      /* no. of repetitions for channel */
  741 #define LINELB_ACTIVATE_CODE    0x07
  742 #define LINELB_DEACTIVATE_CODE  0x1C
  743 #define LINELB_DS3LINE          0x1B
  744 #define LINELB_DS1LINE_1        0x21
  745 #define LINELB_DS1LINE_2        0x22
  746 #define LINELB_DS1LINE_3        0x23
  747 #define LINELB_DS1LINE_4        0x24
  748 #define LINELB_DS1LINE_5        0x25
  749 #define LINELB_DS1LINE_6        0x26
  750 #define LINELB_DS1LINE_7        0x27
  751 #define LINELB_DS1LINE_8        0x28
  752 #define LINELB_DS1LINE_9        0x29
  753 #define LINELB_DS1LINE_10       0x2A
  754 #define LINELB_DS1LINE_11       0x2B
  755 #define LINELB_DS1LINE_12       0x2C
  756 #define LINELB_DS1LINE_13       0x2D
  757 #define LINELB_DS1LINE_14       0x2E
  758 #define LINELB_DS1LINE_15       0x2F
  759 #define LINELB_DS1LINE_16       0x30
  760 #define LINELB_DS1LINE_17       0x31
  761 #define LINELB_DS1LINE_18       0x32
  762 #define LINELB_DS1LINE_19       0x33
  763 #define LINELB_DS1LINE_20       0x34
  764 #define LINELB_DS1LINE_21       0x35
  765 #define LINELB_DS1LINE_22       0x36
  766 #define LINELB_DS1LINE_23       0x37
  767 #define LINELB_DS1LINE_24       0x38
  768 #define LINELB_DS1LINE_25       0x39
  769 #define LINELB_DS1LINE_26       0x3A
  770 #define LINELB_DS1LINE_27       0x3B
  771 #define LINELB_DS1LINE_28       0x3C
  772 #define LINELB_DS1LINE_ALL      0x13
  773 #define LINELB_DS1LINE_MASK     0x1F
  775 /* Interrupt polling delay */
  776 #define POLLING_TE1_TIMER       1000    /* 1 sec */
  778 /* TE1 critical flag */
  779 #define TE_TIMER_RUNNING        0x01
  780 #define TE_TIMER_KILL           0x02
  781 #define LINELB_WAITING          0x03
  782 #define LINELB_CODE_BIT         0x04
  783 #define LINELB_CHANNEL_BIT      0x05
  784 #define TE_CONFIGURED           0x06
  786 #if 0
  787 #define TE_TIMER_RUNNING        0x01
  788 #define TE_TIMER_KILL           0x02
  789 #define LINELB_WAITING          0x04
  790 #define LINELB_CODE_BIT         0x08
  791 #define LINELB_CHANNEL_BIT      0x10
  792 #endif
  794 /* TE1 timer flags */
  795 #define TE_LINELB_TIMER         0x01
  796 #define TE_LINKDOWN_TIMER       0x02
  797 #define TE_SET_INTR             0x03
  798 #define TE_ABCD_UPDATE          0x04
  799 #define TE_LINKUP_TIMER         0x05
  801 /* TE1 T1/E1 interrupt setting delay */
  802 #define INTR_TE1_TIMER          150     /* 50 ms */
  804 #define IS_T1(te_cfg)   ((te_cfg)->media == WAN_MEDIA_T1)
  805 #define IS_E1(te_cfg)   ((te_cfg)->media == WAN_MEDIA_E1)
  807 #define IS_TE1(te_cfg)  (IS_T1(te_cfg) || IS_E1(te_cfg))
  809 #define IS_TE1_UNFRAMED(card)   ((card)->te_cfg.frame == WAN_FR_UNFRAMED)
  811 #define GET_TE_CHANNEL_RANGE(card)                              \
  812                 (IS_T1(&card->te_cfg) ? NUM_OF_T1_CHANNELS :    \
IS_E1(&card->te_cfg) ? NUM_OF_E1_CHANNELS :0)
  815 #define ALOS_ALARM(val)         (val & BIT_ALOS_ALARM) ? "ON" : "OFF"
  816 #define LOS_ALARM(val)          (val & BIT_LOS_ALARM) ? "ON" : "OFF"
  817 #define ALTLOS_ALARM(val)       (val & BIT_ALTLOS_ALARM) ? "ON" : "OFF"
  818 #define OOF_ALARM(val)          (val & BIT_OOF_ALARM) ? "ON" : "OFF"
  819 #define RED_ALARM(val)          (val & BIT_RED_ALARM) ? "ON" : "OFF"
  820 #define AIS_ALARM(val)          (val & BIT_AIS_ALARM) ? "ON" : "OFF"
  821 #define OOSMF_ALARM(val)        (val & BIT_OOSMF_ALARM) ? "ON" : "OFF"
  822 #define OOCMF_ALARM(val)        (val & BIT_OOCMF_ALARM) ? "ON" : "OFF"
  823 #define OOOF_ALARM(val)         (val & BIT_OOOF_ALARM) ? "ON" : "OFF"
  824 #define RAI_ALARM(val)          (val & BIT_RAI_ALARM) ? "ON" : "OFF"
  825 #define YEL_ALARM(val)          (val & BIT_YEL_ALARM) ? "ON" : "OFF"
  827 #define MEDIA_DECODE(val)       (val == WAN_MEDIA_T1) ? "T1" :  \
  828                                 (val == WAN_MEDIA_E1) ? "E1" : "Unknown"
  830 #define LCODE_DECODE(val)       (val == WAN_LC_AMI)  ? "AMI" :  \
  831                                 (val == WAN_LC_B8ZS) ? "B8ZS" : \
  832                                 (val == WAN_LC_HDB3) ? "HDB3" : "Unknown"
  834 #define FRAME_DECODE(val)       (val == WAN_FR_ESF)             ? "ESF"  : \
  835                                 (val == WAN_FR_D4)              ? "D4"   : \
  836                                 (val == WAN_FR_CRC4)            ? "CRC4" : \
  837                                 (val == WAN_FR_NCRC4)   ? "non-CRC4" :  \
  838                                 (val == WAN_FR_UNFRAMED)        ? \
  839                                     "Unframed" : "Unknown"
  841 #define TECLK_DECODE(val)       (val == WAN_NORMAL_CLK) ? "Normal" :    \
  842                                 (val == WAN_MASTER_CLK) ? "Master" : \
  843                                 "Unknown"
  845 #define LBO_DECODE(val)         \
  846         (val == WAN_T1_LBO_0_DB)        ? "0db" :       \
  847         (val == WAN_T1_LBO_75_DB)       ? "7.5db" :     \
  848         (val == WAN_T1_LBO_15_DB)       ? "15dB" :      \
  849         (val == WAN_T1_LBO_225_DB)      ? "22.5dB" :    \
  850         (val == WAN_T1_0_110)   ? "0-110ft" :   \
  851         (val == WAN_T1_110_220) ? "110-220ft" : \
  852         (val == WAN_T1_220_330) ? "220-330ft" : \
  853         (val == WAN_T1_330_440) ? "330-440ft" : \
  854         (val == WAN_T1_440_550) ? "440-550ft" : \
  855         (val == WAN_T1_550_660) ? "550-660ft" : "Unknown"
  858 /*
  859  * T1/E1 configuration structures.
  860  */
  861 typedef struct sdla_te_cfg {
  862         unsigned char media;
  863         unsigned char lcode;
  864         unsigned char frame;
  865         unsigned char lbo;
  866         unsigned char te_clock;
  867         unsigned long active_ch;
  868         unsigned char high_impedance_mode;
  869 } sdla_te_cfg_t;
  871 /* Performamce monitor counters */
  872 typedef struct pmc_pmon {
  873         unsigned long pmon1;
  874         unsigned long pmon2;
  875         unsigned long pmon3;
  876         unsigned long pmon4;
  877 } pmc_pmon_t;
  879 #ifdef _KERNEL
  881 /* 
  882  * Constants for the SET_T1_E1_SIGNALING_CFG/READ_T1_E1_SIGNALING_CFG commands
  883  */
  885 /* the structure for setting the signaling permission */
  886 #pragma pack(1)
  887 typedef struct {
  888         unsigned char time_slot[32];
  889 } te_signaling_perm_t;
  890 #pragma pack()
  892 /* settings for the signaling permission structure */
  893 #define TE_SIG_DISABLED         0x00 /* signaling is disabled */
  894 #define TE_RX_SIG_ENABLED       0x01 /* receive signaling is enabled */
  895 #define TE_TX_SIG_ENABLED       0x02 /* transmit signaling is enabled */
  896 #define TE_SET_TX_SIG_BITS      0x80 /* a flag indicating that outgoing
  897                                         signaling bits should be set */
  899 /* the structure used for the
  900  * SET_T1_E1_SIGNALING_CFG/READ_T1_E1_SIGNALING_CFG command
  901  */
  902 #pragma pack(1)
  903 typedef struct {
  904         /* signaling permission structure */
te_signaling_perm_t sig_perm;
  906         /* loop signaling processing counter */
  907         unsigned char sig_processing_counter;
  908         /* pointer to the signaling permission structure */
  909         unsigned long ptr_te_sig_perm_struct;
  910         /* pointer to the receive signaling structure */
  911         unsigned long ptr_te_Rx_sig_struct;
  912         /* pointer to the transmit signaling structure */
  913         unsigned long ptr_te_Tx_sig_struct;
  914 } te_signaling_cfg_t;
  915 #pragma pack()
  917 /* the structure used for reading and setting the signaling bits */
  918 #pragma pack(1)
  919 typedef struct {
  920         unsigned char time_slot[32];
  921 } te_signaling_status_t;
  922 #pragma pack()
  924 typedef struct {
  925         unsigned char   SIGX_chg_30_25;
  926         unsigned char   SIGX_chg_24_17;
  927         unsigned char   SIGX_chg_16_9;
  928         unsigned char   SIGX_chg_8_1;
  930         unsigned long   ptr_te_sig_perm_off;
  931         unsigned long   ptr_te_Rx_sig_off;
  932         unsigned long   ptr_te_Tx_sig_off;
sdla_te_cfg_t   te_cfg;         /* TE1 hw configuration */
  935         unsigned long   te_alarm;       /* TE1 alarm */
pmc_pmon_t      te_pmon;        /* TE PMON counters */
  937         unsigned char   te_rx_lb_cmd;   /* Received LB cmd */
  938         unsigned long   te_rx_lb_time;  /* Time when LB cmd received */
  940         unsigned char   te_tx_lb_cmd;   /* Received LB cmd */
  941         unsigned long   te_tx_lb_cnt;   /* Time when LB cmd received */
  942         unsigned char   te_critical;    /* T1/E1 critical flag */
  943         struct timeout  te_timer;       /* Timer  */
  944         unsigned char   te_timer_cmd;
  945 } sdla_te_softc_t;
EXTERN int sdla_te_defcfg(void *);
EXTERN int sdla_te_setcfg(struct ifnet *, struct ifmedia *);
EXTERN void sdla_te_settimeslot(void *, unsigned long);
EXTERN unsigned long sdla_te_gettimeslot(void *);
EXTERN short sdla_te_config(void *);
EXTERN void sdla_te_unconfig(void *);
EXTERN unsigned long sdla_te_alarm(void *, int);
EXTERN void sdla_te_alarm_print(void *);
EXTERN void sdla_te_pmon(void *);
EXTERN void sdla_flush_te1_pmon(void *);
EXTERN void sdla_te_intr(void *);
EXTERN int sdla_set_te1_lb_modes(void *, unsigned char, unsigned char);
EXTERN void sdla_te_polling(void *);
EXTERN void sdla_te_timer(void *);
EXTERN int sdla_te_udp(void *, void *, unsigned char *);
EXTERN void aft_green_led_ctrl(void *, int);
  964 #endif /* _KERNEL */
  966 #undef EXTERN
  968 #endif /* __IF_SANTE1_H */