root/arch/i386/include/atomic.h

/* [<][>][^][v][top][bottom][index][help] */

INCLUDED FROM


DEFINITIONS

This source file includes following definitions.
  1. i386_atomic_testset_uq
  2. i386_atomic_testset_ul
  3. i386_atomic_testset_i
  4. i386_atomic_setbits_l
  5. i386_atomic_clearbits_l
  6. i486_atomic_cas_int

    1 /*      $OpenBSD: atomic.h,v 1.6 2007/05/25 15:55:27 art Exp $  */
    2 /* $NetBSD: atomic.h,v 1.1.2.2 2000/02/21 18:54:07 sommerfeld Exp $ */
    3 
    4 /*-
    5  * Copyright (c) 2000 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by RedBack Networks Inc.
   10  *
   11  * Author: Bill Sommerfeld
   12  *
   13  * Redistribution and use in source and binary forms, with or without
   14  * modification, are permitted provided that the following conditions
   15  * are met:
   16  * 1. Redistributions of source code must retain the above copyright
   17  *    notice, this list of conditions and the following disclaimer.
   18  * 2. Redistributions in binary form must reproduce the above copyright
   19  *    notice, this list of conditions and the following disclaimer in the
   20  *    documentation and/or other materials provided with the distribution.
   21  * 3. All advertising materials mentioning features or use of this software
   22  *    must display the following acknowledgement:
   23  *        This product includes software developed by the NetBSD
   24  *        Foundation, Inc. and its contributors.
   25  * 4. Neither the name of The NetBSD Foundation nor the names of its
   26  *    contributors may be used to endorse or promote products derived
   27  *    from this software without specific prior written permission.
   28  *
   29  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   30  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   31  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   32  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   33  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   34  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   35  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   36  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   37  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   38  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   39  * POSSIBILITY OF SUCH DAMAGE.
   40  */
   41 
   42 #ifndef _I386_ATOMIC_H_
   43 #define _I386_ATOMIC_H_
   44 
   45 /*
   46  * Perform atomic operations on memory. Should be atomic with respect
   47  * to interrupts and multiple processors.
   48  *
   49  * void atomic_setbits_int(volatile u_int *a, u_int mask) { *a |= mask; }
   50  * void atomic_clearbits_int(volatile u_int *a, u_int mas) { *a &= ~mask; }
   51  */
   52 #if defined(_KERNEL) && !defined(_LOCORE)
   53 
   54 #ifdef MULTIPROCESSOR
   55 #define LOCK "lock"
   56 #else
   57 #define LOCK
   58 #endif
   59 
   60 static __inline u_int64_t
   61 i386_atomic_testset_uq(volatile u_int64_t *ptr, u_int64_t val)
   62 {
   63         __asm__ volatile ("\n1:\t" LOCK " cmpxchg8b (%1); jnz 1b" : "+A" (val) :
   64             "r" (ptr), "b" ((u_int32_t)val), "c" ((u_int32_t)(val >> 32)));
   65         return val;
   66 }
   67 
   68 static __inline u_int32_t
   69 i386_atomic_testset_ul(volatile u_int32_t *ptr, unsigned long val)
   70 {
   71         __asm__ volatile ("xchgl %0,(%2)" :"=r" (val):"0" (val),"r" (ptr));
   72         return val;
   73 }
   74 
   75 static __inline int
   76 i386_atomic_testset_i(volatile int *ptr, unsigned long val)
   77 {
   78         __asm__ volatile ("xchgl %0,(%2)" :"=r" (val):"0" (val),"r" (ptr));
   79         return val;
   80 }
   81 
   82 static __inline void
   83 i386_atomic_setbits_l(volatile u_int32_t *ptr, unsigned long bits)
   84 {
   85         __asm __volatile(LOCK " orl %1,%0" :  "=m" (*ptr) : "ir" (bits));
   86 }
   87 
   88 static __inline void
   89 i386_atomic_clearbits_l(volatile u_int32_t *ptr, unsigned long bits)
   90 {
   91         bits = ~bits;
   92         __asm __volatile(LOCK " andl %1,%0" :  "=m" (*ptr) : "ir" (bits));
   93 }
   94 
   95 /*
   96  * cas = compare and set
   97  */
   98 static __inline int
   99 i486_atomic_cas_int(volatile u_int *ptr, u_int expect, u_int set)
  100 {
  101         int res;
  102 
  103         __asm volatile(LOCK " cmpxchgl %2, %1" : "=a" (res), "=m" (*ptr)
  104              : "r" (set), "a" (expect), "m" (*ptr) : "memory");
  105 
  106         return (res);
  107 }
  108 
  109 #define atomic_setbits_int i386_atomic_setbits_l
  110 #define atomic_clearbits_int i386_atomic_clearbits_l
  111 
  112 #undef LOCK
  113 
  114 #endif /* defined(_KERNEL) && !defined(_LOCORE) */
  115 #endif /* _I386_ATOMIC_H_ */

/* [<][>][^][v][top][bottom][index][help] */