1 /* $OpenBSD: fxpvar.h,v 1.27 2007/05/28 22:54:04 ckuethe Exp $ */
2 /* $NetBSD: if_fxpvar.h,v 1.1 1997/06/05 02:01:58 thorpej Exp $ */
3
4 /*
5 * Copyright (c) 1995, David Greenman
6 * All rights reserved.
7 *
8 * Modifications to support NetBSD:
9 * Copyright (c) 1997 Jason R. Thorpe. All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice unmodified, this list of conditions, and the following
16 * disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * Id: if_fxpvar.h,v 1.6 1998/08/02 00:29:15 dg Exp
34 */
35
36 /*
37 * Misc. definitions for the Intel EtherExpress Pro/100B PCI Fast
38 * Ethernet driver
39 */
40
41 /*
42 * Number of transmit control blocks. This determines the number
43 * of transmit buffers that can be chained in the CB list.
44 * This must be a power of two.
45 */
46 #define FXP_NTXCB 128
47
48 /*
49 * Minimum and maximum number of receive frame area buffers.
50 */
51 #define FXP_NRFABUFS_MIN 4
52 #define FXP_NRFABUFS_MAX 64 /* These are large so choose wisely. */
53
54 /*
55 * Default maximum time, in microseconds, that an interrupt may be delayed
56 * in an attempt to coalesce interrupts. This is only effective if the Intel
57 * microcode is loaded.
58 */
59 #ifndef FXP_INT_DELAY
60 #define FXP_INT_DELAY 128
61 #endif
62
63 /*
64 * Default number of packets that will be bundled, before an interrupt is
65 * generated. This is only effective if the Intel microcode is loaded.
66 * This is not present in all microcode revisions.
67 */
68 #ifndef FXP_BUNDLE_MAX
69 #define FXP_BUNDLE_MAX 16
70 #endif
71
72 /*
73 * Bit-mask describing minimum size frame that will be bundled.
74 * This is only effetive if the Intel microcode is loaded.
75 * This is not present in all microcode revisions. Disabled by default,
76 * to reduce recieving immediately interrupts from all frames with size less
77 * than 128 bytes.
78 */
79 #ifndef FXP_MIN_SIZE_MASK
80 #define FXP_MIN_SIZE_MASK 0xFFFF
81 #endif
82
83 /*
84 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT
85 * for functional grouping.
86 */
87
88 struct fxp_txsw {
89 struct fxp_txsw *tx_next;
90 struct mbuf *tx_mbuf;
91 bus_dmamap_t tx_map;
92 bus_addr_t tx_off;
93 struct fxp_cb_tx *tx_cb;
94 };
95
96 struct fxp_ctrl {
97 struct fxp_cb_tx tx_cb[FXP_NTXCB];
98 struct fxp_stats stats;
99 union {
100 struct fxp_cb_mcs mcs;
101 struct fxp_cb_ias ias;
102 struct fxp_cb_config cfg;
103 struct fxp_cb_ucode code;
104 } u;
105 };
106
107 struct fxp_softc {
108 struct device sc_dev; /* generic device structures */
109 void *sc_ih; /* interrupt handler cookie */
110 bus_space_tag_t sc_st; /* bus space tag */
111 bus_space_handle_t sc_sh; /* bus space handle */
112 bus_dma_tag_t sc_dmat; /* bus dma tag */
113 struct arpcom sc_arpcom; /* per-interface network data */
114 struct mii_data sc_mii; /* MII media information */
115 struct mbuf *rfa_headm; /* first mbuf in receive frame area */
116 struct mbuf *rfa_tailm; /* last mbuf in receive frame area */
117 int sc_flags; /* misc. flags */
118 #define FXPF_MWI_ENABLE 0x10 /* enable use of PCI MWI command */
119 #define FXPF_DISABLE_STANDBY 0x20 /* currently need to work-around */
120 #define FXPF_UCODE 0x40 /* ucode load already attempted */
121 #define FXPF_RECV_WORKAROUND 0x80 /* receiver lock-up workaround */
122 struct timeout stats_update_to; /* Pointer to timeout structure */
123 int rx_idle_secs; /* # of seconds RX has been idle */
124 struct fxp_cb_tx *cbl_base; /* base of TxCB list */
125 int phy_primary_addr; /* address of primary PHY */
126 int phy_primary_device; /* device type of primary PHY */
127 int phy_10Mbps_only; /* PHY is 10Mbps-only device */
128 int eeprom_size; /* size of serial EEPROM */
129 int rx_bufs; /* how many rx buffers allocated? */
130 void *sc_sdhook; /* shutdownhook */
131 void *sc_powerhook; /* powerhook */
132 struct fxp_txsw txs[FXP_NTXCB];
133 struct fxp_txsw *sc_cbt_cons, *sc_cbt_prod, *sc_cbt_prev;
134 int sc_cbt_cnt;
135 bus_dmamap_t tx_cb_map;
136 bus_dma_segment_t sc_cb_seg;
137 int sc_cb_nseg;
138 struct fxp_ctrl *sc_ctrl;
139 bus_dmamap_t sc_rxmaps[FXP_NRFABUFS_MAX];
140 int sc_rxfree;
141 u_int32_t sc_revision; /* chip revision */
142 u_int16_t sc_int_delay; /* interrupt delay value for ucode */
143 u_int16_t sc_bundle_max; /* max # frames per interrupt (ucode) */
144 u_int16_t sc_min_size_mask; /* bit-mask describing the minimum
145 * size of frame that will be bundled */
146 };
147
148 /* Macros to ease CSR access. */
149 #define CSR_READ_1(sc, reg) \
150 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
151 #define CSR_READ_2(sc, reg) \
152 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
153 #define CSR_READ_4(sc, reg) \
154 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
155 #define CSR_WRITE_1(sc, reg, val) \
156 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
157 #define CSR_WRITE_2(sc, reg, val) \
158 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
159 #define CSR_WRITE_4(sc, reg, val) \
160 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
161
162 extern int fxp_intr(void *);
163 extern int fxp_attach(struct fxp_softc *, const char *);
164
165 #define FXP_RXMAP_GET(sc) ((sc)->sc_rxmaps[(sc)->sc_rxfree++])
166 #define FXP_RXMAP_PUT(sc,map) ((sc)->sc_rxmaps[--(sc)->sc_rxfree] = (map))
167
168 #define FXP_TXCB_SYNC(sc, txs, p) \
169 bus_dmamap_sync((sc)->sc_dmat, (sc)->tx_cb_map, (txs)->tx_off, \
170 sizeof(struct fxp_cb_tx), (p))
171
172 #define FXP_MCS_SYNC(sc, p) \
173 bus_dmamap_sync((sc)->sc_dmat, (sc)->tx_cb_map, \
174 offsetof(struct fxp_ctrl, u.mcs), sizeof(struct fxp_cb_mcs), (p))
175
176 #define FXP_IAS_SYNC(sc, p) \
177 bus_dmamap_sync((sc)->sc_dmat, (sc)->tx_cb_map, \
178 offsetof(struct fxp_ctrl, u.ias), sizeof(struct fxp_cb_ias), (p))
179
180 #define FXP_CFG_SYNC(sc, p) \
181 bus_dmamap_sync((sc)->sc_dmat, (sc)->tx_cb_map, \
182 offsetof(struct fxp_ctrl, u.cfg), sizeof(struct fxp_cb_config), (p))
183
184 #define FXP_UCODE_SYNC(sc, p) \
185 bus_dmamap_sync((sc)->sc_dmat, (sc)->tx_cb_map, \
186 offsetof(struct fxp_ctrl, u.code), sizeof(struct fxp_cb_ucode), (p))
187
188 #define FXP_STATS_SYNC(sc, p) \
189 bus_dmamap_sync((sc)->sc_dmat, (sc)->tx_cb_map, \
190 offsetof(struct fxp_ctrl, stats), sizeof(struct fxp_stats), (p))
191
192 #define FXP_MBUF_SYNC(sc, m, p) \
193 bus_dmamap_sync((sc)->sc_dmat, (m), 0, (m)->dm_mapsize, (p))