1 /* $OpenBSD: cgsixreg.h,v 1.9 2006/06/02 20:00:56 miod Exp $ */
2
3 /*
4 * Copyright (c) 2002 Jason L. Wright (jason@thought.net)
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 union bt_cmap {
30 u_int8_t cm_map[256][3]; /* 256 r/b/g entries */
31 u_int32_t cm_chip[256 * 3 / 4]; /* the way the chip is loaded */
32 };
33
34 #define BT_ADDR 0x00 /* map address register */
35 #define BT_CMAP 0x04 /* colormap data register */
36 #define BT_CTRL 0x08 /* control register */
37 #define BT_OMAP 0x0c /* overlay (cursor) map register */
38
39 #define BT_D4M3(x) ((((x) >> 2) << 1) + ((x) >> 2)) /* (x / 4) * 3 */
40 #define BT_D4M4(x) ((x) & ~3) /* (x / 4) * 4 */
41
42 #define CGSIX_ROM_OFFSET 0x000000
43 #define CGSIX_BT_OFFSET 0x200000
44 #define CGSIX_BT_SIZE (sizeof(u_int32_t) * 4)
45 #define CGSIX_DHC_OFFSET 0x240000
46 #define CGSIX_ALT_OFFSET 0x280000
47 #define CGSIX_FHC_OFFSET 0x300000
48 #define CGSIX_FHC_SIZE (sizeof(u_int32_t) * 1)
49 #define CGSIX_THC_OFFSET 0x301000
50 #define CGSIX_THC_SIZE (sizeof(u_int32_t) * 640)
51 #define CGSIX_FBC_OFFSET 0x700000
52 #define CGSIX_FBC_SIZE 0x1000
53 #define CGSIX_TEC_OFFSET 0x701000
54 #define CGSIX_TEC_SIZE (sizeof(u_int32_t) * 3)
55 #define CGSIX_VID_OFFSET 0x800000
56 #define CGSIX_VID_SIZE (1024 * 1024)
57
58 #define CG6_FHC 0x0 /* fhc register */
59
60 #define FHC_FBID_MASK 0xff000000 /* frame buffer id */
61 #define FHC_FBID_SHIFT 24
62 #define FHC_REV_MASK 0x00f00000 /* revision */
63 #define FHC_REV_SHIFT 20
64 #define FHC_FROP_DISABLE 0x00080000 /* disable fast rasterop */
65 #define FHC_ROW_DISABLE 0x00040000 /* ??? */
66 #define FHC_SRC_DISABLE 0x00020000 /* ??? */
67 #define FHC_DST_DISABLE 0x00010000 /* disable dst cache */
68 #define FHC_RESET 0x00008000 /* ??? */
69 #define FHC_LEBO 0x00002000 /* set little endian order */
70 #define FHC_RES_MASK 0x00001800 /* resolution: */
71 #define FHC_RES_1024 0x00000000 /* 1024x768 */
72 #define FHC_RES_1152 0x00000800 /* 1152x900 */
73 #define FHC_RES_1280 0x00001000 /* 1280x1024 */
74 #define FHC_RES_1600 0x00001800 /* 1600x1200 */
75 #define FHC_CPU_MASK 0x00000600 /* cpu type: */
76 #define FHC_CPU_SPARC 0x00000000 /* sparc */
77 #define FHC_CPU_68020 0x00000200 /* 68020 */
78 #define FHC_CPU_386 0x00000400 /* i386 */
79 #define FHC_TEST 0x00000100 /* test window */
80 #define FHC_TESTX_MASK 0x000000f0 /* test window X */
81 #define FHC_TESTX_SHIFT 4
82 #define FHC_TESTY_MASK 0x0000000f /* test window Y */
83 #define FHC_TESTY_SHIFT 0
84
85 #define CG6_FBC_MODE 0x004 /* mode setting */
86 #define CG6_FBC_CLIP 0x008 /* ??? */
87 #define CG6_FBC_S 0x010 /* global status */
88 #define CG6_FBC_DRAW 0x014 /* drawing pipeline status */
89 #define CG6_FBC_BLIT 0x018 /* blitter status */
90 #define CG6_FBC_FONT 0x01c /* font */
91 #define CG6_FBC_X0 0x080 /* blitter, src llx */
92 #define CG6_FBC_Y0 0x084 /* blitter, src lly */
93 #define CG6_FBC_Z0 0x088 /* blitter, src llz */
94 #define CB6_FBC_C0 0x08c /* blitter, src llcolor */
95 #define CG6_FBC_X1 0x090 /* blitter, src urx */
96 #define CG6_FBC_Y1 0x094 /* blitter, src ury */
97 #define CG6_FBC_Z1 0x098 /* blitter, src urz */
98 #define CB6_FBC_C1 0x09c /* blitter, src urcolor */
99 #define CG6_FBC_X2 0x0a0 /* blitter, dst llx */
100 #define CG6_FBC_Y2 0x0a4 /* blitter, dst lly */
101 #define CG6_FBC_Z2 0x0a8 /* blitter, dst llz */
102 #define CB6_FBC_C2 0x0ac /* blitter, dst llcolor */
103 #define CG6_FBC_X3 0x0b0 /* blitter, dst urx */
104 #define CG6_FBC_Y3 0x0b4 /* blitter, dst ury */
105 #define CG6_FBC_Z3 0x0b8 /* blitter, dst urz */
106 #define CB6_FBC_C3 0x0bc /* blitter, dst urcolor */
107 #define CG6_FBC_OFFX 0x0c0 /* x offset for drawing */
108 #define CG6_FBC_OFFY 0x0c4 /* y offset for drawing */
109 #define CG6_FBC_INCX 0x0d0 /* x increment */
110 #define CG6_FBC_INCY 0x0d4 /* y increment */
111 #define CG6_FBC_CLIPMINX 0x0e0 /* clip rectangle llx */
112 #define CG6_FBC_CLIPMINY 0x0e4 /* clip rectangle lly */
113 #define CG6_FBC_CLIPMAXX 0x0f0 /* clip rectangle urx */
114 #define CG6_FBC_CLIPMAXY 0x0f4 /* clip rectangle ury */
115 #define CG6_FBC_FG 0x100 /* fg value for rop */
116 #define CG6_FBC_BG 0x104 /* bg value for rop */
117 #define CG6_FBC_ALU 0x108 /* operation */
118 #define CG6_FBC_PM 0x10c /* */
119 #define CG6_FBC_PIXELM 0x110 /* */
120 #define CG6_FBC_PATALIGN 0x11c /* */
121 #define CG6_FBC_PATTERN 0x120 /* 8 u_int32_t pattern */
122 #define CG6_FBC_APOINTX 0x800 /* */
123 #define CG6_FBC_APOINTY 0x804 /* */
124 #define CG6_FBC_APOINTZ 0x808 /* */
125 #define CG6_FBC_RPOINTX 0x810 /* */
126 #define CG6_FBC_RPOINTY 0x814 /* */
127 #define CG6_FBC_RPOINTZ 0x818 /* */
128 #define CG6_FBC_POINTR 0x830 /* */
129 #define CG6_FBC_POINTG 0x834 /* */
130 #define CG6_FBC_POINTB 0x838 /* */
131 #define CG6_FBC_POINTA 0x83c /* */
132 #define CG6_FBC_ALINEX 0x840 /* */
133 #define CG6_FBC_ALINEY 0x844 /* */
134 #define CG6_FBC_ALINEZ 0x848 /* */
135 #define CG6_FBC_RLINEX 0x850 /* */
136 #define CG6_FBC_RLINEY 0x854 /* */
137 #define CG6_FBC_RLINEZ 0x858 /* */
138 #define CG6_FBC_LINER 0x870 /* */
139 #define CG6_FBC_LINEG 0x874 /* */
140 #define CG6_FBC_LINEB 0x878 /* */
141 #define CG6_FBC_LINEA 0x87c /* */
142 #define CG6_FBC_ATRIX 0x880 /* */
143 #define CG6_FBC_ATRIY 0x884 /* */
144 #define CG6_FBC_ATRIZ 0x888 /* */
145 #define CG6_FBC_RTRIX 0x890 /* */
146 #define CG6_FBC_RTRIY 0x894 /* */
147 #define CG6_FBC_RTRIZ 0x898 /* */
148 #define CG6_FBC_TRIR 0x8b0 /* */
149 #define CG6_FBC_TRIG 0x8b4 /* */
150 #define CG6_FBC_TRIB 0x8b8 /* */
151 #define CG6_FBC_TRIA 0x8bc /* */
152 #define CG6_FBC_AQUADX 0x8c0 /* */
153 #define CG6_FBC_AQUADY 0x8c4 /* */
154 #define CG6_FBC_AQUADZ 0x8c8 /* */
155 #define CG6_FBC_RQUADX 0x8d0 /* */
156 #define CG6_FBC_RQUADY 0x8d4 /* */
157 #define CG6_FBC_RQUADZ 0x8d8 /* */
158 #define CG6_FBC_QUADR 0x8f0 /* */
159 #define CG6_FBC_QUADG 0x8f4 /* */
160 #define CG6_FBC_QUADB 0x8f8 /* */
161 #define CG6_FBC_QUADA 0x8fc /* */
162 #define CG6_FBC_ARECTX 0x900 /* rectangle drawing, x coord */
163 #define CG6_FBC_ARECTY 0x904 /* rectangle drawing, y coord */
164 #define CG6_FBC_ARECTZ 0x908 /* rectangle drawing, z coord */
165 #define CG6_FBC_RRECTX 0x910 /* */
166 #define CG6_FBC_RRECTY 0x914 /* */
167 #define CG6_FBC_RRECTZ 0x918 /* */
168 #define CG6_FBC_RRECTR 0x930 /* */
169 #define CG6_FBC_RRECTG 0x934 /* */
170 #define CG6_FBC_RRECTB 0x938 /* */
171 #define CG6_FBC_RRECTA 0x938 /* */
172
173 #define FBC_MODE_VAL ( \
174 0x00200000 /* GX_BLIT_SRC */ \
175 | 0x00020000 /* GX_MODE_COLOR8 */ \
176 | 0x00008000 /* GX_DRAW_RENDER */ \
177 | 0x00002000 /* GX_BWRITE0_ENABLE */ \
178 | 0x00001000 /* GX_BWRITE1_DISABLE */ \
179 | 0x00000200 /* GX_BREAD_0 */ \
180 | 0x00000080 /* GX_BDISP_0 */ \
181 )
182 #define FBC_MODE_MASK ( \
183 0x00300000 /* GX_BLIT_ALL */ \
184 | 0x00060000 /* GX_MODE_ALL */ \
185 | 0x00018000 /* GX_DRAW_ALL */ \
186 | 0x00006000 /* GX_BWRITE0_ALL */ \
187 | 0x00001800 /* GX_BWRITE1_ALL */ \
188 | 0x00000600 /* GX_BREAD_ALL */ \
189 | 0x00000180 /* GX_BDISP_ALL */ \
190 )
191
192 #define FBC_S_GXINPROGRESS 0x10000000 /* drawing in progress */
193
194 #define FBC_BLIT_UNKNOWN 0x80000000 /* ??? */
195 #define FBC_BLIT_GXFULL 0x20000000 /* queue is full */
196
197 #define FBC_DRAW_UNKNOWN 0x80000000 /* ??? */
198 #define FBC_DRAW_GXFULL 0x20000000
199
200 /* Value for the alu register for screen-to-screen copies */
201 #define FBC_ALU_COPY ( \
202 0x80000000 /* GX_PLANE_ONES (ignore planemask register) */ \
203 | 0x20000000 /* GX_PIXEL_ONES (ignore pixelmask register) */ \
204 | 0x00800000 /* GX_ATTR_SUPP (function unknown) */ \
205 | 0x00000000 /* GX_RAST_BOOL (function unknown) */ \
206 | 0x00000000 /* GX_PLOT_PLOT (function unknown) */ \
207 | 0x08000000 /* GX_PATTERN_ONES (ignore pattern) */ \
208 | 0x01000000 /* GX_POLYG_OVERLAP (unsure - handle overlap?) */ \
209 | 0x0000cccc /* ALU = src */ \
210 )
211
212 /* Value for the alu register for region fills */
213 #define FBC_ALU_FILL ( \
214 0x80000000 /* GX_PLANE_ONES (ignore planemask register) */ \
215 | 0x20000000 /* GX_PIXEL_ONES (ignore pixelmask register) */ \
216 | 0x00800000 /* GX_ATTR_SUPP (function unknown) */ \
217 | 0x00000000 /* GX_RAST_BOOL (function unknown) */ \
218 | 0x00000000 /* GX_PLOT_PLOT (function unknown) */ \
219 | 0x08000000 /* GX_PATTERN_ONES (ignore pattern) */ \
220 | 0x01000000 /* GX_POLYG_OVERLAP (unsure - handle overlap?) */ \
221 | 0x0000ff00 /* ALU = fg color */ \
222 )
223
224 /* Value for the alu register for toggling an area */
225 #define FBC_ALU_FLIP ( \
226 0x80000000 /* GX_PLANE_ONES (ignore planemask register) */ \
227 | 0x20000000 /* GX_PIXEL_ONES (ignore pixelmask register) */ \
228 | 0x00800000 /* GX_ATTR_SUPP (function unknown) */ \
229 | 0x00000000 /* GX_RAST_BOOL (function unknown) */ \
230 | 0x00000000 /* GX_PLOT_PLOT (function unknown) */ \
231 | 0x08000000 /* GX_PATTERN_ONES (ignore pattern) */ \
232 | 0x01000000 /* GX_POLYG_OVERLAP (unsure - handle overlap?) */ \
233 | 0x00005555 /* ALU = ~dst */ \
234 )
235
236 #define CG6_TEC_MV 0x0 /* matrix stuff */
237 #define CG6_TEC_CLIP 0x4 /* clipping stuff */
238 #define CG6_TEC_VDC 0x8 /* ??? */
239
240 #define CG6_THC_HSYNC1 0x800 /* horizontal sync timing */
241 #define CG6_THC_HSYNC2 0x804 /* more hsync timing */
242 #define CG6_THC_HSYNC3 0x808 /* yet more hsync timing */
243 #define CG6_THC_VSYNC1 0x80c /* vertical sync timing */
244 #define CG6_THC_VSYNC2 0x810 /* only two of these */
245 #define CG6_THC_REFRESH 0x814 /* refresh counter */
246 #define CG6_THC_MISC 0x818 /* misc control/status */
247 #define CG6_THC_CURSXY 0x8fc /* cursor x/y, 16 bit each */
248 #define CG6_THC_CURSMASK 0x900 /* cursor mask bits */
249 #define CG6_THC_CURSBITS 0x980 /* cursor bits */
250
251 /* cursor x/y position for 'off' */
252 #define THC_CURSOFF ((65536-32) | ((65536-32) << 16))
253
254 #define THC_MISC_REV_M 0x000f0000 /* chip revision */
255 #define THC_MISC_REV_S 16
256 #define THC_MISC_RESET 0x00001000 /* reset */
257 #define THC_MISC_VIDEN 0x00000400 /* video enable */
258 #define THC_MISC_SYNC 0x00000200 /* not sure what ... */
259 #define THC_MISC_VSYNC 0x00000100 /* ... these really are */
260 #define THC_MISC_SYNCEN 0x00000080 /* sync enable */
261 #define THC_MISC_CURSRES 0x00000040 /* cursor resolution */
262 #define THC_MISC_INTEN 0x00000020 /* v.retrace intr enable */
263 #define THC_MISC_INTR 0x00000010 /* intr pending/ack */
264 #define THC_MISC_CYCLS 0x0000000f /* cycles before transfer */
265
266 struct cgsix_softc {
267 struct sunfb sc_sunfb;
268 bus_space_tag_t sc_bustag;
269 bus_addr_t sc_paddr;
270 bus_space_handle_t sc_bt_regs;
271 bus_space_handle_t sc_fhc_regs;
272 bus_space_handle_t sc_thc_regs;
273 bus_space_handle_t sc_tec_regs;
274 bus_space_handle_t sc_vid_regs;
275 bus_space_handle_t sc_fbc_regs;
276 int sc_nscreens;
277 union bt_cmap sc_cmap;
278 void *sc_ih;
279 u_int sc_mode;
280 u_int sc_curs_enabled, sc_curs_fg, sc_curs_bg;
281 struct wsdisplay_curpos sc_curs_pos, sc_curs_hot, sc_curs_size;
282 u_char sc_curs_image[128], sc_curs_mask[128];
283 };
284
285 #define CG6_USER_FBC 0x70000000
286 #define CG6_USER_TEC 0x70001000
287 #define CG6_USER_BTREGS 0x70002000
288 #define CG6_USER_FHC 0x70004000
289 #define CG6_USER_THC 0x70005000
290 #define CG6_USER_ROM 0x70006000
291 #define CG6_USER_RAM 0x70016000
292 #define CG6_USER_DHC 0x80000000
293
294 #define THC_READ(sc,r) \
295 bus_space_read_4((sc)->sc_bustag, (sc)->sc_thc_regs, (r))
296 #define THC_WRITE(sc,r,v) \
297 bus_space_write_4((sc)->sc_bustag, (sc)->sc_thc_regs, (r), (v))
298
299 #define TEC_READ(sc,r) \
300 bus_space_read_4((sc)->sc_bustag, (sc)->sc_tec_regs, (r))
301 #define TEC_WRITE(sc,r,v) \
302 bus_space_write_4((sc)->sc_bustag, (sc)->sc_tec_regs, (r), (v))
303
304 #define FHC_READ(sc) \
305 bus_space_read_4((sc)->sc_bustag, (sc)->sc_fhc_regs, CG6_FHC)
306 #define FHC_WRITE(sc,v) \
307 bus_space_write_4((sc)->sc_bustag, (sc)->sc_fhc_regs, CG6_FHC, (v))
308
309 #define FBC_READ(sc,r) \
310 bus_space_read_4((sc)->sc_bustag, (sc)->sc_fbc_regs, (r))
311 #define FBC_WRITE(sc,r,v) \
312 bus_space_write_4((sc)->sc_bustag, (sc)->sc_fbc_regs, (r), (v))
313
314 #define BT_WRITE(sc, reg, val) \
315 bus_space_write_4((sc)->sc_bustag, (sc)->sc_bt_regs, (reg), (val))
316 #define BT_READ(sc, reg) \
317 bus_space_read_4((sc)->sc_bustag, (sc)->sc_bt_regs, (reg))
318 #define BT_BARRIER(sc,reg,flags) \
319 bus_space_barrier((sc)->sc_bustag, (sc)->sc_bt_regs, (reg), \
320 sizeof(u_int32_t), (flags))
321
322 #define CG6_BLIT_WAIT(sc) \
323 while ((FBC_READ(sc, CG6_FBC_BLIT) & \
324 (FBC_BLIT_UNKNOWN|FBC_BLIT_GXFULL)) == \
325 (FBC_BLIT_UNKNOWN|FBC_BLIT_GXFULL))
326 #define CG6_DRAW_WAIT(sc) \
327 while ((FBC_READ(sc, CG6_FBC_DRAW) & \
328 (FBC_DRAW_UNKNOWN|FBC_DRAW_GXFULL)) == \
329 (FBC_DRAW_UNKNOWN|FBC_DRAW_GXFULL))
330 #define CG6_DRAIN(sc) \
331 while (FBC_READ(sc, CG6_FBC_S) & FBC_S_GXINPROGRESS)
332
333 #define CG6_MAX_CURSOR 32
334
335 #define CG6_CFFLAG_NOACCEL 0x1 /* disable console acceleration */