root/dev/mii/rgephy.c

DEFINITIONS

1. rgephymatch
2. rgephyattach
3. rgephy_service
4. rgephy_status
5. rgephy_mii_phy_auto
6. rgephy_loop
7. rgephy_load_dspcode
8. rgephy_reset

    1 /*      $OpenBSD: rgephy.c,v 1.24 2007/01/21 22:37:56 kettenis Exp $    */
    2 /*
    3  * Copyright (c) 2003
    4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. All advertising materials mentioning features or use of this software
   15  *    must display the following acknowledgement:
   16  *      This product includes software developed by Bill Paul.
   17  * 4. Neither the name of the author nor the names of any co-contributors
   18  *    may be used to endorse or promote products derived from this software
   19  *    without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   31  * THE POSSIBILITY OF SUCH DAMAGE.
   32  *
   33  * $FreeBSD: rgephy.c,v 1.5 2004/05/30 17:57:40 phk Exp $
   34  */
   36 /*
   37  * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
   38  */
   40 #include <sys/param.h>
   41 #include <sys/systm.h>
   42 #include <sys/kernel.h>
   43 #include <sys/device.h>
   44 #include <sys/socket.h>
   45 #include <sys/timeout.h>
   46 #include <sys/errno.h>
   48 #include <net/if.h>
   49 #include <net/if_media.h>
   51 #ifdef INET
   52 #include <netinet/in.h>
   53 #include <netinet/if_ether.h>
   54 #endif
   56 #include <dev/pci/pcivar.h>
   58 #include <dev/mii/mii.h>
   59 #include <dev/mii/miivar.h>
   60 #include <dev/mii/miidevs.h>
   62 #include <dev/mii/rgephyreg.h>
   64 #include <machine/bus.h>
   66 #include <dev/ic/rtl81x9reg.h>
   68 int     rgephymatch(struct device *, void *, void *);
   69 void    rgephyattach(struct device *, struct device *, void *);
   71 struct cfattach rgephy_ca = {
   72         sizeof(struct mii_softc),
rgephymatch,
rgephyattach,
mii_phy_detach,
mii_phy_activate
   77 };
   79 struct cfdriver rgephy_cd = {
NULL, "rgephy", DV_DULL
   81 };
   83 int     rgephy_service(struct mii_softc *, struct mii_data *, int);
   84 void    rgephy_status(struct mii_softc *);
   85 int     rgephy_mii_phy_auto(struct mii_softc *);
   86 void    rgephy_reset(struct mii_softc *);
   87 void    rgephy_loop(struct mii_softc *);
   88 void    rgephy_load_dspcode(struct mii_softc *);
   90 const struct mii_phy_funcs rgephy_funcs = {
rgephy_service, rgephy_status, rgephy_reset,
   92 };
   94 static const struct mii_phydesc rgephys[] = {
   95         { MII_OUI_REALTEK2,             MII_MODEL_xxREALTEK_RTL8169S,
MII_STR_xxREALTEK_RTL8169S },
   97         { MII_OUI_xxREALTEK,            MII_MODEL_xxREALTEK_RTL8169S,
MII_STR_xxREALTEK_RTL8169S },
  100         { 0,                    0,
NULL },
  102 };
  104 int
rgephymatch(struct device *parent, void *match, void *aux)
  106 {
  107         struct mii_attach_args *ma = aux;
  109         if (mii_phy_match(ma, rgephys) != NULL)
  110                 return (10);
  112         return (0);
  113 }
  115 void
rgephyattach(struct device *parent, struct device *self, void *aux)
  117 {
  118         struct mii_softc *sc = (struct mii_softc *)self;
  119         struct mii_attach_args *ma = aux;
  120         struct mii_data *mii = ma->mii_data;
  121         const struct mii_phydesc *mpd;
mpd = mii_phy_match(ma, rgephys);
printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
sc->mii_inst = mii->mii_instance;
sc->mii_phy = ma->mii_phyno;
sc->mii_funcs = &rgephy_funcs;
sc->mii_pdata = mii;
sc->mii_flags = ma->mii_flags;
sc->mii_anegticks = MII_ANEGTICKS_GIGE;
sc->mii_flags |= MIIF_NOISOLATE;
sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
  137         if (sc->mii_capabilities & BMSR_EXTSTAT)
sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
  139         if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
  140             (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
mii_phy_add_media(sc);
PHY_RESET(sc);
  144 }
  146 int
rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
  148 {
  149         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
  150         int anar, reg, speed, gig = 0;
  152         switch (cmd) {
  153         case MII_POLLSTAT:
  154                 /*
  155                  * If we're not polling our PHY instance, just return.
  156                  */
  157                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
  158                         return (0);
  159                 break;
  161         case MII_MEDIACHG:
  162                 /*
  163                  * If the media indicates a different PHY instance,
  164                  * isolate ourselves.
  165                  */
  166                 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
reg = PHY_READ(sc, MII_BMCR);
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
  169                         return (0);
  170                 }
  172                 /*
  173                  * If the interface is not up, don't do anything.
  174                  */
  175                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
  176                         break;
PHY_RESET(sc);  /* XXX hardware bug work-around */
anar = PHY_READ(sc, RGEPHY_MII_ANAR);
anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
  184                 switch (IFM_SUBTYPE(ife->ifm_media)) {
  185                 case IFM_AUTO:
  186                         (void) rgephy_mii_phy_auto(sc);
  187                         break;
  188                 case IFM_1000_T:
speed = RGEPHY_S1000;
  190                         goto setit;
  191                 case IFM_100_TX:
speed = RGEPHY_S100;
anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
  194                         goto setit;
  195                 case IFM_10_T:
speed = RGEPHY_S10;
anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
setit:
rgephy_loop(sc);
  200                         if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
speed |= RGEPHY_BMCR_FDX;
  202                                 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T)
gig = RGEPHY_1000CTL_AFD;
anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
  205                         } else {
  206                                 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T)
gig = RGEPHY_1000CTL_AHD;
anar &=
  209                                     ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
  210                         }
  212                         if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T &&
mii->mii_media.ifm_media & IFM_ETH_MASTER)
gig |= RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC;
PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
  220                         break;
  221 #if 0
  222                 case IFM_NONE:
PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
  224                         break;
  225 #endif
  226                 case IFM_100_T4:
  227                 default:
  228                         return (EINVAL);
  229                 }
  230                 break;
  232         case MII_TICK:
  233                 /*
  234                  * If we're not currently selected, just return.
  235                  */
  236                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
  237                         return (0);
  239                 /*
  240                  * Is the interface even up?
  241                  */
  242                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
  243                         return (0);
  245                 /*
  246                  * Only used for autonegotiation.
  247                  */
  248                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
  249                         break;
  251                 /*
  252                  * Check to see if we have link.  If we do, we don't
  253                  * need to restart the autonegotiation process.  Read
  254                  * the BMSR twice in case it's latched.
  255                  */
reg = PHY_READ(sc, RL_GMEDIASTAT);
  257                 if (reg & RL_GMEDIASTAT_LINK)
  258                         break;
  260                 /*
  261                  * Only retry autonegotiation every mii_anegticks seconds.
  262                  */
  263                 if (++sc->mii_ticks <= sc->mii_anegticks)
  264                         break;
sc->mii_ticks = 0;
rgephy_mii_phy_auto(sc);
  268                 return (0);
  269         }
  271         /* Update the media status. */
mii_phy_status(sc);
  274         /*
  275          * Callback if something changed. Note that we need to poke
  276          * the DSP on the RealTek PHYs if the media changes.
  277          *
  278          */
  279         if (sc->mii_media_active != mii->mii_media_active || 
sc->mii_media_status != mii->mii_media_status ||
cmd == MII_MEDIACHG)
rgephy_load_dspcode(sc);
  284         /* Callback if something changed. */
mii_phy_update(sc, cmd);
  287         return (0);
  288 }
  290 void
rgephy_status(struct mii_softc *sc)
  292 {
  293         struct mii_data *mii = sc->mii_pdata;
  294         int bmsr, bmcr, gtsr;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
bmsr = PHY_READ(sc, RL_GMEDIASTAT);
  301         if (bmsr & RL_GMEDIASTAT_LINK)
mii->mii_media_status |= IFM_ACTIVE;
bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
  307         if (bmcr & RGEPHY_BMCR_LOOP)
mii->mii_media_active |= IFM_LOOP;
  310         if (bmcr & RGEPHY_BMCR_AUTOEN) {
  311                 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
  312                         /* Erg, still trying, I guess... */
mii->mii_media_active |= IFM_NONE;
  314                         return;
  315                 }
  316         }
bmsr = PHY_READ(sc, RL_GMEDIASTAT);
  319         if (bmsr & RL_GMEDIASTAT_1000MBPS)
mii->mii_media_active |= IFM_1000_T;
  321         else if (bmsr & RL_GMEDIASTAT_100MBPS)
mii->mii_media_active |= IFM_100_TX;
  323         else if (bmsr & RL_GMEDIASTAT_10MBPS)
mii->mii_media_active |= IFM_10_T;
  326         if (bmsr & RL_GMEDIASTAT_FDX)
mii->mii_media_active |= mii_phy_flowstatus(sc) | IFM_FDX;
  328         else
mii->mii_media_active |= IFM_HDX;
gtsr = PHY_READ(sc, RGEPHY_MII_1000STS);
  332         if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
gtsr & RGEPHY_1000STS_MSR)
mii->mii_media_active |= IFM_ETH_MASTER;
  335 }
  338 int
rgephy_mii_phy_auto(struct mii_softc *sc)
  340 {
  341         int anar;
rgephy_loop(sc);
PHY_RESET(sc);
anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
  347         if (sc->mii_flags & MIIF_DOPAUSE)
anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
DELAY(1000);
PHY_WRITE(sc, RGEPHY_MII_1000CTL,
RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
DELAY(1000);
PHY_WRITE(sc, RGEPHY_MII_BMCR,
RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
DELAY(100);
  359         return (EJUSTRETURN);
  360 }
  362 void
rgephy_loop(struct mii_softc *sc)
  364 {
u_int32_t bmsr;
  366         int i;
PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
DELAY(1000);
  371         for (i = 0; i < 15000; i++) {
bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
  373                 if (!(bmsr & RGEPHY_BMSR_LINK))
  374                         break;
DELAY(10);
  376         }
  377 }
  379 #define PHY_SETBIT(x, y, z) \
PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
  381 #define PHY_CLRBIT(x, y, z) \
PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
  384 /*
  385  * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
  386  * existing revisions of the 8169S/8110S chips need to be tuned in
  387  * order to reliably negotiate a 1000Mbps link. This is only needed
  388  * for rev 0 and rev 1 of the PHY. Later versions work without
  389  * any fixups.
  390  */
  391 void
rgephy_load_dspcode(struct mii_softc *sc)
  393 {
  394         int val;
u_int16_t id2;
id2 = PHY_READ(sc, MII_PHYIDR2);
  398         if (MII_REV(id2) > 1)
  399                 return;
PHY_WRITE(sc, 31, 0x0001);
PHY_WRITE(sc, 21, 0x1000);
PHY_WRITE(sc, 24, 0x65C7);
PHY_CLRBIT(sc, 4, 0x0800);
val = PHY_READ(sc, 4) & 0xFFF;
PHY_WRITE(sc, 4, val);
PHY_WRITE(sc, 3, 0x00A1);
PHY_WRITE(sc, 2, 0x0008);
PHY_WRITE(sc, 1, 0x1020);
PHY_WRITE(sc, 0, 0x1000);
PHY_SETBIT(sc, 4, 0x0800);
PHY_CLRBIT(sc, 4, 0x0800);
val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
PHY_WRITE(sc, 4, val);
PHY_WRITE(sc, 3, 0xFF41);
PHY_WRITE(sc, 2, 0xDE60);
PHY_WRITE(sc, 1, 0x0140);
PHY_WRITE(sc, 0, 0x0077);
val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
PHY_WRITE(sc, 4, val);
PHY_WRITE(sc, 3, 0xDF01);
PHY_WRITE(sc, 2, 0xDF20);
PHY_WRITE(sc, 1, 0xFF95);
PHY_WRITE(sc, 0, 0xFA00);
val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
PHY_WRITE(sc, 4, val);
PHY_WRITE(sc, 3, 0xFF41);
PHY_WRITE(sc, 2, 0xDE20);
PHY_WRITE(sc, 1, 0x0140);
PHY_WRITE(sc, 0, 0x00BB);
val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
PHY_WRITE(sc, 4, val);
PHY_WRITE(sc, 3, 0xDF01);
PHY_WRITE(sc, 2, 0xDF20);
PHY_WRITE(sc, 1, 0xFF95);
PHY_WRITE(sc, 0, 0xBF00);
PHY_SETBIT(sc, 4, 0x0800);
PHY_CLRBIT(sc, 4, 0x0800);
PHY_WRITE(sc, 31, 0x0000);
DELAY(40);
  442 }
  444 void
rgephy_reset(struct mii_softc *sc)
  446 {
mii_phy_reset(sc);
DELAY(1000);
rgephy_load_dspcode(sc);
  450 }