root/dev/pci/ises.c

DEFINITIONS

1. ises_match
2. ises_attach
3. ises_initstate
4. ises_queue_cmd
5. ises_process_oqueue
6. ises_intr
7. ises_feed
8. ises_newsession
9. ises_freesession
10. ises_process
11. ises_callback
12. ises_hrng_init
13. ises_hrng
14. ises_get_fwversion
15. ises_assert_cmd_mode
16. ises_bchu_switch_session
17. ises_bchu_switch_final
18. ises_read_dma
19. ises_debug_init
20. ises_debug_2
21. ises_debug_simple_cmd
22. ises_debug_loop
23. ises_showreg
24. ises_debug_parse_omr

    1 /*      $OpenBSD: ises.c,v 1.31 2006/06/29 21:34:51 deraadt Exp $       */
    3 /*
    4  * Copyright (c) 2000, 2001 Håkan Olsson (ho@crt.se)
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   18  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   19  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
   20  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   22  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   24  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
   25  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   26  * POSSIBILITY OF SUCH DAMAGE.
   27  */
   29 /*
   30  * PCC-ISES hardware crypto accelerator
   31  */
   33 #include <sys/param.h>
   34 #include <sys/systm.h>
   35 #include <sys/proc.h>
   36 #include <sys/errno.h>
   37 #include <sys/malloc.h>
   38 #include <sys/kernel.h>
   39 #include <sys/mbuf.h>
   40 #include <sys/timeout.h>
   41 #include <sys/device.h>
   42 #include <sys/queue.h>
   44 #include <crypto/cryptodev.h>
   45 #include <crypto/cryptosoft.h>
   46 #include <dev/rndvar.h>
   47 #include <crypto/md5.h>
   48 #include <crypto/sha1.h>
   49 #include <crypto/rmd160.h>
   51 #include <dev/pci/pcireg.h>
   52 #include <dev/pci/pcivar.h>
   53 #include <dev/pci/pcidevs.h>
   55 #include <dev/pci/isesreg.h>
   56 #include <dev/pci/isesvar.h>
   57 #include <dev/microcode/ises/ises_fw.h>
   59 /*
   60  * Prototypes and count for the pci_device structure
   61  */
   62 int     ises_match(struct device *, void *, void *);
   63 void    ises_attach(struct device *, struct device *, void *);
   65 void    ises_initstate(void *);
   66 void    ises_hrng_init(struct ises_softc *);
   67 void    ises_hrng(void *);
   68 void    ises_process_oqueue(struct ises_softc *);
   69 int     ises_queue_cmd(struct ises_softc *, u_int32_t, u_int32_t *, 
u_int32_t (*)(struct ises_softc *, struct ises_cmd *));
u_int32_t ises_get_fwversion(struct ises_softc *);
   72 int     ises_assert_cmd_mode(struct ises_softc *);
   74 int     ises_intr(void *);
   75 int     ises_newsession(u_int32_t *, struct cryptoini *);
   76 int     ises_freesession(u_int64_t);
   77 int     ises_process(struct cryptop *);
   78 void    ises_callback(struct ises_q *);
   79 int     ises_feed(struct ises_softc *);
   80 int     ises_bchu_switch_session(struct ises_softc *, 
   81                                       struct ises_session *, int);
u_int32_t ises_bchu_switch_final(struct ises_softc *, struct ises_cmd *);
   84 void    ises_read_dma(struct ises_softc *);
   86 #define READ_REG(sc,r) \
bus_space_read_4((sc)->sc_memt, (sc)->sc_memh,r)
   89 #define WRITE_REG(sc,reg,val) \
bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, reg, val)
   92 /* XXX This should probably be (x) = htole32((x)) */
   93 #define SWAP32(x) ((x) = swap32((x)))
   95 #ifdef ISESDEBUG
   96 #  define DPRINTF(x) printf x
   97 #else
   98 #  define DPRINTF(x)
   99 #endif
  101 #ifdef ISESDEBUG
  102 void    ises_debug_init(struct ises_softc *);
  103 void    ises_debug_2(void);
  104 void    ises_debug_loop(void *);
  105 void    ises_showreg(void);
  106 void    ises_debug_parse_omr(struct ises_softc *);
  107 void    ises_debug_simple_cmd(struct ises_softc *, u_int32_t, u_int32_t);
  108 struct ises_softc *ises_sc;
  109 struct timeout ises_db_timeout;
  110 int ises_db;
  111 #endif
  113 /* For HRNG entropy collection, these values gather 1600 bytes/s */
  114 #ifndef ISESRNGBITS
  115 #define ISESRNGBITS     128             /* Bits per iteration (mult. of 32) */
  116 #define ISESRNGIPS      100             /* Iterations per second */
  117 #endif
  119 /* XXX Disable HRNG while debugging. */
  120 #define ISES_HRNG_DISABLED
  122 /* Maximum number of times we try to download the firmware. */
  123 #define ISES_MAX_DOWNLOAD_RETRIES       3
  125 struct cfattach ises_ca = {
  126         sizeof(struct ises_softc), ises_match, ises_attach,
  127 };
  129 struct cfdriver ises_cd = {
  130         0, "ises", DV_DULL
  131 };
  133 struct ises_stats {
u_int64_t       ibytes;
u_int64_t       obytes;
u_int32_t       ipkts;
u_int32_t       opkts;
u_int32_t       invalid;
u_int32_t       nomem;
  140 } isesstats;
  142 int
ises_match(struct device *parent, void *match, void *aux)
  144 {
  145         struct pci_attach_args *pa = (struct pci_attach_args *)aux;
  147         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PIJNENBURG &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_PIJNENBURG_PCC_ISES)
  149                 return (1);
  151         return (0);
  152 }
  154 void
ises_attach(struct device *parent, struct device *self, void *aux)
  156 {
  157         struct ises_softc *sc = (struct ises_softc *)self;
  158         struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
pci_intr_handle_t ih;
  161         const char *intrstr = NULL;
bus_size_t memsize;
bus_dma_segment_t seg;
  165         int nsegs, error, state;
SIMPLEQ_INIT(&sc->sc_queue);
SIMPLEQ_INIT(&sc->sc_qchip);
SIMPLEQ_INIT(&sc->sc_cmdq);
state = 0;
  172         /* Map control/status registers. */
  173         if (pci_mapreg_map(pa, PCI_MAPREG_START,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_memt,
  175             &sc->sc_memh, NULL, &memsize, 0)) {
printf(": can't find mem space\n");
  177                 return;
  178         }
state++;
  181         /* Map interrupt. */
  182         if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
  184                 goto fail;
  185         }
state++;
intrstr = pci_intr_string(pc, ih);
sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ises_intr, sc,
self->dv_xname);
  191         if (sc->sc_ih == NULL) {
printf(": couldn't establish interrupt\n");
  193                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
  196                 goto fail;
  197         }
  199         /* Initialize DMA map */
sc->sc_dmat = pa->pa_dmat;
error = bus_dmamap_create(sc->sc_dmat, 1 << PGSHIFT, 1, 1 << PGSHIFT,
  202             0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_dmamap);
  203         if (error) {
printf(": cannot create dma map (%d)\n", error);
  205                 goto fail;
  206         }
state++;
  209         /* Allocate in DMAable memory. */
  210         if (bus_dmamem_alloc(sc->sc_dmat, ISES_B_DATASIZE, 1, 0, &seg, 1,
  211             &nsegs, BUS_DMA_NOWAIT)) {
printf(": can't alloc dma buffer space\n");
  213                 goto fail;
  214         }
state++;
  217         if (bus_dmamem_map(sc->sc_dmat, &seg, nsegs, ISES_B_DATASIZE,
  218             &sc->sc_dma_data, 0)) {
printf(": can't map dma buffer space\n");
  220                 goto fail;
  221         }
state++;
printf(": %s\n", intrstr);
bzero(&isesstats, sizeof(isesstats));
sc->sc_cid = crypto_get_driverid(0);
  230         if (sc->sc_cid < 0)
  231                 goto fail;
  233         /*
  234          * Since none of the initialization steps generate interrupts
  235          * for example, the hardware reset, we use a number of timeouts
  236          * (or init states) to do the rest of the chip initialization.
  237          */
sc->sc_initstate = 0;
startuphook_establish(ises_initstate, sc);
  242 #ifdef ISESDEBUG
ises_debug_init(sc);
  244 #endif
  245         return;
fail:
  248         switch (state) { /* Always fallthrough here. */
  249         case 5:
bus_dmamem_unmap(sc->sc_dmat, (caddr_t)&sc->sc_dma_data,
  251                     sizeof sc->sc_dma_data);
  252                 /* FALLTHROUGH */
  253         case 4:
bus_dmamem_free(sc->sc_dmat, &seg, nsegs);
  255                 /* FALLTHROUGH */
  256         case 3:
bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
  258                 /* FALLTHROUGH */
  259         case 2:
pci_intr_disestablish(pc, sc->sc_ih);
  261                 /* FALLTHROUGH */
  262         case 1:
bus_space_unmap(sc->sc_memt, sc->sc_memh, memsize);
  264                 /* FALLTHROUGH */
  265         default: /* 0 */
  266                 break;
  267         }
  268         return;
  269 }
  271 void
ises_initstate(void *v)
  273 {
  274         /*
  275          * Step through chip initialization.
  276          * sc->sc_initstate tells us what to do.
  277          */
  278         extern int hz;
  279         struct ises_softc *sc = v;
  280         char *dv = sc->sc_dv.dv_xname;
u_int32_t stat;
  282         int p, ticks, algs[CRYPTO_ALGORITHM_MAX + 1];
  283         static int retry_count = 0; /* XXX Should be in softc */
ticks = hz * 3 / 2; /* 1.5s */ 
p = ISES_STAT_IDP_STATE(READ_REG(sc, ISES_A_STAT));
DPRINTF(("%s: initstate %d, IDP state is %d \"%s\"\n", dv, 
sc->sc_initstate, p, ises_idp_state[p]));
  291         switch (sc->sc_initstate) {
  292         case 0:
  293                 /* Called by dostartuphooks(9). */
timeout_set(&sc->sc_timeout, ises_initstate, sc);
sc->sc_initstate++;
  297                 /* FALLTHROUGH */
  298         case 1:
  299                 /* Power up the chip (clear powerdown bit) */
stat = READ_REG(sc, ISES_BO_STAT);
  301                 if (stat & ISES_BO_STAT_POWERDOWN) {
stat &= ~ISES_BO_STAT_POWERDOWN;
WRITE_REG(sc, ISES_BO_STAT, stat);
  304                         /* Selftests will take 1 second. */
  305                         break;
  306                 }
  307 #if 1
  308                 else {
  309                         /* Power down the chip for sane init, then rerun. */
stat |= ISES_BO_STAT_POWERDOWN;
WRITE_REG(sc, ISES_BO_STAT, stat);
sc->sc_initstate--; /* Rerun state 1. */
  313                         break;
  314                 }
  315 #else
  316                 /* FALLTHROUGH (chip is already powered up) */
sc->sc_initstate++;
  318 #endif
  320         case 2:
  321                 /* Perform a hardware reset */
stat = 0;
printf ("%s: initializing...\n", dv);
  326                 /* Clear all possible bypass bits. */
  327                 for (p = 0; p < 128; p++)
WRITE_REG(sc, ISES_B_BDATAOUT, 0L);
stat |= ISES_BO_STAT_HWRESET;
WRITE_REG(sc, ISES_BO_STAT, stat);
stat &= ~ISES_BO_STAT_HWRESET;
WRITE_REG(sc, ISES_BO_STAT, stat);
  334                 /* Again, selftests will take 1 second. */
  335                 break;
  337         case 3:
  338                 /* Set AConf to zero, i.e 32-bits access to A-int. */
stat = READ_REG(sc, ISES_BO_STAT);
stat &= ~ISES_BO_STAT_ACONF;
WRITE_REG(sc, ISES_BO_STAT, stat);
  343                 /* Is the firmware already loaded? */
  344                 if (READ_REG(sc, ISES_A_STAT) & ISES_STAT_HW_DA) {
  345                         /* Yes it is, jump ahead a bit */
ticks = 1;
sc->sc_initstate += 3; /* Next step --> 7 */
  348                         break;
  349                 }
  351                 /*
  352                  * Download the Basic Functionality firmware.
  353                  */
p = ISES_STAT_IDP_STATE(READ_REG(sc, ISES_A_STAT));
  356                 if (p == ISES_IDP_WFPL) {
  357                         /* We're ready to download. */
ticks = 1;
sc->sc_initstate += 2; /* Next step --> 6 */
  360                         break;
  361                 }
  363                 /*
  364                  * Prior to downloading we need to reset the NSRAM.
  365                  * Setting the tamper bit will erase the contents
  366                  * in 1 microsecond.
  367                  */
stat = READ_REG(sc, ISES_BO_STAT);
stat |= ISES_BO_STAT_TAMPER;
WRITE_REG(sc, ISES_BO_STAT, stat);
ticks = 1;
  372                 break;
  374         case 4:
  375                 /* After tamper bit has been set, powerdown chip. */
stat = READ_REG(sc, ISES_BO_STAT);
stat |= ISES_BO_STAT_POWERDOWN;
WRITE_REG(sc, ISES_BO_STAT, stat);
  379                 /* Wait one second for power to dissipate. */
  380                 break;
  382         case 5:
  383                 /* Clear tamper and powerdown bits. */
stat = READ_REG(sc, ISES_BO_STAT);
stat &= ~(ISES_BO_STAT_TAMPER | ISES_BO_STAT_POWERDOWN);
WRITE_REG(sc, ISES_BO_STAT, stat);
  387                 /* Again we need to wait a second for selftests. */
  388                 break;
  390         case 6:
  391                 /*
  392                  * We'll need some space in the input queue (IQF)
  393                  * and we need to be in the 'waiting for program
  394                  * length' IDP state (0x4).
  395                  */
p = ISES_STAT_IDP_STATE(READ_REG(sc, ISES_A_STAT));
  397                 if (READ_REG(sc, ISES_A_IQF) < 4 || p != ISES_IDP_WFPL) {
  398                         if (retry_count++ < ISES_MAX_DOWNLOAD_RETRIES) {
  399                                 /* Retry download. */
sc->sc_initstate -= 5; /* Next step --> 2 */
ticks = 1;
  402                                 break;
  403                         }
retry_count = 0;
printf("%s: cannot download firmware, "
  406                             "IDP state is \"%s\"\n", dv, ises_idp_state[p]);
  407                         return;
  408                 }
  410                 /* Write firmware length */
WRITE_REG(sc, ISES_A_IQD, ISES_BF_IDPLEN);
  413                 /* Write firmware code */
  414                 for (p = 0; p < sizeof(ises_bf_fw)/sizeof(u_int32_t); p++) {
WRITE_REG(sc, ISES_A_IQD, ises_bf_fw[p]);
  416                         if (READ_REG(sc, ISES_A_IQF) < 4)
DELAY(10);
  418                 }
  420                 /* Write firmware CRC */
WRITE_REG(sc, ISES_A_IQD, ISES_BF_IDPCRC);
  423                 /* Wait 1s while chip resets and runs selftests */
  424                 break;
  426         case 7:
  427                 /* Did the download succed? */
  428                 if (READ_REG(sc, ISES_A_STAT) & ISES_STAT_HW_DA) {
ticks = 1;
  430                         break;
  431                 }
  433                 /* We failed. */
  434                 goto fail;
  436         case 8:
  437                 if (ises_assert_cmd_mode(sc) < 0)
  438                         goto fail;
  440                 /*
  441                  * Now that the basic functionality firmware should be
  442                  * up and running, try to get the firmware version.
  443                  */
stat = ises_get_fwversion(sc);
  446                 if (stat == 0)
  447                         goto fail;
printf("%s: firmware v%d.%d loaded (%d bytes)", dv,
stat & 0xffff, (stat >> 16) & 0xffff, ISES_BF_IDPLEN << 2);
  452                 /* We can use firmware versions 1.x & 2.x */
  453                 switch (stat & 0xffff) {
  454                 case 0:
printf(" diagnostic, %s disabled\n", dv);
  456                         goto fail;
  457                 case 1: /* Basic Func "base" firmware */
  458                 case 2: /* Basic Func "ipsec" firmware, no ADP code */
  459                         break;
  460                 default:
printf(" unknown, %s disabled\n", dv);
  462                         goto fail;
  463                 }
stat = READ_REG(sc, ISES_A_STAT);
DPRINTF((", mode %s",
ises_sw_mode[ISES_STAT_SW_MODE(stat)]));
  469                 /* Reuse the timeout for HRNG entropy collection. */
timeout_del(&sc->sc_timeout);
ises_hrng_init(sc);
  473                 /* Set the interrupt mask */
sc->sc_intrmask = ISES_STAT_BCHU_OAF | ISES_STAT_BCHU_ERR |
ISES_STAT_BCHU_OFHF | ISES_STAT_SW_OQSINC |
ISES_STAT_LNAU_BUSY_1 | ISES_STAT_LNAU_ERR_1 |
ISES_STAT_LNAU_BUSY_2 | ISES_STAT_LNAU_ERR_2;
  478 #if 0
ISES_STAT_BCHU_ERR | ISES_STAT_BCHU_OAF |
ISES_STAT_BCHU_IFE | ISES_STAT_BCHU_IFHE |
ISES_STAT_BCHU_OFHF | ISES_STAT_BCHU_OFF;
  482 #endif
WRITE_REG(sc, ISES_A_INTE, sc->sc_intrmask);
  486                 /* We're done. */
printf("\n");
  489                 /* Register ourselves with crypto framework. */
bzero(algs, sizeof(algs));
algs[CRYPTO_3DES_CBC] = CRYPTO_ALG_FLAG_SUPPORTED;
algs[CRYPTO_DES_CBC] = CRYPTO_ALG_FLAG_SUPPORTED;
algs[CRYPTO_MD5_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED;
algs[CRYPTO_SHA1_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED;
algs[CRYPTO_RIPEMD160_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED;
crypto_register(sc->sc_cid, algs,
ises_newsession, ises_freesession, ises_process);
  500                 return;
  502         default:
printf("%s: entered unknown initstate %d\n", dv,
sc->sc_initstate);
  505                 goto fail;
  506         }
  508         /* Increment state counter and schedule next step in 'ticks' ticks. */
sc->sc_initstate++;
timeout_add(&sc->sc_timeout, ticks);
  511         return;
fail:
printf("%s: firmware failure\n", dv);
timeout_del(&sc->sc_timeout);
  516         return;
  517 }
  519 /* Put a command on the A-interface queue. */
  520 int
ises_queue_cmd(struct ises_softc *sc, u_int32_t cmd, u_int32_t *data, 
u_int32_t (*callback)(struct ises_softc *, struct ises_cmd *))
  523 {
  524         struct ises_cmd *cq;
  525         int p, len, s, code;
len = cmd >> 24;
code = (cmd >> 16) & 0xFF;
  530 #ifdef ISESDEBUG
  531         if (code != ISES_CMD_HBITS) /* ... since this happens 100 times/s */
DPRINTF(("%s: queueing cmd 0x%x len %d\n", sc->sc_dv.dv_xname,
code, len));
  534 #endif
s = splnet();
  538         if (len > READ_REG(sc, ISES_A_IQF)) {
splx(s);
  540                 return (EAGAIN); /* XXX ENOMEM ? */
  541         }
cq = (struct ises_cmd *) 
malloc(sizeof (struct ises_cmd), M_DEVBUF, M_NOWAIT);
  545         if (cq == NULL) {
splx(s);
isesstats.nomem++;
  548                 return (ENOMEM);
  549         }
bzero(cq, sizeof (struct ises_cmd));
cq->cmd_code = code;
cq->cmd_cb = callback;
cq->cmd_session = sc->sc_cursession;
SIMPLEQ_INSERT_TAIL(&sc->sc_cmdq, cq, cmd_next);
WRITE_REG(sc, ISES_A_IQD, cmd);
  558         /* LNAU register data should be written in reverse order */
  559         if ((code >= ISES_CMD_LW_A_1 && code <= ISES_CMD_LW_U_1) || /* LNAU1 */
  560             (code >= ISES_CMD_LW_A_2 && code <= ISES_CMD_LW_U_2))   /* LNAU2 */
  561                 for (p = len - 1; p >= 0; p--)
WRITE_REG(sc, ISES_A_IQD, *(data + p));
  563         else
  564                 for (p = 0; p < len; p++)
WRITE_REG(sc, ISES_A_IQD, *(data + p));
  567         /* Signal 'command ready'. */
WRITE_REG(sc, ISES_A_IQS, 0);
splx(s);
  571         return (0);
  572 }
  574 /* Process all completed responses in the output queue. */
  575 void
ises_process_oqueue(struct ises_softc *sc)
  577 {
  578 #ifdef ISESDEBUG
  579         char *dv = sc->sc_dv.dv_xname;
  580 #endif
  581         struct ises_cmd *cq;
  582         struct ises_session *ses;
u_int32_t oqs, r, d;
  584         int cmd, len, c, s;
r = READ_REG(sc, ISES_A_OQS);
  587         if (r > 1)
DPRINTF(("%s:process_oqueue: OQS=%d\n", dv, r));
  590         /* OQS gives us the number of responses we have to process. */
  591         while ((oqs = READ_REG(sc, ISES_A_OQS)) > 0) {
  592                 /* Read command response. [ len(8) | cmd(8) | rc(16) ] */
r = READ_REG(sc, ISES_A_OQD);
len = (r >> 24);
cmd = (r >> 16) & 0xff;
r   = r & 0xffff;
s = splnet();
  599                 if (!SIMPLEQ_EMPTY(&sc->sc_cmdq)) {
cq = SIMPLEQ_FIRST(&sc->sc_cmdq);
SIMPLEQ_REMOVE_HEAD(&sc->sc_cmdq, cmd_next);
cq->cmd_rlen = len;
  603                 } else {
cq = NULL;
DPRINTF(("%s:process_oqueue: cmd queue empty!\n", dv));
  606                 }
splx(s);
  609                 if (r) {
  610                         /* Ouch. This command generated an error */
DPRINTF(("%s:process_oqueue: cmd 0x%x err %d\n", dv, 
cmd, (r & ISES_RC_MASK)));
  613                         /* Abort any running session switch to force a retry.*/
sc->sc_switching = 0;
  615                         /* Return to CMD mode. This will reset all queues. */
  616                         (void)ises_assert_cmd_mode(sc);
  617                 } else {
  618                         /* Use specified callback, if any */
  619                         if (cq && cq->cmd_cb) {
  620                                 if (cmd == cq->cmd_code) {
cq->cmd_cb(sc, cq);
cmd = ISES_CMD_NONE;
  623                                 } else {
DPRINTF(("%s:process_oqueue: expected"
  625                                             " cmd 0x%x, got 0x%x\n", dv, 
cq->cmd_code, cmd));
  627                                         /* XXX Some error handling here? */
  628                                 }
  629                         }
  631                         switch (cmd) {
  632                         case ISES_CMD_NONE:
  633                                 break;
  635                         case ISES_CMD_HBITS:
  636                                 /* XXX How about increasing the pool size? */
  637                                 /* XXX Use add_entropy_words instead? */
  638                                 /* XXX ... at proper spl */
  639                                 /* Cmd generated by ises_rng() via timeouts */
  640                                 while (len--) {
d = READ_REG(sc, ISES_A_OQD);
add_true_randomness(d);
  643                                 }
  644                                 break;
  646                         case ISES_CMD_LUPLOAD_1:
  647                                 /* Get result of LNAU 1 operation. */
DPRINTF(("%s:process_oqueue: LNAU 1 result "
  649                                      "upload (len=%d)\n", dv, len));
sc->sc_lnau1_rlen = len;
bzero(sc->sc_lnau1_r, 2048 / 8);
  652                                 while (len--) {
  653                                         /* first word is LSW */
sc->sc_lnau1_r[len] = 
READ_REG(sc, ISES_A_OQD);
  656                                 }
  657                                 break;
  659                         case ISES_CMD_LUPLOAD_2:
  660                                 /* Get result of LNAU 1 operation. */
DPRINTF(("%s:process_oqueue: LNAU 2 result "
  662                                      "upload (len=%d)\n", dv, len));
sc->sc_lnau2_rlen = len;
bzero(sc->sc_lnau1_r, 2048 / 8);
  665                                 while (len--) {
  666                                         /* first word is LSW */
sc->sc_lnau2_r[len] = 
READ_REG(sc, ISES_A_OQD);
  669                                 }
  670                                 break;
  672                         case ISES_CMD_BR_OMR:
ses = &sc->sc_sessions[cq->cmd_session];
ses->omr = READ_REG(sc, ISES_A_OQD);
DPRINTF(("%s:process_oqueue: read OMR[%08x]\n",
dv, ses->omr));
  677 #ifdef ISESDEBUG
ises_debug_parse_omr(sc);
  679 #endif
  680                                 break;
  682                         case ISES_CMD_BSWITCH:
  683                                 /* XXX Currently BSWITCH does not work. */
DPRINTF(("%s:process_oqueue: BCHU_SWITCH\n"));
  685                                 /* Put switched BCHU session in cur session. */
ses = &sc->sc_sessions[cq->cmd_session];
  687                                 for(c = 0; len > 0; len--, c++)
  688 #if 0 /* Don't store the key, just drain the data */
  689                                         *((u_int32_t *)&ses + c) =
  690 #endif
READ_REG(sc, ISES_A_OQD);
sc->sc_switching = 0;
ises_feed (sc);
  695                                 break;
  697                         case ISES_CMD_BW_HMLR:
  698                                 /* XXX Obsoleted by ises_bchu_switch_final */
DPRINTF(("%s:process_oqueue: CMD_BW_HMLR !?\n",
dv));
  701                                 break;
  703                         default:
  704                                 /* All other are ok (no response data) */
DPRINTF(("%s:process_oqueue cmd 0x%x len %d\n",
dv, cmd, len));
  707                                 if (cq && cq->cmd_cb) 
len -= cq->cmd_cb(sc, cq);
  709                         }
  710                 }
  712                 if (cq)
free(cq, M_DEVBUF);
  715                 /* This will drain any remaining data and ACK this reponse. */
  716                 while (len-- > 0)
d = READ_REG(sc, ISES_A_OQD);
WRITE_REG(sc, ISES_A_OQS, 0);
  719                 if (oqs > 1)
DELAY(1); /* Wait for fw to decrement OQS (8 clocks) */
  721         }
  722 }
  724 int
ises_intr(void *arg)
  726 {
  727         struct ises_softc *sc = arg;
u_int32_t ints, dma_status, cmd; 
  729         char *dv = sc->sc_dv.dv_xname;
dma_status = READ_REG(sc, ISES_DMA_STATUS);
  733         if (!(dma_status & (ISES_DMA_STATUS_R_ERR | ISES_DMA_STATUS_W_ERR))) {
  734                 if ((sc->sc_dma_mask & ISES_DMA_STATUS_R_RUN) != 0 &&
  735                     (dma_status & ISES_DMA_STATUS_R_RUN) == 0) {
DPRINTF(("%s: DMA read complete\n", dv));
bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0,
sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
  741                         /* XXX Pick up and return the data.*/
WRITE_REG(sc, ISES_DMA_RESET, 0);
  744                 }
  745                 if ((sc->sc_dma_mask & ISES_DMA_STATUS_W_RUN) != 0 &&
  746                     (dma_status & ISES_DMA_STATUS_W_RUN) == 0) {
DPRINTF(("%s: DMA write complete\n", dv));
bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0,
sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
WRITE_REG(sc, ISES_DMA_RESET, 0);
ises_feed(sc);
  754                 }
  755         } else {
printf ("%s: DMA error\n", dv);
WRITE_REG(sc, ISES_DMA_RESET, 0);
  758         }
ints = READ_REG(sc, ISES_A_INTS);
  761         if (!(ints & sc->sc_intrmask)) {
DPRINTF (("%s: other intr mask [%08x]\n", ints));
  763                 return (0); /* Not our interrupt. */
  764         }
  766         /* Clear all set intr bits. */
WRITE_REG(sc, ISES_A_INTS, ints);
  769 #if 0
  770         /* Check it we've got room for more data. */
  771         if (READ_REG(sc, ISES_A_STAT) &
  772             (ISES_STAT_BCHU_IFE | ISES_STAT_BCHU_IFHE))
ises_feed(sc);
  774 #endif
  776         /* Does the A-intf output queue have data we need to process? */
  777         if (ints & ISES_STAT_SW_OQSINC)
ises_process_oqueue(sc);
  780         if (ints & ISES_STAT_LNAU_BUSY_1) {
DPRINTF(("%s:ises_intr: LNAU 1 job complete\n", dv));
  782                 /* upload LNAU 1 result (into sc->sc_lnau1_r) */
cmd = ISES_MKCMD(ISES_CMD_LUPLOAD_1, 0);
ises_queue_cmd(sc, cmd, NULL, NULL);
  785         }
  787         if (ints & ISES_STAT_LNAU_BUSY_2) {
DPRINTF(("%s:ises_intr: LNAU 2 job complete\n", dv));
  789                 /* upload LNAU 2 result (into sc->sc_lnau2_r) */
cmd = ISES_MKCMD(ISES_CMD_LUPLOAD_2, 0);
ises_queue_cmd(sc, cmd, NULL, NULL);
  792         }
  794         if (ints & ISES_STAT_LNAU_ERR_1) {
DPRINTF(("%s:ises_intr: LNAU 1 error\n", dv));
sc->sc_lnau1_rlen = -1;
  797         }
  799         if (ints & ISES_STAT_LNAU_ERR_2) {
DPRINTF(("%s:ises_intr: LNAU 2 error\n", dv));
sc->sc_lnau2_rlen = -1;
  802         }
  804         if (ints & ISES_STAT_BCHU_OAF) {        /* output data available */
DPRINTF(("%s:ises_intr: BCHU_OAF bit set\n", dv));
  806                 /* Read DMA data from B-interface. */
ises_read_dma (sc);
  808         }
  810         if (ints & ISES_STAT_BCHU_ERR) {        /* We got a BCHU error */
DPRINTF(("%s:ises_intr: BCHU error\n", dv));
  812                 /* XXX Error handling */
  813         }
  815         if (ints & ISES_STAT_BCHU_OFHF) {       /* Output is half full */
DPRINTF(("%s:ises_intr: BCHU output FIFO half full\n", dv));
  817                 /* XXX drain data? */
  818         }
  820 #if 0 /* XXX Useful? */
  821         if (ints & ISES_STAT_BCHU_OFF) {        /* Output is full */
  822                 /* XXX drain data / error handling? */
  823         }
  824 #endif
  825         return (1);
  826 }
  828 int
ises_feed(struct ises_softc *sc)
  830 {
  831         struct ises_q *q;
bus_dma_segment_t *ds = &sc->sc_dmamap->dm_segs[0];
u_int32_t dma_status;
  834         int s;
  835 #ifdef ISESDEBUG
  836         char *dv = sc->sc_dv.dv_xname;
  837 #endif
DPRINTF(("%s:ises_feed: called (sc = %p)\n", dv, sc));
DELAY(1000000);
s = splnet();
  843         /* Anything to do? */
  844         if (SIMPLEQ_EMPTY(&sc->sc_queue) ||
  845             (READ_REG(sc, ISES_A_STAT) & ISES_STAT_BCHU_IFF)) {
splx(s);
  847                 return (0);
  848         }
  850         /* Pick the first */
q = SIMPLEQ_FIRST(&sc->sc_queue);
splx(s);
  854         /* If we're currently switching sessions, we'll have to wait. */
  855         if (sc->sc_switching != 0) {
DPRINTF(("%s:ises_feed: waiting for session switch\n", dv));
  857                 return (0);
  858         }
  860         /* If on-chip data is not correct for this data, switch session. */
  861         if (sc->sc_cursession != q->q_sesn) {
  862                 /* Session switch required */
DPRINTF(("%s:ises_feed: initiating session switch\n", dv));
  864                 if (ises_bchu_switch_session (sc, &q->q_session, q->q_sesn))
sc->sc_cursession = q->q_sesn;
  866                 else
DPRINTF(("%s:ises_feed: session switch failed\n", dv));
  868                 return (0);
  869         }
DPRINTF(("%s:ises_feed: feed to chip (q = %p)\n", dv, q));
DELAY(2000000);
s = splnet();
SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
  877         --sc->sc_nqueue;
splx(s);
  880         if (q->q_crp->crp_flags & CRYPTO_F_IMBUF)
bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_dmamap, 
q->q_src.mbuf, BUS_DMA_NOWAIT);
  883         else if (q->q_crp->crp_flags & CRYPTO_F_IOV)
bus_dmamap_load_uio(sc->sc_dmat, sc->sc_dmamap, q->q_src.uio,
BUS_DMA_NOWAIT);
  886         /* ... else */  
  888         /* Start writing data to the ises. */
bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0,
sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE);
DPRINTF(("%s:ises_feed: writing DMA\n", dv));
DELAY(1000000);
sc->sc_dma_mask |= ISES_DMA_STATUS_W_RUN;
WRITE_REG(sc, ISES_DMA_WRITE_START, ds->ds_addr);
WRITE_REG(sc, ISES_DMA_WRITE_COUNT, ISES_DMA_WCOUNT(ds->ds_len));
dma_status = READ_REG(sc, ISES_DMA_STATUS);
dma_status |= ISES_DMA_CTRL_ILT | ISES_DMA_CTRL_RLINE;
WRITE_REG(sc, ISES_DMA_CTRL, dma_status);
DPRINTF(("%s:ises_feed: done\n", dv));
  905         return (0);
  906 }
  908 /*
  909  * Allocate a new 'session' and return an encoded session id.  'sidp'
  910  * contains our registration id, and should contain an encoded session
  911  * id on successful allocation.
  912  */
  913 int
ises_newsession(u_int32_t *sidp, struct cryptoini *cri)
  915 {
  916         struct cryptoini *c, *mac = NULL, *enc = NULL;
  917         struct ises_softc *sc = NULL;
  918         struct ises_session *ses;
MD5_CTX    md5ctx;
SHA1_CTX   sha1ctx;
RMD160_CTX rmd160ctx;
  922         int i, sesn;
  923 #ifdef ISESDEBUG
  924         char *dv;
  925 #endif
  927         if (sidp == NULL || cri == NULL)
  928                 return (EINVAL);
  930         for (i = 0; i < ises_cd.cd_ndevs; i++) {
sc = ises_cd.cd_devs[i];
  932                 if (sc == NULL || sc->sc_cid == (*sidp))
  933                         break;
  934         }
  935         if (sc == NULL)
  936                 return (EINVAL);
  937 #ifdef ISESDEBUG
dv = sc->sc_dv.dv_xname;
  939 #endif
DPRINTF(("%s:ises_newsession: start\n", dv));
  943         for (c = cri; c != NULL; c = c->cri_next) {
  944                 if (c->cri_alg == CRYPTO_MD5_HMAC ||
c->cri_alg == CRYPTO_SHA1_HMAC ||
c->cri_alg == CRYPTO_RIPEMD160_HMAC) {
  947                         if (mac)
  948                                 return (EINVAL);
mac = c;
  950                 } else if (c->cri_alg == CRYPTO_DES_CBC ||
c->cri_alg == CRYPTO_3DES_CBC) {
  952                         if (enc)
  953                                 return (EINVAL);
enc = c;
  955                 } else
  956                         return (EINVAL);
  957         }
  958         if (mac == 0 && enc == 0)
  959                 return (EINVAL);
  961 #ifdef ISESDEBUG
printf ("%s:ises_newsession: mac=%p(%d) enc=%p(%d)\n",
dv, mac, (mac ? mac->cri_alg : -1), enc, (enc ? enc->cri_alg : -1));
  964 #endif
  966         /* Allocate a new session */
  967         if (sc->sc_sessions == NULL) {
ses = sc->sc_sessions = (struct ises_session *)
malloc(sizeof(struct ises_session), M_DEVBUF, M_NOWAIT);
  970                 if (ses == NULL) {
isesstats.nomem++;
  972                         return (ENOMEM);
  973                 }
sc->sc_cursession = -1;
sesn = 0;
sc->sc_nsessions = 1;
  977         } else {
ses = NULL;
  979                 for (sesn = 0; sesn < sc->sc_nsessions; sesn++)
  980                         if (sc->sc_sessions[sesn].omr == 0) {
ses = &sc->sc_sessions[sesn];
sc->sc_cursession = sesn;
  983                                 break;
  984                         }
  986                 if (ses == NULL) {
i = sc->sc_nsessions * sizeof(struct ises_session);
ses = (struct ises_session *)
malloc(i + sizeof(struct ises_session), M_DEVBUF,
M_NOWAIT);
  991                         if (ses == NULL) {
isesstats.nomem++;
  993                                 return (ENOMEM);
  994                         }
bcopy(sc->sc_sessions, ses, i);
bzero(sc->sc_sessions, i);
free(sc->sc_sessions, M_DEVBUF);
sc->sc_sessions = ses;
ses = &sc->sc_sessions[sc->sc_nsessions];
sc->sc_cursession = sc->sc_nsessions;
sc->sc_nsessions++;
 1003                 }
 1004         }
DPRINTF(("%s:ises_newsession: nsessions=%d cursession=%d\n", dv,
sc->sc_nsessions, sc->sc_cursession));
bzero(ses, sizeof(struct ises_session));
 1011         /* Select data path through B-interface. */
ses->omr |= ISES_SELR_BCHU_DIS;
 1014         if (enc) {
 1015                 /* get an IV, network byte order */
 1016                 /* XXX switch to using builtin HRNG ! */
get_random_bytes(ses->sccr, sizeof(ses->sccr));
 1019                 /* crypto key */
 1020                 if (enc->cri_alg == CRYPTO_DES_CBC) {
bcopy(enc->cri_key, &ses->kr[0], 8);
bcopy(enc->cri_key, &ses->kr[2], 8);
bcopy(enc->cri_key, &ses->kr[4], 8);
 1024                 } else
bcopy(enc->cri_key, &ses->kr[0], 24);
SWAP32(ses->kr[0]);
SWAP32(ses->kr[1]);
SWAP32(ses->kr[2]);
SWAP32(ses->kr[3]);
SWAP32(ses->kr[4]);
SWAP32(ses->kr[5]);
 1033         }
 1035         if (mac) {
 1036                 for (i = 0; i < mac->cri_klen / 8; i++)
mac->cri_key[i] ^= HMAC_IPAD_VAL;
 1039                 switch (mac->cri_alg) {
 1040                 case CRYPTO_MD5_HMAC:
MD5Init(&md5ctx);
MD5Update(&md5ctx, mac->cri_key, mac->cri_klen / 8);
MD5Update(&md5ctx, hmac_ipad_buffer, HMAC_BLOCK_LEN -
 1044                             (mac->cri_klen / 8));
MD5Final((u_int8_t *)&ses->cvr, &md5ctx);
 1046                         break;
 1047                 case CRYPTO_SHA1_HMAC:
SHA1Init(&sha1ctx);
SHA1Update(&sha1ctx, mac->cri_key, mac->cri_klen / 8);
SHA1Update(&sha1ctx, hmac_ipad_buffer, HMAC_BLOCK_LEN -
 1051                             (mac->cri_klen / 8));
SHA1Final((u_int8_t *)ses->cvr, &sha1ctx);
 1053                         break;
 1054                 case CRYPTO_RIPEMD160_HMAC:
 1055                 default:
RMD160Init(&rmd160ctx);
RMD160Update(&rmd160ctx, mac->cri_key,
mac->cri_klen / 8);
RMD160Update(&rmd160ctx, hmac_ipad_buffer,
HMAC_BLOCK_LEN - (mac->cri_klen / 8));
RMD160Final((u_int8_t *)ses->cvr, &rmd160ctx);
 1062                         break;
 1063                 }
 1065                 for (i = 0; i < mac->cri_klen / 8; i++)
mac->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
 1068                 switch (mac->cri_alg) {
 1069                 case CRYPTO_MD5_HMAC:
MD5Init(&md5ctx);
MD5Update(&md5ctx, mac->cri_key, mac->cri_klen / 8);
MD5Update(&md5ctx, hmac_opad_buffer, HMAC_BLOCK_LEN -
 1073                             (mac->cri_klen / 8));
MD5Update(&md5ctx, (u_int8_t *)ses->cvr,
 1075                             sizeof(md5ctx.state));
MD5Final((u_int8_t *)ses->cvr, &md5ctx);
 1077                         break;
 1078                 case CRYPTO_SHA1_HMAC:
SHA1Init(&sha1ctx);
SHA1Update(&sha1ctx, mac->cri_key, mac->cri_klen / 8);
SHA1Update(&sha1ctx, hmac_opad_buffer, HMAC_BLOCK_LEN -
 1082                             (mac->cri_klen / 8));
SHA1Update(&sha1ctx, (u_int8_t *)ses->cvr,
 1084                             sizeof(sha1ctx.state));
SHA1Final((u_int8_t *)ses->cvr, &sha1ctx);
 1086                         break;
 1087                 case CRYPTO_RIPEMD160_HMAC:
 1088                 default:
RMD160Init(&rmd160ctx);
RMD160Update(&rmd160ctx, mac->cri_key,
mac->cri_klen / 8);
RMD160Update(&rmd160ctx, hmac_opad_buffer,
HMAC_BLOCK_LEN - (mac->cri_klen / 8));
RMD160Update(&rmd160ctx, (u_int8_t *)ses->cvr, 
 1095                             sizeof(rmd160ctx.state));
RMD160Final((u_int8_t *)ses->cvr, &rmd160ctx);
 1097                         break;
 1098                 }
 1100                 for (i = 0; i < mac->cri_klen / 8; i++)
mac->cri_key[i] ^= HMAC_OPAD_VAL;
 1102         }
DPRINTF(("%s:ises_newsession: done\n", dv));
 1105         *sidp = ISES_SID(sc->sc_dv.dv_unit, sesn);
 1106         return (0);
 1107 }
 1109 /* Deallocate a session. */
 1110 int
ises_freesession(u_int64_t tsid)
 1112 {
 1113         struct ises_softc *sc;
 1114         int card, sesn;
u_int32_t sid = ((u_int32_t)tsid) & 0xffffffff;
card = ISES_CARD(sid);
 1118         if (card >= ises_cd.cd_ndevs || ises_cd.cd_devs[card] == NULL)
 1119                 return (EINVAL);
sc = ises_cd.cd_devs[card];
sesn = ISES_SESSION(sid);
DPRINTF(("%s:ises_freesession: freeing session %d\n",
sc->sc_dv.dv_xname, sesn));
 1127         if (sc->sc_cursession == sesn)
sc->sc_cursession = -1;
bzero(&sc->sc_sessions[sesn], sizeof(sc->sc_sessions[sesn]));
 1132         return (0);
 1133 }
 1135 /* Called by the crypto framework, crypto(9). */
 1136 int
ises_process(struct cryptop *crp)
 1138 {
 1139         struct ises_softc *sc;
 1140         struct ises_q *q;
 1141         struct cryptodesc *maccrd, *enccrd, *crd;
 1142         struct ises_session *ses;
 1143         int card, s, err = EINVAL;
 1144         int encoffset, macoffset, cpskip, sskip, dskip, stheend, dtheend;
 1145         int cpoffset, coffset;
 1146 #if 0
 1147         int nicealign;
 1148 #endif
 1149 #ifdef ISESDEBUG
 1150         char *dv;
 1151 #endif
 1153         if (crp == NULL || crp->crp_callback == NULL)
 1154                 return (EINVAL);
card = ISES_CARD(crp->crp_sid);
 1157         if (card >= ises_cd.cd_ndevs || ises_cd.cd_devs[card] == NULL)
 1158                 goto errout;
sc = ises_cd.cd_devs[card];
 1161 #ifdef ISESDEBUG
dv = sc->sc_dv.dv_xname;
 1163 #endif
DPRINTF(("%s:ises_process: start (crp = %p)\n", dv, crp));
s = splnet();
 1168         if (sc->sc_nqueue == ISES_MAX_NQUEUE) {
splx(s);
 1170                 goto memerr;
 1171         }
splx(s);
q = (struct ises_q *)malloc(sizeof(struct ises_q), M_DEVBUF, M_NOWAIT);
 1175         if (q == NULL)
 1176                 goto memerr;
bzero(q, sizeof(struct ises_q));
q->q_sesn = ISES_SESSION(crp->crp_sid);
ses = &sc->sc_sessions[q->q_sesn];
DPRINTF(("%s:ises_process: session %d selected\n", dv, q->q_sesn));
q->q_sc = sc;
q->q_crp = crp;
 1187         if (crp->crp_flags & CRYPTO_F_IMBUF) {
q->q_src.mbuf = (struct mbuf *)crp->crp_buf;
q->q_dst.mbuf = (struct mbuf *)crp->crp_buf;
 1190         } else if (crp->crp_flags & CRYPTO_F_IOV) {
q->q_src.uio = (struct uio *)crp->crp_buf;
q->q_dst.uio = (struct uio *)crp->crp_buf;
 1193         } else {
 1194                 /* XXX for now... */
 1195                 goto errout;
 1196         }
 1198         /*
 1199          * Check if the crypto descriptors are sane. We accept:
 1200          * - just one crd; either auth or crypto
 1201          * - two crds; must be one auth and one crypto, although now
 1202          *   for encryption we only want the first to be crypto, while
 1203          *   for decryption the second one should be crypto.
 1204          */
maccrd = enccrd = NULL;
 1206         for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
 1207                 switch (crd->crd_alg) {
 1208                 case CRYPTO_MD5_HMAC:
 1209                 case CRYPTO_SHA1_HMAC:
 1210                 case CRYPTO_RIPEMD160_HMAC:
 1211                         if (maccrd || (enccrd &&
 1212                             (enccrd->crd_flags & CRD_F_ENCRYPT) == 0))
 1213                                 goto errout;
maccrd = crd;
 1215                         break;
 1216                 case CRYPTO_DES_CBC:
 1217                 case CRYPTO_3DES_CBC:
 1218                         if (enccrd ||
 1219                             (maccrd && (crd->crd_flags & CRD_F_ENCRYPT)))
 1220                                 goto errout;
enccrd = crd;
 1222                         break;
 1223                 default:
 1224                         goto errout;
 1225                 }
 1226         }
 1227         if (!maccrd && !enccrd)
 1228                 goto errout;
DPRINTF(("%s:ises_process: enc=%p mac=%p\n", dv, enccrd, maccrd));
 1232         /* Select data path through B-interface. */
q->q_session.omr |= ISES_SELR_BCHU_DIS;
 1235         if (enccrd) {
encoffset = enccrd->crd_skip;
 1238                 /* Select algorithm */
 1239                 if (enccrd->crd_alg == CRYPTO_3DES_CBC)
q->q_session.omr |= ISES_SOMR_BOMR_3DES;
 1241                 else
q->q_session.omr |= ISES_SOMR_BOMR_DES;
 1244                 /* Set CBC mode */
q->q_session.omr |= ISES_SOMR_FMR_CBC;
 1247                 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
 1248                         /* Set encryption bit */
q->q_session.omr |= ISES_SOMR_EDR;
 1251                         if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
bcopy(enccrd->crd_iv, q->q_session.sccr, 8);
 1253                         else {
q->q_session.sccr[0] = ses->sccr[0];
q->q_session.sccr[1] = ses->sccr[1];
 1256                         }
 1258                         if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
 1259                                 if (crp->crp_flags & CRYPTO_F_IMBUF)
m_copyback(q->q_src.mbuf,
enccrd->crd_inject, 8,
 1262                                             (caddr_t)q->q_session.sccr);
 1263                                 else if (crp->crp_flags & CRYPTO_F_IOV)
cuio_copyback(q->q_src.uio,
enccrd->crd_inject, 8,
 1266                                             (caddr_t)q->q_session.sccr);
 1267                                 /* XXX else ... */
 1268                         }
 1269                 } else {
 1270                         /* Clear encryption bit == decrypt mode */
q->q_session.omr &= ~ISES_SOMR_EDR;
 1273                         if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
bcopy(enccrd->crd_iv, q->q_session.sccr, 8);
 1275                         else if (crp->crp_flags & CRYPTO_F_IMBUF)
m_copydata(q->q_src.mbuf, enccrd->crd_inject,
 1277                                     8, (caddr_t)q->q_session.sccr);
 1278                         else if (crp->crp_flags & CRYPTO_F_IOV)
cuio_copydata(q->q_src.uio,
enccrd->crd_inject, 8,
 1281                                     (caddr_t)q->q_session.sccr);
 1282                         /* XXX else ... */
 1283                 }
q->q_session.kr[0] = ses->kr[0];
q->q_session.kr[1] = ses->kr[1];
q->q_session.kr[2] = ses->kr[2];
q->q_session.kr[3] = ses->kr[3];
q->q_session.kr[4] = ses->kr[4];
q->q_session.kr[5] = ses->kr[5];
SWAP32(q->q_session.sccr[0]);
SWAP32(q->q_session.sccr[1]);
 1294         }
 1296         if (maccrd) {
macoffset = maccrd->crd_skip;
 1299                 /* Select algorithm */
 1300                 switch (crd->crd_alg) {
 1301                 case CRYPTO_MD5_HMAC:
q->q_session.omr |= ISES_HOMR_HFR_MD5;
 1303                         break;
 1304                 case CRYPTO_SHA1_HMAC:
q->q_session.omr |= ISES_HOMR_HFR_SHA1;
 1306                         break;
 1307                 case CRYPTO_RIPEMD160_HMAC:
 1308                 default:
q->q_session.omr |= ISES_HOMR_HFR_RMD160;
 1310                         break;
 1311                 }
q->q_session.cvr[0] = ses->cvr[0];
q->q_session.cvr[1] = ses->cvr[1];
q->q_session.cvr[2] = ses->cvr[2];
q->q_session.cvr[3] = ses->cvr[3];
q->q_session.cvr[4] = ses->cvr[4];
 1318         }
 1320         if (enccrd && maccrd) {
 1321                 /* XXX Check if ises handles differing end of auth/enc etc */
 1322                 /* XXX For now, assume not (same as ubsec). */
 1323                 if (((encoffset + enccrd->crd_len) !=
 1324                     (macoffset + maccrd->crd_len)) ||
 1325                     (enccrd->crd_skip < maccrd->crd_skip)) {
 1326                         goto errout;
 1327                 }
sskip = maccrd->crd_skip;
cpskip = dskip = enccrd->crd_skip;
stheend = maccrd->crd_len;
dtheend = enccrd->crd_len;
coffset = cpskip - sskip;
cpoffset = cpskip + dtheend;
 1335                 /* XXX DEBUG ? */
 1336         } else {
cpskip = dskip = sskip = macoffset + encoffset;
dtheend = enccrd ? enccrd->crd_len : maccrd->crd_len;
stheend = dtheend;
cpoffset = cpskip + dtheend;
coffset = 0;
 1342         }
q->q_offset = coffset >> 2;
 1345 #if 0   /* XXX not sure about this, in bus_dma context */
 1347         if (crp->crp_flags & CRYPTO_F_IMBUF)
q->q_src_l = mbuf2pages(q->q_src.mbuf, &q->q_src_npa,
q->q_src_packp, q->q_src_packl, 1, &nicealign);
 1350         else if (crp->crp_flags & CRYPTO_F_IOV)
q->q_src_l = iov2pages(q->q_src.uio, &q->q_src_npa,
q->q_src_packp, q->q_src_packl, 1, &nicealign);
 1353         /* XXX else */
DPRINTF(("%s:ises_process: foo2pages called!\n", dv));
 1357         if (q->q_src_l == 0)
 1358                 goto memerr;
 1359         else if (q->q_src_l > 0xfffc) {
err = EIO;
 1361                 goto errout;
 1362         }
 1364         /* XXX ... */
 1366         if (enccrd == NULL && maccrd != NULL) {
 1367                 /* XXX ... */
 1368         } else {
 1369                 if (!nicealign && (crp->crp_flags & CRYPTO_F_IOV)) {
 1370                         goto errout;
 1371                 } else if (!nicealign && (crp->crp_flags & CRYPTO_F_IMBUF)) {
 1372                         int totlen, len;
 1373                         struct mbuf *m, *top, **mp;
totlen = q->q_dst_l = q->q_src_l;
 1376                         if (q->q_src.mbuf->m_flags & M_PKTHDR) {
MGETHDR(m, M_DONTWAIT, MT_DATA);
M_DUP_PKTHDR(m, q->q_src.mbuf);
len = MHLEN;
 1380                         } else {
MGET(m, M_DONTWAIT, MT_DATA);
len = MLEN;
 1383                         }
 1384                         if (m == NULL)
 1385                                 goto memerr;
 1386                         if (totlen >= MINCLSIZE) {
MCLGET(m, M_DONTWAIT);
 1388                                 if (m->m_flags & M_EXT)
len = MCLBYTES;
 1390                         }
m->m_len = len;
top = NULL;
mp = &top;
 1395                         while (totlen > 0) {
 1396                                 if (top) {
MGET(m, M_DONTWAIT, MT_DATA);
 1398                                         if (m == NULL) {
m_freem(top);
 1400                                                 goto memerr;
 1401                                         }
len = MLEN;
 1403                                 }
 1404                                 if (top && totlen >= MINCLSIZE) {
MCLGET(m, M_DONTWAIT);
 1406                                         if (m->m_flags & M_EXT)
len = MCLBYTES;
 1408                                 }
m->m_len = len = min(totlen, len);
totlen -= len;
 1411                                 *mp = m;
mp = &m->m_next;
 1414                         }
q->q_dst.mbuf = top;
 1416 #if notyet
ubsec_mcopy(q->q_src.mbuf, q->q_dst.mbuf, cpskip, cpoffset);
 1418 #endif
 1419                 } else
q->q_dst.mbuf = q->q_src.mbuf;
 1422 #if 0
 1423                 /* XXX ? */
q->q_dst_l = mbuf2pages(q->q_dst.mbuf, &q->q_dst_npa,
 1425                     &q->q_dst_packp, &q->q_dst_packl, 1, NULL);
 1426 #endif
 1427         }
 1429 #endif /* XXX */
DPRINTF(("%s:ises_process: queueing request\n", dv));
s = splnet();
SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
sc->sc_nqueue++;
splx(s);
ises_feed(sc);
 1439         return (0);
memerr:
err = ENOMEM;
isesstats.nomem++;
errout:
DPRINTF(("%s:ises_process: an error occurred, err=%d, q=%p\n", dv, 
err, q));
 1448         if (err == EINVAL)
isesstats.invalid++;
 1451         if (q) {
 1452                 if (q->q_src.mbuf != q->q_dst.mbuf)
m_freem(q->q_dst.mbuf);
free(q, M_DEVBUF);
 1455         }
crp->crp_etype = err;
crypto_done(crp);
 1458         return (0);
 1459 }
 1461 void
ises_callback(struct ises_q *q)
 1463 {
 1464         struct cryptop *crp = (struct cryptop *)q->q_crp;
 1465         struct cryptodesc *crd;
 1466         struct ises_softc *sc = q->q_sc;
u_int8_t *sccr;
 1469         if ((crp->crp_flags & CRYPTO_F_IMBUF) && 
 1470             (q->q_src.mbuf != q->q_dst.mbuf)) {
m_freem(q->q_src.mbuf);
crp->crp_buf = (caddr_t)q->q_dst.mbuf;
 1473         }
 1475         if (q->q_session.omr & ISES_SOMR_EDR) {
 1476                 /* Copy out IV after encryption. */
sccr = (u_int8_t *)&sc->sc_sessions[q->q_sesn].sccr;
 1478                 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
 1479                         if (crd->crd_alg != CRYPTO_DES_CBC &&
crd->crd_alg != CRYPTO_3DES_CBC)
 1481                                 continue;
 1482                         if (crp->crp_flags & CRYPTO_F_IMBUF)
m_copydata((struct mbuf *)crp->crp_buf,
crd->crd_skip + crd->crd_len - 8, 8, sccr);
 1485                         else if (crp->crp_flags & CRYPTO_F_IOV)
cuio_copydata((struct uio *)crp->crp_buf,
crd->crd_skip + crd->crd_len - 8, 8, sccr);
 1488                 }
 1489         }
 1491         for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
 1492                 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
crd->crd_alg != CRYPTO_SHA1_HMAC &&
crd->crd_alg != CRYPTO_RIPEMD160_HMAC)
 1495                         continue;
 1496                 if (crp->crp_flags & CRYPTO_F_IMBUF)
m_copyback((struct mbuf *)crp->crp_buf,
crd->crd_inject, 12, (u_int8_t *)q->q_macbuf);
 1499                 else if (crp->crp_flags & CRYPTO_F_IOV)
bcopy((u_int8_t *)q->q_macbuf, crp->crp_mac, 12);
 1501                 /* XXX else ... */
 1502                 break;
 1503         }
free(q, M_DEVBUF);
DPRINTF(("%s:ises_callback: calling crypto_done\n",
sc->sc_dv.dv_xname));
crypto_done(crp);
 1509 }
 1511 /* Initilize the ISES hardware RNG, and set up timeouts. */
 1512 void
ises_hrng_init(struct ises_softc *sc)
 1514 {
u_int32_t cmd, r;
 1516         int i;
 1517 #ifdef ISESDEBUG
 1518         struct timeval tv1, tv2;
 1519 #endif
 1521         /* Asking for random data will seed LFSR and start the RBG */
cmd = ISES_MKCMD(ISES_CMD_HBITS, 1);
r   = 8; /* 8 * 32 = 256 bits */
 1525         if (ises_queue_cmd(sc, cmd, &r, NULL))
 1526                 return;
 1528         /* Wait until response arrives. */
 1529         for (i = 1000; i && READ_REG(sc, ISES_A_OQS) == 0; i--)
DELAY(10);
 1532         if (!READ_REG(sc, ISES_A_OQS))
 1533                 return;
 1535         /* Drain cmd response and 8*32 bits data */
 1536         for (i = 0; i <= r; i++)
 1537                 (void)READ_REG(sc, ISES_A_OQD);
 1539         /* ACK the response */
WRITE_REG(sc, ISES_A_OQS, 0);
DELAY(1);
printf(", rng active");
 1544 #ifdef ISESDEBUG
 1545         /* Benchmark the HRNG. */
 1547         /*
 1548          * XXX These values gets surprisingly large. Docs state the
 1549          * HNRG produces > 1 mbit/s of random data. The values I'm seeing
 1550          * are much higher, ca 2.7-2.8 mbit/s. AFAICT the algorithm is sound.
 1551          * Compiler optimization issues, perhaps?
 1552          */
 1554 #define ISES_WPR 250
 1555 #define ISES_ROUNDS 100
cmd = ISES_MKCMD(ISES_CMD_HBITS, 1);
r = ISES_WPR;
 1559         /* Queue 100 cmds; each generate 250 32-bit words of rnd data. */
microtime(&tv1);
 1561         for (i = 0; i < ISES_ROUNDS; i++)
ises_queue_cmd(sc, cmd, &r, NULL);
 1563         for (i = 0; i < ISES_ROUNDS; i++) {
 1564                 while (READ_REG(sc, ISES_A_OQS) == 0) ; /* Wait for response */
 1566                 (void)READ_REG(sc, ISES_A_OQD);         /* read response */
 1567                 for (r = ISES_WPR; r--;)
 1568                         (void)READ_REG(sc, ISES_A_OQD); /* read data */
WRITE_REG(sc, ISES_A_OQS, 0);           /* ACK resp */
DELAY(1); /* OQS needs 1us to decrement */
 1571         }
microtime(&tv2);
timersub(&tv2, &tv1, &tv1);
tv1.tv_usec += 1000000 * tv1.tv_sec;
printf(", %dKb/sec",
ISES_WPR * ISES_ROUNDS * 32 / 1024 * 1000000 / tv1.tv_usec);
 1578 #endif
timeout_set(&sc->sc_timeout, ises_hrng, sc);
 1581 #ifndef ISES_HRNG_DISABLED
ises_hrng(sc); /* Call first update */
 1583 #endif
 1584 }
 1586 /* Called by timeout (and once by ises_init_hrng()). */
 1587 void
ises_hrng(void *v)
 1589 {
 1590         /*
 1591          * Throw a HRNG read random bits command on the command queue.
 1592          * The normal loop will manage the result and add it to the pool.
 1593          */
 1594         struct ises_softc *sc = v;
u_int32_t cmd, n;
 1596         extern int hz; /* from param.c */
timeout_add(&sc->sc_timeout, hz / ISESRNGIPS);
 1600         if (ises_assert_cmd_mode(sc) != 0)
 1601                 return;
cmd = ISES_MKCMD(ISES_CMD_HBITS, 1);
n   = (ISESRNGBITS >> 5) & 0xff; /* ask for N 32 bit words */
ises_queue_cmd(sc, cmd, &n, NULL);
 1607 }
u_int32_t
ises_get_fwversion(struct ises_softc *sc)
 1611 {
u_int32_t r;
 1613         int i;
r = ISES_MKCMD(ISES_CMD_CHIP_ID, 0);
WRITE_REG(sc, ISES_A_IQD, r);
WRITE_REG(sc, ISES_A_IQS, 0);
 1619         for (i = 100; i > 0 && READ_REG(sc, ISES_A_OQS) == 0; i--)
DELAY(1);
 1622         if (i < 1)
 1623                 return (0); /* No response */
r = READ_REG(sc, ISES_A_OQD);
 1627         /* Check validity. On error drain reponse data. */
 1628         if (((r >> 16) & 0xff) != ISES_CMD_CHIP_ID ||
 1629             ((r >> 24) & 0xff) != 3 || (r & ISES_RC_MASK) != ISES_RC_SUCCESS) {
 1630                 if ((r & ISES_RC_MASK) == ISES_RC_SUCCESS)
 1631                         for (i = ((r >> 24) & 0xff); i; i--)
 1632                                 (void)READ_REG(sc, ISES_A_OQD);
r = 0;
 1634                 goto out;
 1635         }
r = READ_REG(sc, ISES_A_OQD); /* read version */
 1638         (void)READ_REG(sc, ISES_A_OQD); /* Discard 64bit "chip-id" */
 1639         (void)READ_REG(sc, ISES_A_OQD);
out:
WRITE_REG(sc, ISES_A_OQS, 0); /* Ack the response */
DELAY(1);
 1643         return (r);
 1644 }
 1646 /*
 1647  * ises_assert_cmd_mode() returns
 1648  *   -1 for failure to go to cmd
 1649  *    0 if mode already was cmd
 1650  *   >0 if mode was other (WFC/WFR) but now is cmd (this has reset the queues)
 1651  */
 1652 int
ises_assert_cmd_mode(struct ises_softc *sc)
 1654 {
 1655         switch (ISES_STAT_SW_MODE(READ_REG(sc, ISES_A_STAT))) {
 1656         case 0x0: /* Selftest. XXX This is a transient state. */
DELAY(1000000);
 1658                 if (ISES_STAT_SW_MODE(READ_REG(sc, ISES_A_STAT)) == 0)
 1659                         return (-1);
 1660                 return (ises_assert_cmd_mode(sc));
 1661         case 0x1: /* Command mode */
 1662                 return (0);
 1663         case 0x2: /* Waiting For Continue / WFC */
bus_space_write_2(sc->sc_memt, sc->sc_memh, ISES_A_CTRL,
ISES_A_CTRL_CONTINUE);
DELAY(1);
 1667                 return ((ISES_STAT_SW_MODE(READ_REG(sc, ISES_A_STAT)) == 0) ?
 1668                     1 : -1);
 1669         case 0x3: /* Waiting For Reset / WFR */
bus_space_write_2(sc->sc_memt, sc->sc_memh, ISES_A_CTRL,
ISES_A_CTRL_RESET);
DELAY(1000000);
 1673                 return ((ISES_STAT_SW_MODE(READ_REG(sc, ISES_A_STAT)) == 0) ?
 1674                     2 : -1);
 1675         default:
 1676                 return (-1); /* Unknown mode */
 1677         }
 1678 }
 1680 int
ises_bchu_switch_session (struct ises_softc *sc, struct ises_session *ss, 
 1682                           int new_session)
 1683 {
 1684         /* It appears that the BCHU_SWITCH_SESSION command is broken. */
 1685         /* We have to work around it. */
u_int32_t cmd;
 1689         /* Do we have enough in-queue space? Count cmds + data, 16bit words. */
 1690         if ((8 * 2 + sizeof (*ss) / 2) > READ_REG(sc, ISES_A_IQF))
 1691                 return (0);
 1693         /* Mark 'switch' in progress. */
sc->sc_switching = new_session + 1;
 1696         /* Write the key. */
cmd = ISES_MKCMD(ISES_CMD_BW_KR0, 2);
ises_queue_cmd(sc, cmd, &ss->kr[4], NULL);
cmd = ISES_MKCMD(ISES_CMD_BW_KR1, 2);
ises_queue_cmd(sc, cmd, &ss->kr[2], NULL);
cmd = ISES_MKCMD(ISES_CMD_BW_KR2, 2);
ises_queue_cmd(sc, cmd, &ss->kr[0], NULL);
 1704         /* Write OMR - Operation Method Register, clears SCCR+CVR+DBCR+HMLR */
cmd = ISES_MKCMD(ISES_CMD_BW_OMR, 1);
ises_queue_cmd(sc, cmd, &ss->omr, NULL);
 1708         /* Write SCCR - Symmetric Crypto Chaining Register (IV) */
cmd = ISES_MKCMD(ISES_CMD_BW_SCCR, 2);
ises_queue_cmd(sc, cmd, &ss->sccr[0], NULL);
 1712         /* Write CVR - Chaining Variables Register (hash state) */
cmd = ISES_MKCMD(ISES_CMD_BW_CVR, 5);
ises_queue_cmd(sc, cmd, &ss->cvr[0], NULL);
 1716         /* Write DBCR - Data Block Count Register */
cmd = ISES_MKCMD(ISES_CMD_BW_DBCR, 2);
ises_queue_cmd(sc, cmd, &ss->dbcr[0], NULL);
 1720         /* Write HMLR - Hash Message Length Register - last cmd in switch */
cmd = ISES_MKCMD(ISES_CMD_BW_HMLR, 2);
ises_queue_cmd(sc, cmd, &ss->hmlr[0], ises_bchu_switch_final);
 1724         return (1);
 1725 }
u_int32_t
ises_bchu_switch_final (struct ises_softc *sc, struct ises_cmd *cmd)
 1729 {
 1730         /* Session switch is complete. */
DPRINTF(("%s:ises_bchu_switch_final: switch complete\n",
sc->sc_dv.dv_xname));
sc->sc_cursession = sc->sc_switching - 1;
sc->sc_switching = 0;
 1738         /* Retry/restart feed. */
ises_feed(sc);
 1741         return (0);
 1742 }
 1744 /* XXX Currently unused. */
 1745 void
ises_read_dma (struct ises_softc *sc)
 1747 {
bus_dma_segment_t *ds = &sc->sc_dmamap->dm_segs[0];
u_int32_t dma_status;
bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0,
sc->sc_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
WRITE_REG(sc, ISES_DMA_READ_START, ds->ds_addr);
WRITE_REG(sc, ISES_DMA_READ_START, ISES_DMA_RCOUNT(ds->ds_len));
dma_status = READ_REG(sc, ISES_DMA_STATUS);
dma_status |= ISES_DMA_CTRL_ILT | ISES_DMA_CTRL_WRITE;
WRITE_REG(sc, ISES_DMA_CTRL, dma_status);
 1760 }
 1762 #ifdef ISESDEBUG
 1763 /*
 1764  * Development code section below here.
 1765  */
 1767 void
ises_debug_init (struct ises_softc *sc)
 1769 {
ises_sc = sc;
ises_db = 0;
timeout_set (&ises_db_timeout, ises_debug_loop, sc);
timeout_add (&ises_db_timeout, 100);
printf ("ises0: ISESDEBUG active (ises_sc = %p)\n", ises_sc);
 1775 }
 1777 void
ises_debug_2 (void)
 1779 {
timeout_set (&ises_db_timeout, ises_debug_loop, ises_sc);
timeout_add (&ises_db_timeout, 100);
printf ("ises0: another debug timeout scheduled!\n");
 1783 }
 1785 void
ises_debug_simple_cmd (struct ises_softc *sc, u_int32_t code, u_int32_t d)
 1787 {
u_int32_t cmd, data;
cmd = ISES_MKCMD(code, (d ? 1 : 0));
data = d;
ises_queue_cmd(sc, cmd, &d, NULL);
 1793 }
 1795 void
ises_debug_loop (void *v)
 1797 {
 1798         struct ises_softc *sc = (struct ises_softc *)v;
 1799         struct ises_session ses;
u_int32_t cmd, stat;
 1801         int i;
 1803         if (ises_db)
printf ("ises0: ises_db = %d  sc = %p\n", ises_db, sc);
timeout_add (&ises_db_timeout, 300); /* Every 3 secs */
stat = READ_REG(sc, ISES_A_OQS);
cmd  = READ_REG(sc, ISES_A_IQS);
 1810         if (stat || cmd)
printf ("ises0: IQS=%d OQS=%d / IQF=%d OQF=%d\n",
cmd, stat, READ_REG(sc, ISES_A_IQF),
READ_REG(sc, ISES_A_OQF));
 1815         switch (ises_db) {
 1816         default: 
 1817                 /* 0 - do nothing (just loop) */
 1818                 break;
 1819         case 1:
 1820                 /* Just dump register info */
ises_showreg();
 1822                 break;
 1823         case 2:
 1824                 /* Reset LNAU 1 registers */
ises_debug_simple_cmd(sc, ISES_CMD_LRESET_1, 0);
 1827                 /* Compute R = (141 * 5623) % 117 (R should be 51 (0x33)) */
ises_debug_simple_cmd(sc, ISES_CMD_LW_A_1, 141);
ises_debug_simple_cmd(sc, ISES_CMD_LW_B_1, 5623);
ises_debug_simple_cmd(sc, ISES_CMD_LW_N_1, 117);
 1832                 /* Launch LNAU operation. */
ises_debug_simple_cmd(sc, ISES_CMD_LMULMOD_1, 0);
 1834                 break;
 1835         case 3:
 1836                 /* Read result LNAU_1 R register (should not be necessary) */
ises_debug_simple_cmd(sc, ISES_CMD_LUPLOAD_1, 0);
 1838                 break;
 1839         case 4:
 1840                 /* Print result */
printf ("LNAU_1 R length = %d\n", sc->sc_lnau1_rlen);
 1842                 for (i = 0; i < sc->sc_lnau1_rlen; i++)
printf ("W%02d-[%08x]-(%u)\t%s", i, sc->sc_lnau1_r[i],
sc->sc_lnau1_r[i], (i%4)==3 ? "\n" : "");
printf ("%s", (i%4) ? "\n" : "");
 1846                 break;
 1847         case 5:
 1848                 /* Crypto. */
 1850                 /* Load BCHU session data */
bzero(&ses, sizeof ses);
ses.kr[0] = 0xD0;
ses.kr[1] = 0xD1;
ses.kr[2] = 0xD2;
ses.kr[3] = 0xD3;
ses.kr[4] = 0xD4;
ses.kr[5] = 0xD5;
 1859                 /* cipher data out is hash in, SHA1, 3DES, encrypt, ECB */
ses.omr = ISES_SELR_BCHU_HISOF | ISES_HOMR_HFR_SHA1 |
ISES_SOMR_BOMR_3DES | ISES_SOMR_EDR | ISES_SOMR_FMR_ECB;
 1863 #if 1
printf ("Queueing home-cooked session switch\n");
ises_bchu_switch_session(sc, &ses, 0);
 1866 #else /* switch session does not appear to work - it never returns */
printf ("Queueing BCHU session switch\n");
cmd = ISES_MKCMD(ISES_CMD_BSWITCH, sizeof ses / 4);
printf ("session is %d 32bit words (== 18 ?), cmd = [%08x]\n", 
 1870                         sizeof ses / 4, cmd);
ises_queue_cmd(sc, cmd, (u_int32_t *)&ses, NULL);
 1872 #endif
 1874                 break;
 1875         case 96:
printf ("Stopping HRNG data collection\n");
timeout_del(&sc->sc_timeout);
 1878                 break;
 1879         case 97:
printf ("Restarting HRNG data collection\n");
 1881                 if (!timeout_pending(&sc->sc_timeout))
timeout_add(&sc->sc_timeout, hz);
 1883                 break;
 1884         case 98:
printf ("Resetting (wait >1s before cont.)\n");
stat = ISES_BO_STAT_HWRESET;
WRITE_REG(sc, ISES_BO_STAT, stat);
stat &= ~ISES_BO_STAT_HWRESET;
WRITE_REG(sc, ISES_BO_STAT, stat);
 1890                 break;
 1891         case 99:
printf ("Resetting everything!\n");
 1893                 if (timeout_pending(&sc->sc_timeout))
timeout_del(&sc->sc_timeout);
timeout_set(&sc->sc_timeout, ises_initstate, sc);
sc->sc_initstate = 0;
ises_initstate(sc);
 1898                 break;
 1899         }
ises_db = 0; 
 1902 }
 1904 void
ises_showreg (void)
 1906 {
 1907         struct ises_softc *sc = ises_sc;
u_int32_t stat, cmd;
 1910         /* Board register */
printf ("Board register: ");
stat = READ_REG(sc, ISES_BO_STAT);
 1915         if (stat & ISES_BO_STAT_LOOP)
printf ("LoopMode ");
 1917         if (stat & ISES_BO_STAT_TAMPER)
printf ("Tamper ");
 1919         if (stat & ISES_BO_STAT_POWERDOWN)
printf ("PowerDown ");
 1921         if (stat & ISES_BO_STAT_ACONF)
printf ("16bitA-IF ");
 1923         if (stat & ISES_BO_STAT_HWRESET)
printf ("HWReset");
 1925         if (stat & ISES_BO_STAT_AIRQ)
printf ("A-IFintr");
printf("\n");
 1929         /* A interface */
printf ("A Interface STAT register: \n\tLNAU-[");
stat = READ_REG(sc, ISES_A_STAT);
 1933         if (stat & ISES_STAT_LNAU_MASKED)
printf ("masked");
 1935         else {
 1936                 if (stat & ISES_STAT_LNAU_BUSY_1)
printf ("busy1 ");
 1938                 if (stat & ISES_STAT_LNAU_ERR_1)
printf ("err1 ");
 1940                 if (stat & ISES_STAT_LNAU_BUSY_2)
printf ("busy2 ");
 1942                 if (stat & ISES_STAT_LNAU_ERR_2)
printf ("err2 ");
 1944         }
printf ("]\n\tBCHU-[");
 1947         if (stat & ISES_STAT_BCHU_MASKED)
printf ("masked");
 1949         else {
 1950                 if (stat & ISES_STAT_BCHU_BUSY)
printf ("busy ");
 1952                 if (stat & ISES_STAT_BCHU_ERR)
printf ("err ");
 1954                 if (stat & ISES_STAT_BCHU_SCIF)
printf ("cr-inop ");
 1956                 if (stat & ISES_STAT_BCHU_HIF)
printf ("ha-inop ");
 1958                 if (stat & ISES_STAT_BCHU_DDB)
printf ("dscd-data ");
 1960                 if (stat & ISES_STAT_BCHU_IRF)
printf ("inp-req ");
 1962                 if (stat & ISES_STAT_BCHU_OAF)
printf ("out-avail ");
 1964                 if (stat & ISES_STAT_BCHU_DIE)
printf ("inp-enabled ");
 1966                 if (stat & ISES_STAT_BCHU_UE)
printf ("ififo-empty ");
 1968                 if (stat & ISES_STAT_BCHU_IFE)
printf ("ififo-half ");
 1970                 if (stat & ISES_STAT_BCHU_IFHE)
printf ("ififo-full ");
 1972                 if (stat & ISES_STAT_BCHU_OFE)
printf ("ofifo-empty ");
 1974                 if (stat & ISES_STAT_BCHU_OFHF)
printf ("ofifo-half ");
 1976                 if (stat & ISES_STAT_BCHU_OFF)
printf ("ofifo-full ");
 1978         }
printf ("] \n\tmisc-[");
 1981         if (stat & ISES_STAT_HW_DA)
printf ("downloaded-appl ");
 1983         if (stat & ISES_STAT_HW_ACONF)
printf ("A-IF-conf ");
 1985         if (stat & ISES_STAT_SW_WFOQ)
printf ("OQ-wait ");
 1987         if (stat & ISES_STAT_SW_OQSINC)
printf ("OQS-increased ");
printf ("]\n\t");
 1991         if (stat & ISES_STAT_HW_DA)
printf ("SW-mode is \"%s\"", 
ises_sw_mode[ISES_STAT_SW_MODE(stat)]);
 1994         else
printf ("IDP-state is \"%s\"", 
ises_idp_state[ISES_STAT_IDP_STATE(stat)]);
printf ("\n");
printf ("\tOQS = %d  IQS = %d  OQF = %d  IQF = %d\n", 
READ_REG(sc, ISES_A_OQS), READ_REG(sc, ISES_A_IQS),
READ_REG(sc, ISES_A_OQF), READ_REG(sc, ISES_A_IQF));
 2003         /* B interface */
printf ("B-interface status register contains [%08x]\n", 
READ_REG(sc, ISES_B_STAT));
 2008         /* DMA */
printf ("DMA read starts at 0x%x, length %d bytes\n", 
READ_REG(sc, ISES_DMA_READ_START), 
READ_REG(sc, ISES_DMA_READ_COUNT) >> 16);
printf ("DMA write starts at 0x%x, length %d bytes\n",
READ_REG(sc, ISES_DMA_WRITE_START),
READ_REG(sc, ISES_DMA_WRITE_COUNT) & 0x00ff);
stat = READ_REG(sc, ISES_DMA_STATUS);
printf ("DMA status register contains [%08x]\n", stat);
 2021         if (stat & ISES_DMA_CTRL_ILT)
printf (" -- Ignore latency timer\n");
 2023         if (stat & 0x0C000000)
printf (" -- PCI Read - multiple\n");
 2025         else if (stat & 0x08000000)
printf (" -- PCI Read - line\n");
 2028         if (stat & ISES_DMA_STATUS_R_RUN)
printf (" -- PCI Read running/incomplete\n");
 2030         else
printf (" -- PCI Read complete\n");
 2032         if (stat & ISES_DMA_STATUS_R_ERR)
printf (" -- PCI Read DMA Error\n");
 2035         if (stat & ISES_DMA_STATUS_W_RUN)
printf (" -- PCI Write running/incomplete\n");
 2037         else
printf (" -- PCI Write complete\n");
 2039         if (stat & ISES_DMA_STATUS_W_ERR)
printf (" -- PCI Write DMA Error\n");
 2042         /* OMR / HOMR / SOMR */
 2044         /*
 2045          * All these means throwing a cmd on to the A-interface, and then
 2046          * reading the result.
 2047          *
 2048          * Currently, put debug output in process_oqueue...
 2049          */
printf ("Queueing Operation Method Register (OMR) READ cmd...\n");
cmd = ISES_MKCMD(ISES_CMD_BR_OMR, 0);
ises_queue_cmd(sc, cmd, NULL, NULL);
 2054 }
 2056 void
ises_debug_parse_omr (struct ises_softc *sc)
 2058 {
u_int32_t omr = sc->sc_sessions[sc->sc_cursession].omr;
printf ("SELR : ");
 2062         if (omr & ISES_SELR_BCHU_EH)
printf ("cont-on-error ");
 2064         else
printf ("stop-on-error ");
 2067         if (omr & ISES_SELR_BCHU_HISOF)
printf ("HU-input-is-SCU-output ");
 2070         if (omr & ISES_SELR_BCHU_DIS)
printf ("data-interface-select=B ");
 2072         else
printf ("data-interface-select=DataIn/DataOut ");
printf ("\n");
printf ("HOMR : ");
 2078         if (omr & ISES_HOMR_HMTR)
printf ("expect-padded-hash-msg ");
 2080         else
printf ("expect-plaintext-hash-msg ");
printf ("ER=%d ", (omr & ISES_HOMR_ER) >> 20); /* ick */
printf ("HFR=");
 2086         switch (omr & ISES_HOMR_HFR) {
 2087         case ISES_HOMR_HFR_NOP:
printf ("inactive ");
 2089                 break;
 2090         case ISES_HOMR_HFR_MD5:
printf ("MD5 ");
 2092                 break;
 2093         case ISES_HOMR_HFR_RMD160:
printf ("RMD160 ");
 2095                 break;
 2096         case ISES_HOMR_HFR_RMD128:
printf ("RMD128 ");
 2098                 break;
 2099         case ISES_HOMR_HFR_SHA1:
printf ("SHA-1 ");
 2101                 break;
 2102         default:
printf ("reserved! ");
 2104                 break;
 2105         }
printf ("\nSOMR : ");
 2108         switch (omr & ISES_SOMR_BOMR) {
 2109         case ISES_SOMR_BOMR_NOP:
printf ("NOP ");
 2111                 break;
 2112         case ISES_SOMR_BOMR_TRANSPARENT:
printf ("transparent ");
 2114                 break;
 2115         case ISES_SOMR_BOMR_DES:
printf ("DES ");
 2117                 break;
 2118         case ISES_SOMR_BOMR_3DES2:
printf ("3DES-2 ");
 2120                 break;
 2121         case ISES_SOMR_BOMR_3DES:
printf ("3DES-3 ");
 2123                 break;
 2124         default:
 2125                 if (omr & ISES_SOMR_BOMR_SAFER)
printf ("SAFER ");
 2127                 else
printf ("reserved! ");
 2129                 break;
 2130         }
 2132         if (omr & ISES_SOMR_EDR)
printf ("mode=encrypt ");
 2134         else
printf ("mode=decrypt ");
 2137         switch (omr & ISES_SOMR_FMR) {
 2138         case ISES_SOMR_FMR_ECB:
printf ("ECB");
 2140                 break;
 2141         case ISES_SOMR_FMR_CBC:
printf ("CBC");
 2143                 break;
 2144         case ISES_SOMR_FMR_CFB64:
printf ("CFB64");
 2146                 break;
 2147         case ISES_SOMR_FMR_OFB64:
printf ("OFB64");
 2149                 break;
 2150         default:
 2151                 /* Nada */
 2152         }
printf ("\n");
 2154 }
 2156 #endif /* ISESDEBUG */