WRITE_REG 1375 dev/pci/if_san_te1.c WRITE_REG(REG_XLPG_WAVEFORM_ADDR, indirect_addr); WRITE_REG 1376 dev/pci/if_san_te1.c WRITE_REG(REG_XLPG_WAVEFORM_DATA, 0x00); WRITE_REG 1447 dev/pci/if_san_te1.c WRITE_REG(REG_XLPG_WAVEFORM_ADDR, indirect_addr); WRITE_REG 1448 dev/pci/if_san_te1.c WRITE_REG(REG_XLPG_WAVEFORM_DATA, (*tx_waveform)[j][i]); WRITE_REG 1475 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_EQ_RWB, BIT_RLPS_EQ_RWB); WRITE_REG 1477 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_EQ_ADDR, (unsigned char)ram_addr); WRITE_REG 1481 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_IND_DATA_1, rlps_ram_table[ram_addr].byte1); WRITE_REG 1483 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_IND_DATA_2, rlps_ram_table[ram_addr].byte2); WRITE_REG 1485 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_IND_DATA_3, rlps_ram_table[ram_addr].byte3); WRITE_REG 1487 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_IND_DATA_4, rlps_ram_table[ram_addr].byte4); WRITE_REG 1489 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_EQ_RWB, 0x00); WRITE_REG 1491 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_EQ_ADDR, (unsigned char)ram_addr); WRITE_REG 1560 dev/pci/if_san_te1.c WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND); WRITE_REG 1576 dev/pci/if_san_te1.c WRITE_REG(REG_TPSC_CHANNEL_INDIRECT_DATA_BUFFER, WRITE_REG 1578 dev/pci/if_san_te1.c WRITE_REG(REG_TPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL, WRITE_REG 1592 dev/pci/if_san_te1.c WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND | BIT_TPSC_PCCE); WRITE_REG 1613 dev/pci/if_san_te1.c WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND); WRITE_REG 1628 dev/pci/if_san_te1.c WRITE_REG(REG_TPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL, WRITE_REG 1642 dev/pci/if_san_te1.c WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND | BIT_TPSC_PCCE); WRITE_REG 1665 dev/pci/if_san_te1.c WRITE_REG(REG_RPSC_CFG, BIT_RPSC_IND); WRITE_REG 1681 dev/pci/if_san_te1.c WRITE_REG(REG_RPSC_CHANNEL_INDIRECT_DATA_BUFFER, (unsigned char)value); WRITE_REG 1682 dev/pci/if_san_te1.c WRITE_REG(REG_RPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL, WRITE_REG 1696 dev/pci/if_san_te1.c WRITE_REG(REG_RPSC_CFG, BIT_RPSC_IND | BIT_RPSC_PCCE); WRITE_REG 1715 dev/pci/if_san_te1.c WRITE_REG(REG_RPSC_CFG, BIT_RPSC_IND); WRITE_REG 1730 dev/pci/if_san_te1.c WRITE_REG(REG_RPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL, WRITE_REG 1744 dev/pci/if_san_te1.c WRITE_REG(REG_RPSC_CFG, BIT_RPSC_IND | BIT_RPSC_PCCE); WRITE_REG 2116 dev/pci/if_san_te1.c WRITE_REG(REG_RESET, BIT_RESET); WRITE_REG 2119 dev/pci/if_san_te1.c WRITE_REG(REG_RESET, 0x0/*~BIT_RESET*/); WRITE_REG 2129 dev/pci/if_san_te1.c WRITE_REG(REG_GLOBAL_CFG, WRITE_REG 2133 dev/pci/if_san_te1.c WRITE_REG(REG_GLOBAL_CFG, WRITE_REG 2138 dev/pci/if_san_te1.c WRITE_REG(REG_GLOBAL_CFG, WRITE_REG 2144 dev/pci/if_san_te1.c WRITE_REG(REG_XLPG_LINE_CFG, xlpg_scale); WRITE_REG 2148 dev/pci/if_san_te1.c WRITE_REG(REG_CSU_CFG, BIT_CSU_MODE0); WRITE_REG 2152 dev/pci/if_san_te1.c WRITE_REG(REG_CSU_CFG, 0x00); WRITE_REG 2157 dev/pci/if_san_te1.c WRITE_REG(REG_CDRC_CFG, BIT_CDRC_CFG_AMI); WRITE_REG 2159 dev/pci/if_san_te1.c WRITE_REG(REG_CDRC_CFG, 0x00); WRITE_REG 2165 dev/pci/if_san_te1.c WRITE_REG(REG_RX_ELST_CFG, BIT_RX_ELST_IR | BIT_RX_ELST_OR); WRITE_REG 2166 dev/pci/if_san_te1.c WRITE_REG(REG_TX_ELST_CFG, BIT_TX_ELST_IR | BIT_RX_ELST_OR); WRITE_REG 2168 dev/pci/if_san_te1.c WRITE_REG(REG_RX_ELST_CFG, 0x00); WRITE_REG 2169 dev/pci/if_san_te1.c WRITE_REG(REG_TX_ELST_CFG, 0x00); WRITE_REG 2185 dev/pci/if_san_te1.c WRITE_REG(REG_E1_TRAN_CFG, value); WRITE_REG 2196 dev/pci/if_san_te1.c WRITE_REG(REG_E1_FRMR_CFG, value); WRITE_REG 2208 dev/pci/if_san_te1.c WRITE_REG(REG_T1_XBAS_CFG, value); WRITE_REG 2215 dev/pci/if_san_te1.c WRITE_REG(REG_T1_FRMR_CFG, value); WRITE_REG 2223 dev/pci/if_san_te1.c WRITE_REG(REG_T1_ALMI_CFG, value); WRITE_REG 2228 dev/pci/if_san_te1.c WRITE_REG(REG_SIGX_CFG, 0x00); WRITE_REG 2234 dev/pci/if_san_te1.c WRITE_REG(REG_SIGX_CFG, value); WRITE_REG 2250 dev/pci/if_san_te1.c WRITE_REG(REG_BTIF_CFG, value); WRITE_REG 2257 dev/pci/if_san_te1.c WRITE_REG(REG_BTIF_FR_PULSE_CFG, value); WRITE_REG 2272 dev/pci/if_san_te1.c WRITE_REG(REG_BRIF_CFG, value); WRITE_REG 2279 dev/pci/if_san_te1.c WRITE_REG(REG_BRIF_FR_PULSE_CFG, value); WRITE_REG 2281 dev/pci/if_san_te1.c WRITE_REG(REG_BRIF_DATA_CFG, BIT_BRIF_DATA_TRI_0); WRITE_REG 2285 dev/pci/if_san_te1.c WRITE_REG(REG_TX_TIMING_OPT, BIT_TX_PLLREF1 | BIT_TX_TXELSTBYP); WRITE_REG 2287 dev/pci/if_san_te1.c WRITE_REG(REG_TX_TIMING_OPT, WRITE_REG 2292 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_CFG_STATUS, BIT_RLPS_CFG_STATUS_LONGE); WRITE_REG 2301 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_ALOS_DET_CLR_THR, WRITE_REG 2306 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_ALOS_DET_CLR_THR, WRITE_REG 2314 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_ALOS_DET_PER, REG_RLPS_ALOS_DET_PER_0); WRITE_REG 2316 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_ALOS_CLR_PER, BIT_RLPS_ALOS_CLR_PER_0); WRITE_REG 2325 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_EQ_STATUS, 0x00); WRITE_REG 2327 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_EQ_CFG, WRITE_REG 2331 dev/pci/if_san_te1.c WRITE_REG(REG_TJAT_CFG, BIT_TJAT_CENT); WRITE_REG 2334 dev/pci/if_san_te1.c WRITE_REG(REG_RJAT_CFG, BIT_RJAT_CENT); WRITE_REG 2337 dev/pci/if_san_te1.c WRITE_REG(REG_RECEIVE_OPT, BIT_RECEIVE_OPT_UNF); WRITE_REG 2339 dev/pci/if_san_te1.c WRITE_REG(REG_RECEIVE_OPT, 0x00); WRITE_REG 2343 dev/pci/if_san_te1.c WRITE_REG(REG_XLPG_TPC, BIT_XLPG_TPC_0); WRITE_REG 2345 dev/pci/if_san_te1.c WRITE_REG(REG_XLPG_TNC, BIT_XLPG_TNC_0); WRITE_REG 2349 dev/pci/if_san_te1.c WRITE_REG(REG_EQ_VREF, 0x34); WRITE_REG 2351 dev/pci/if_san_te1.c WRITE_REG(REG_EQ_VREF, 0x2C); WRITE_REG 2353 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_FUSE_CTRL_STAT, 0x00); WRITE_REG 2357 dev/pci/if_san_te1.c WRITE_REG(0xF4, 0x01); WRITE_REG 2358 dev/pci/if_san_te1.c WRITE_REG(0xF4, 0x01); WRITE_REG 2360 dev/pci/if_san_te1.c WRITE_REG(0xF4, value); WRITE_REG 2362 dev/pci/if_san_te1.c WRITE_REG(0xF5, 0x01); WRITE_REG 2363 dev/pci/if_san_te1.c WRITE_REG(0xF5, 0x01); WRITE_REG 2365 dev/pci/if_san_te1.c WRITE_REG(0xF5, value); WRITE_REG 2367 dev/pci/if_san_te1.c WRITE_REG(0xF6, 0x01); WRITE_REG 2416 dev/pci/if_san_te1.c WRITE_REG(REG_RLPS_CFG_STATUS, WRITE_REG 2420 dev/pci/if_san_te1.c WRITE_REG(REG_T1_RBOC_ENABLE, WRITE_REG 2424 dev/pci/if_san_te1.c WRITE_REG(REG_T1_ALMI_INT_EN, WRITE_REG 2432 dev/pci/if_san_te1.c WRITE_REG(REG_E1_FRMR_M_A_INT_EN, WRITE_REG 2444 dev/pci/if_san_te1.c WRITE_REG(REG_SIGX_CFG, WRITE_REG 2446 dev/pci/if_san_te1.c WRITE_REG(REG_SIGX_CFG, WRITE_REG 2526 dev/pci/if_san_te1.c WRITE_REG(REG_CDRC_INT_EN, WRITE_REG 2529 dev/pci/if_san_te1.c WRITE_REG(REG_CDRC_INT_EN, WRITE_REG 2686 dev/pci/if_san_te1.c WRITE_REG(REG_PMON_BIT_ERROR, 0x00); WRITE_REG 2731 dev/pci/if_san_te1.c WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND); WRITE_REG 2749 dev/pci/if_san_te1.c WRITE_REG(REG_TPSC_CFG, WRITE_REG 3046 dev/pci/if_san_te1.c WRITE_REG(REG_MASTER_DIAG,reg); WRITE_REG 3053 dev/pci/if_san_te1.c WRITE_REG(REG_MASTER_DIAG,reg); WRITE_REG 3570 dev/pci/if_san_te1.c WRITE_REG(REG_MASTER_DIAG, WRITE_REG 3576 dev/pci/if_san_te1.c WRITE_REG(REG_MASTER_DIAG, WRITE_REG 3593 dev/pci/if_san_te1.c WRITE_REG(REG_MASTER_DIAG, WRITE_REG 3598 dev/pci/if_san_te1.c WRITE_REG(REG_MASTER_DIAG, WRITE_REG 3615 dev/pci/if_san_te1.c WRITE_REG(REG_MASTER_DIAG, WRITE_REG 3620 dev/pci/if_san_te1.c WRITE_REG(REG_MASTER_DIAG, WRITE_REG 3681 dev/pci/if_san_te1.c WRITE_REG(REG_T1_XBOC_CODE, WRITE_REG 3687 dev/pci/if_san_te1.c WRITE_REG(REG_T1_XBOC_CODE, WRITE_REG 3866 dev/pci/if_san_te1.c WRITE_REG(REG_GLOBAL_CFG,led); WRITE_REG 307 dev/pci/if_txp.c WRITE_REG(sc, TXP_IER, 0); WRITE_REG 308 dev/pci/if_txp.c WRITE_REG(sc, TXP_IMR, WRITE_REG 314 dev/pci/if_txp.c WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | WRITE_REG 324 dev/pci/if_txp.c WRITE_REG(sc, TXP_IER, 0); WRITE_REG 325 dev/pci/if_txp.c WRITE_REG(sc, TXP_IMR, WRITE_REG 331 dev/pci/if_txp.c WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | WRITE_REG 347 dev/pci/if_txp.c WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); WRITE_REG 349 dev/pci/if_txp.c WRITE_REG(sc, TXP_SRR, 0); WRITE_REG 379 dev/pci/if_txp.c WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); WRITE_REG 382 dev/pci/if_txp.c WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); WRITE_REG 396 dev/pci/if_txp.c WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); WRITE_REG 412 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_1, letoh32(fileheader->addr)); WRITE_REG 413 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); WRITE_REG 431 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); WRITE_REG 444 dev/pci/if_txp.c WRITE_REG(sc, TXP_IER, ier); WRITE_REG 445 dev/pci/if_txp.c WRITE_REG(sc, TXP_IMR, imr); WRITE_REG 473 dev/pci/if_txp.c WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); WRITE_REG 542 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_1, letoh32(sect->nbytes)); WRITE_REG 543 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_2, letoh16(sect->cksum)); WRITE_REG 544 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_3, letoh32(sect->addr)); WRITE_REG 545 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); WRITE_REG 546 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); WRITE_REG 547 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); WRITE_REG 574 dev/pci/if_txp.c WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | WRITE_REG 586 dev/pci/if_txp.c WRITE_REG(sc, TXP_ISR, isr); WRITE_REG 611 dev/pci/if_txp.c WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); WRITE_REG 908 dev/pci/if_txp.c WRITE_REG(sc, TXP_IMR, WRITE_REG 1131 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); WRITE_REG 1132 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); WRITE_REG 1133 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); WRITE_REG 1148 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); WRITE_REG 1149 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); WRITE_REG 1150 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); WRITE_REG 1151 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); WRITE_REG 1319 dev/pci/if_txp.c WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | WRITE_REG 1324 dev/pci/if_txp.c WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); WRITE_REG 1545 dev/pci/if_txp.c WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); WRITE_REG 1638 dev/pci/if_txp.c WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); WRITE_REG 303 dev/pci/ises.c WRITE_REG(sc, ISES_BO_STAT, stat); WRITE_REG 311 dev/pci/ises.c WRITE_REG(sc, ISES_BO_STAT, stat); WRITE_REG 328 dev/pci/ises.c WRITE_REG(sc, ISES_B_BDATAOUT, 0L); WRITE_REG 331 dev/pci/ises.c WRITE_REG(sc, ISES_BO_STAT, stat); WRITE_REG 333 dev/pci/ises.c WRITE_REG(sc, ISES_BO_STAT, stat); WRITE_REG 341 dev/pci/ises.c WRITE_REG(sc, ISES_BO_STAT, stat); WRITE_REG 370 dev/pci/ises.c WRITE_REG(sc, ISES_BO_STAT, stat); WRITE_REG 378 dev/pci/ises.c WRITE_REG(sc, ISES_BO_STAT, stat); WRITE_REG 386 dev/pci/ises.c WRITE_REG(sc, ISES_BO_STAT, stat); WRITE_REG 411 dev/pci/ises.c WRITE_REG(sc, ISES_A_IQD, ISES_BF_IDPLEN); WRITE_REG 415 dev/pci/ises.c WRITE_REG(sc, ISES_A_IQD, ises_bf_fw[p]); WRITE_REG 421 dev/pci/ises.c WRITE_REG(sc, ISES_A_IQD, ISES_BF_IDPCRC); WRITE_REG 484 dev/pci/ises.c WRITE_REG(sc, ISES_A_INTE, sc->sc_intrmask); WRITE_REG 556 dev/pci/ises.c WRITE_REG(sc, ISES_A_IQD, cmd); WRITE_REG 562 dev/pci/ises.c WRITE_REG(sc, ISES_A_IQD, *(data + p)); WRITE_REG 565 dev/pci/ises.c WRITE_REG(sc, ISES_A_IQD, *(data + p)); WRITE_REG 568 dev/pci/ises.c WRITE_REG(sc, ISES_A_IQS, 0); WRITE_REG 718 dev/pci/ises.c WRITE_REG(sc, ISES_A_OQS, 0); WRITE_REG 743 dev/pci/ises.c WRITE_REG(sc, ISES_DMA_RESET, 0); WRITE_REG 752 dev/pci/ises.c WRITE_REG(sc, ISES_DMA_RESET, 0); WRITE_REG 757 dev/pci/ises.c WRITE_REG(sc, ISES_DMA_RESET, 0); WRITE_REG 767 dev/pci/ises.c WRITE_REG(sc, ISES_A_INTS, ints); WRITE_REG 897 dev/pci/ises.c WRITE_REG(sc, ISES_DMA_WRITE_START, ds->ds_addr); WRITE_REG 898 dev/pci/ises.c WRITE_REG(sc, ISES_DMA_WRITE_COUNT, ISES_DMA_WCOUNT(ds->ds_len)); WRITE_REG 902 dev/pci/ises.c WRITE_REG(sc, ISES_DMA_CTRL, dma_status); WRITE_REG 1540 dev/pci/ises.c WRITE_REG(sc, ISES_A_OQS, 0); WRITE_REG 1569 dev/pci/ises.c WRITE_REG(sc, ISES_A_OQS, 0); /* ACK resp */ WRITE_REG 1616 dev/pci/ises.c WRITE_REG(sc, ISES_A_IQD, r); WRITE_REG 1617 dev/pci/ises.c WRITE_REG(sc, ISES_A_IQS, 0); WRITE_REG 1641 dev/pci/ises.c WRITE_REG(sc, ISES_A_OQS, 0); /* Ack the response */ WRITE_REG 1754 dev/pci/ises.c WRITE_REG(sc, ISES_DMA_READ_START, ds->ds_addr); WRITE_REG 1755 dev/pci/ises.c WRITE_REG(sc, ISES_DMA_READ_START, ISES_DMA_RCOUNT(ds->ds_len)); WRITE_REG 1759 dev/pci/ises.c WRITE_REG(sc, ISES_DMA_CTRL, dma_status); WRITE_REG 1887 dev/pci/ises.c WRITE_REG(sc, ISES_BO_STAT, stat); WRITE_REG 1889 dev/pci/ises.c WRITE_REG(sc, ISES_BO_STAT, stat); WRITE_REG 140 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_IER, sc->sc_ier); WRITE_REG 364 dev/pci/lofn.c WRITE_REG(sc, LOFN_LENADDR(LOFN_WIN_2, 2), 1024); WRITE_REG 366 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_INSTR + ip, WRITE_REG 370 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_INSTR + ip, WRITE_REG 388 dev/pci/lofn.c WRITE_REG(sc, LOFN_LENADDR(LOFN_WIN_2, 0), 1024); WRITE_REG 390 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_INSTR + ip, WRITE_REG 394 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_INSTR + ip, WRITE_REG 416 dev/pci/lofn.c WRITE_REG(sc, LOFN_LENADDR(LOFN_WIN_2, 1), 1024); WRITE_REG 418 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_INSTR + ip, WRITE_REG 422 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_INSTR + ip, WRITE_REG 428 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_INSTR + ip, WRITE_REG 432 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_INSTR + ip, WRITE_REG 436 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_INSTR + ip, WRITE_REG 440 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_INSTR + ip, WRITE_REG 446 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_CR, 0); WRITE_REG 526 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_IER, sc->sc_ier); WRITE_REG 540 dev/pci/lofn.c WRITE_REG(sc, LOFN_REL_IER, sc->sc_ier); WRITE_REG 66 dev/pci/lofnvar.h #define WRITE_REG_0(sc,r,v) WRITE_REG((sc), (r) | LOFN_WIN_0, (v)) WRITE_REG 67 dev/pci/lofnvar.h #define WRITE_REG_1(sc,r,v) WRITE_REG((sc), (r) | LOFN_WIN_1, (v)) WRITE_REG 68 dev/pci/lofnvar.h #define WRITE_REG_2(sc,r,v) WRITE_REG((sc), (r) | LOFN_WIN_2, (v)) WRITE_REG 69 dev/pci/lofnvar.h #define WRITE_REG_3(sc,r,v) WRITE_REG((sc), (r) | LOFN_WIN_3, (v)) WRITE_REG 994 dev/pci/safe.c WRITE_REG(sc, SAFE_PE_DMACFG, v WRITE_REG 998 dev/pci/safe.c WRITE_REG(sc, SAFE_PE_DMACFG, v); WRITE_REG 1018 dev/pci/safe.c WRITE_REG(sc, SAFE_PE_DMACFG, v); WRITE_REG 1020 dev/pci/safe.c WRITE_REG(sc, SAFE_CRYPTO_CTRL, SAFE_CRYPTO_CTRL_PKEY | WRITE_REG 1024 dev/pci/safe.c WRITE_REG(sc, SAFE_ENDIAN, SAFE_ENDIAN_TGT_PASS|SAFE_ENDIAN_DMA_PASS); WRITE_REG 1026 dev/pci/safe.c WRITE_REG(sc, SAFE_ENDIAN, SAFE_ENDIAN_TGT_PASS|SAFE_ENDIAN_DMA_SWAB); WRITE_REG 1037 dev/pci/safe.c WRITE_REG(sc, SAFE_DMA_CFG, 256); WRITE_REG 1046 dev/pci/safe.c WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); WRITE_REG 1047 dev/pci/safe.c WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); WRITE_REG 1054 dev/pci/safe.c WRITE_REG(sc, SAFE_PE_RINGCFG, WRITE_REG 1056 dev/pci/safe.c WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ WRITE_REG 1058 dev/pci/safe.c WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); WRITE_REG 1059 dev/pci/safe.c WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); WRITE_REG 1060 dev/pci/safe.c WRITE_REG(sc, SAFE_PE_PARTSIZE, WRITE_REG 1067 dev/pci/safe.c WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE); WRITE_REG 1069 dev/pci/safe.c WRITE_REG(sc, SAFE_HI_CLR, SAFE_INT_PE_CDONE | SAFE_INT_PE_DDONE | WRITE_REG 1073 dev/pci/safe.c WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); WRITE_REG 1080 dev/pci/safe.c WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); WRITE_REG 1082 dev/pci/safe.c WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); WRITE_REG 1084 dev/pci/safe.c WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); WRITE_REG 1151 dev/pci/safe.c WRITE_REG(sc, SAFE_RNG_CTRL, 0); WRITE_REG 1153 dev/pci/safe.c WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ WRITE_REG 1154 dev/pci/safe.c WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); WRITE_REG 1230 dev/pci/safe.c WRITE_REG(sc, SAFE_RNG_CTRL, WRITE_REG 1237 dev/pci/safe.c WRITE_REG(sc, SAFE_RNG_CNFG, w); WRITE_REG 1239 dev/pci/safe.c WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); WRITE_REG 1245 dev/pci/safe.c WRITE_REG(sc, SAFE_RNG_CTRL, WRITE_REG 1252 dev/pci/safe.c WRITE_REG(sc, SAFE_RNG_CTRL, WRITE_REG 1255 dev/pci/safe.c WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); WRITE_REG 1550 dev/pci/safe.c WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); WRITE_REG 1743 dev/pci/safe.c WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ WRITE_REG 1894 dev/pci/safe.c WRITE_REG(sc, SAFE_PK_A_LEN, (exp_bits + 31) / 32); WRITE_REG 1895 dev/pci/safe.c WRITE_REG(sc, SAFE_PK_B_LEN, (mod_bits + 31) / 32); WRITE_REG 1915 dev/pci/safe.c WRITE_REG(sc, SAFE_PK_A_ADDR, a_off >> 2); WRITE_REG 1918 dev/pci/safe.c WRITE_REG(sc, SAFE_PK_B_ADDR, b_off >> 2); WRITE_REG 1921 dev/pci/safe.c WRITE_REG(sc, SAFE_PK_C_ADDR, c_off >> 2); WRITE_REG 1922 dev/pci/safe.c WRITE_REG(sc, SAFE_PK_D_ADDR, d_off >> 2); WRITE_REG 1924 dev/pci/safe.c WRITE_REG(sc, SAFE_PK_FUNC, op | SAFE_PK_FUNC_RUN); WRITE_REG 2014 dev/pci/safe.c WRITE_REG(sc, i, 0); WRITE_REG 2035 dev/pci/safe.c WRITE_REG(sc, SAFE_PK_RAM_START + off + (i << 2), WRITE_REG 345 dev/pci/ubsec.c WRITE_REG(sc, BS_STAT, stat); /* IACK */ WRITE_REG 506 dev/pci/ubsec.c WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + WRITE_REG 532 dev/pci/ubsec.c WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + WRITE_REG 1338 dev/pci/ubsec.c WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); WRITE_REG 1566 dev/pci/ubsec.c WRITE_REG(sc, BS_CTRL, ctrl); WRITE_REG 1594 dev/pci/ubsec.c WRITE_REG(sc, BS_CTRL, ctrl);