READ_REG 76 dev/pci/if_san_te1.c unsigned char test_value = READ_REG(reg); \
READ_REG 1563 dev/pci/if_san_te1.c temp = READ_REG(REG_TPSC_MICRO_ACCESS_STATUS);
READ_REG 1582 dev/pci/if_san_te1.c temp = READ_REG(REG_TPSC_MICRO_ACCESS_STATUS);
READ_REG 1616 dev/pci/if_san_te1.c tmp = READ_REG(REG_TPSC_MICRO_ACCESS_STATUS);
READ_REG 1632 dev/pci/if_san_te1.c tmp = READ_REG(REG_TPSC_MICRO_ACCESS_STATUS);
READ_REG 1634 dev/pci/if_san_te1.c value = READ_REG(REG_TPSC_CHANNEL_INDIRECT_DATA_BUFFER);
READ_REG 1668 dev/pci/if_san_te1.c temp = READ_REG(REG_RPSC_MICRO_ACCESS_STATUS);
READ_REG 1686 dev/pci/if_san_te1.c temp = READ_REG(REG_RPSC_MICRO_ACCESS_STATUS);
READ_REG 1718 dev/pci/if_san_te1.c tmp = READ_REG(REG_RPSC_MICRO_ACCESS_STATUS);
READ_REG 1734 dev/pci/if_san_te1.c tmp = READ_REG(REG_RPSC_MICRO_ACCESS_STATUS);
READ_REG 1736 dev/pci/if_san_te1.c value = READ_REG(REG_RPSC_CHANNEL_INDIRECT_DATA_BUFFER);
READ_REG 2230 dev/pci/if_san_te1.c value = READ_REG(REG_SIGX_CFG);
READ_REG 2359 dev/pci/if_san_te1.c value = READ_REG(0xF4) & 0xFE;
READ_REG 2364 dev/pci/if_san_te1.c value = READ_REG(0xF5) & 0xFE;
READ_REG 2417 dev/pci/if_san_te1.c READ_REG(REG_RLPS_CFG_STATUS) | BIT_RLPS_CFG_STATUS_ALOSE);
READ_REG 2445 dev/pci/if_san_te1.c READ_REG(REG_SIGX_CFG) | BIT_SIGX_SIGE);
READ_REG 2447 dev/pci/if_san_te1.c READ_REG(REG_SIGX_CFG) | BIT_SIGX_COSS);
READ_REG 2527 dev/pci/if_san_te1.c (READ_REG(REG_CDRC_INT_EN) | BIT_CDRC_INT_EN_LOSE));
READ_REG 2530 dev/pci/if_san_te1.c (READ_REG(REG_CDRC_INT_EN) & ~BIT_CDRC_INT_EN_LOSE));
READ_REG 2566 dev/pci/if_san_te1.c if (READ_REG(REG_RLPS_ALOS_DET_PER) &&
READ_REG 2567 dev/pci/if_san_te1.c (READ_REG(REG_RLPS_CFG_STATUS) & BIT_RLPS_CFG_STATUS_ALOSV)) {
READ_REG 2575 dev/pci/if_san_te1.c if ((READ_REG(REG_CDRC_CFG) & (BIT_CDRC_CFG_LOS0|BIT_CDRC_CFG_LOS1)) &&
READ_REG 2576 dev/pci/if_san_te1.c (READ_REG(REG_CDRC_INT_STATUS) & BIT_CDRC_INT_STATUS_LOSV)) {
READ_REG 2583 dev/pci/if_san_te1.c if (READ_REG(REG_ALTLOS_STATUS) & BIT_ALTLOS_STATUS_ALTLOS) {
READ_REG 2590 dev/pci/if_san_te1.c if (READ_REG(REG_E1_FRMR_FR_STATUS) &
READ_REG 2595 dev/pci/if_san_te1.c if (READ_REG(REG_E1_FRMR_FR_STATUS) &
READ_REG 2600 dev/pci/if_san_te1.c if (READ_REG(REG_E1_FRMR_FR_STATUS) &
READ_REG 2605 dev/pci/if_san_te1.c if (READ_REG(REG_E1_FRMR_FR_STATUS) &
READ_REG 2610 dev/pci/if_san_te1.c if (READ_REG(REG_E1_FRMR_MAINT_STATUS) &
READ_REG 2617 dev/pci/if_san_te1.c if (READ_REG(REG_E1_FRMR_MAINT_STATUS) &
READ_REG 2625 dev/pci/if_san_te1.c if ((READ_REG(REG_E1_FRMR_MAINT_OPT) &
READ_REG 2627 dev/pci/if_san_te1.c (READ_REG(REG_E1_FRMR_MAINT_STATUS) &
READ_REG 2635 dev/pci/if_san_te1.c if (!(READ_REG(REG_T1_FRMR_INT_STATUS) &
READ_REG 2643 dev/pci/if_san_te1.c if ((READ_REG(REG_T1_ALMI_INT_STATUS) &
READ_REG 2645 dev/pci/if_san_te1.c (READ_REG(REG_T1_ALMI_DET_STATUS) &
READ_REG 2652 dev/pci/if_san_te1.c if (READ_REG(REG_T1_ALMI_DET_STATUS) &
READ_REG 2660 dev/pci/if_san_te1.c if ((READ_REG(REG_T1_ALMI_INT_STATUS) &
READ_REG 2662 dev/pci/if_san_te1.c (READ_REG(REG_T1_ALMI_DET_STATUS) &
READ_REG 2689 dev/pci/if_san_te1.c READ_REG(REG_PMON_BIT_ERROR) & BITS_PMON_BIT_ERROR;
READ_REG 2693 dev/pci/if_san_te1.c ((READ_REG(REG_PMON_OOF_FEB_MSB_ERROR) &
READ_REG 2695 dev/pci/if_san_te1.c READ_REG(REG_PMON_OOF_FEB_LSB_ERROR);
READ_REG 2699 dev/pci/if_san_te1.c ((READ_REG(REG_PMON_BIT_CRC_MSB_ERROR) &
READ_REG 2701 dev/pci/if_san_te1.c READ_REG(REG_PMON_BIT_CRC_LSB_ERROR);
READ_REG 2704 dev/pci/if_san_te1.c pmon->lcv += ((READ_REG(REG_PMON_LCV_MSB_COUNT) &
READ_REG 2705 dev/pci/if_san_te1.c BITS_PMON_LCV_MSB_COUNT) << 8) | READ_REG(REG_PMON_LCV_LSB_COUNT);
READ_REG 2750 dev/pci/if_san_te1.c ((READ_REG(REG_TPSC_CFG) & MASK_TPSC_CFG) | BIT_TPSC_PCCE));
READ_REG 2783 dev/pci/if_san_te1.c intr_src1 = READ_REG(REG_INT_SRC_1);
READ_REG 2784 dev/pci/if_san_te1.c intr_src2 = READ_REG(REG_INT_SRC_2);
READ_REG 2785 dev/pci/if_san_te1.c intr_src3 = READ_REG(REG_INT_SRC_3);
READ_REG 2851 dev/pci/if_san_te1.c intr_src1 = READ_REG(REG_INT_SRC_1);
READ_REG 2852 dev/pci/if_san_te1.c intr_src2 = READ_REG(REG_INT_SRC_2);
READ_REG 2853 dev/pci/if_san_te1.c intr_src3 = READ_REG(REG_INT_SRC_3);
READ_REG 2863 dev/pci/if_san_te1.c status = READ_REG(REG_PDVD_INT_EN_STATUS);
READ_REG 2880 dev/pci/if_san_te1.c status = READ_REG(REG_T1_ALMI_INT_STATUS);
READ_REG 2982 dev/pci/if_san_te1.c status = READ_REG(REG_T1_RBOC_CODE_STATUS);
READ_REG 3044 dev/pci/if_san_te1.c reg=READ_REG(REG_MASTER_DIAG);
READ_REG 3051 dev/pci/if_san_te1.c reg=READ_REG(REG_MASTER_DIAG);
READ_REG 3127 dev/pci/if_san_te1.c status = READ_REG(REG_T1_FRMR_INT_STATUS);
READ_REG 3128 dev/pci/if_san_te1.c if ((READ_REG(REG_T1_FRMR_INT_EN) & BIT_T1_FRMR_INT_EN_INFRE) &&
READ_REG 3148 dev/pci/if_san_te1.c status = READ_REG(REG_RLPS_CFG_STATUS);
READ_REG 3169 dev/pci/if_san_te1.c status = READ_REG(REG_CDRC_INT_STATUS);
READ_REG 3170 dev/pci/if_san_te1.c if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LOSE) &&
READ_REG 3186 dev/pci/if_san_te1.c if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LCVE) &&
READ_REG 3191 dev/pci/if_san_te1.c if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LCSDE) &&
READ_REG 3196 dev/pci/if_san_te1.c if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_ZNDE) &&
READ_REG 3201 dev/pci/if_san_te1.c status = READ_REG(REG_ALTLOS_STATUS);
READ_REG 3225 dev/pci/if_san_te1.c status = READ_REG(REG_PMON_INT_EN_STATUS);
READ_REG 3240 dev/pci/if_san_te1.c SIGX_chg_30_25 = READ_REG(REG_SIGX_CFG);
READ_REG 3241 dev/pci/if_san_te1.c SIGX_chg_24_17= READ_REG(REG_SIGX_TIMESLOT_IND_STATUS);
READ_REG 3242 dev/pci/if_san_te1.c SIGX_chg_16_9 = READ_REG(REG_SIGX_TIMESLOT_IND_ACCESS);
READ_REG 3243 dev/pci/if_san_te1.c SIGX_chg_8_1 = READ_REG(REG_SIGX_TIMESLOT_IND_DATA_BUFFER);
READ_REG 3250 dev/pci/if_san_te1.c status = READ_REG(REG_IBCD_INT_EN_STATUS);
READ_REG 3292 dev/pci/if_san_te1.c intr_src1 = READ_REG(REG_INT_SRC_1);
READ_REG 3293 dev/pci/if_san_te1.c intr_src2 = READ_REG(REG_INT_SRC_2);
READ_REG 3294 dev/pci/if_san_te1.c intr_src3 = READ_REG(REG_INT_SRC_3);
READ_REG 3303 dev/pci/if_san_te1.c int_status = READ_REG(REG_E1_FRMR_FRM_STAT_INT_IND);
READ_REG 3305 dev/pci/if_san_te1.c status = READ_REG(REG_E1_FRMR_FR_STATUS);
READ_REG 3306 dev/pci/if_san_te1.c if ((READ_REG(REG_E1_FRMR_FRM_STAT_INT_EN) &
READ_REG 3324 dev/pci/if_san_te1.c if ((READ_REG(REG_E1_FRMR_FRM_STAT_INT_EN) &
READ_REG 3338 dev/pci/if_san_te1.c if ((READ_REG(REG_E1_FRMR_FRM_STAT_INT_EN) &
READ_REG 3353 dev/pci/if_san_te1.c status = READ_REG(REG_E1_FRMR_P_A_INT_STAT);
READ_REG 3354 dev/pci/if_san_te1.c if ((READ_REG(REG_E1_FRMR_P_A_INT_EN) &
READ_REG 3357 dev/pci/if_san_te1.c if (READ_REG(REG_E1_FRMR_FR_STATUS) &
READ_REG 3370 dev/pci/if_san_te1.c int_status = READ_REG(REG_E1_FRMR_M_A_INT_IND);
READ_REG 3373 dev/pci/if_san_te1.c status = READ_REG(REG_E1_FRMR_MAINT_STATUS);
READ_REG 3374 dev/pci/if_san_te1.c if ((READ_REG(REG_E1_FRMR_M_A_INT_EN) &
READ_REG 3387 dev/pci/if_san_te1.c if ((READ_REG(REG_E1_FRMR_M_A_INT_EN) &
READ_REG 3400 dev/pci/if_san_te1.c if ((READ_REG(REG_E1_FRMR_M_A_INT_EN) &
READ_REG 3418 dev/pci/if_san_te1.c status = READ_REG(REG_RLPS_CFG_STATUS);
READ_REG 3440 dev/pci/if_san_te1.c status = READ_REG(REG_CDRC_INT_STATUS);
READ_REG 3441 dev/pci/if_san_te1.c if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LOSE) &&
READ_REG 3457 dev/pci/if_san_te1.c if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LCVE) &&
READ_REG 3462 dev/pci/if_san_te1.c if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LCSDE) &&
READ_REG 3467 dev/pci/if_san_te1.c if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_ZNDE) &&
READ_REG 3472 dev/pci/if_san_te1.c status = READ_REG(REG_ALTLOS_STATUS);
READ_REG 3495 dev/pci/if_san_te1.c status = READ_REG(REG_PMON_INT_EN_STATUS);
READ_REG 3523 dev/pci/if_san_te1.c if (!(READ_REG(REG_RLPS_CFG_STATUS) & BIT_RLPS_CFG_STATUS_ALOSV)) {
READ_REG 3571 dev/pci/if_san_te1.c READ_REG(REG_MASTER_DIAG) | BIT_MASTER_DIAG_LINELB);
READ_REG 3577 dev/pci/if_san_te1.c READ_REG(REG_MASTER_DIAG) & ~BIT_MASTER_DIAG_LINELB);
READ_REG 3594 dev/pci/if_san_te1.c READ_REG(REG_MASTER_DIAG) | BIT_MASTER_DIAG_PAYLB);
READ_REG 3599 dev/pci/if_san_te1.c READ_REG(REG_MASTER_DIAG) & ~BIT_MASTER_DIAG_PAYLB);
READ_REG 3616 dev/pci/if_san_te1.c READ_REG(REG_MASTER_DIAG) | BIT_MASTER_DIAG_DDLB);
READ_REG 3621 dev/pci/if_san_te1.c READ_REG(REG_MASTER_DIAG) & ~BIT_MASTER_DIAG_DDLB);
READ_REG 3710 dev/pci/if_san_te1.c if ((READ_REG(REG_RLPS_ALOS_DET_PER) &&
READ_REG 3711 dev/pci/if_san_te1.c (READ_REG(REG_RLPS_CFG_STATUS) &
READ_REG 3714 dev/pci/if_san_te1.c (READ_REG(REG_E1_FRMR_FR_STATUS) &
READ_REG 3717 dev/pci/if_san_te1.c (READ_REG(REG_T1_FRMR_INT_STATUS) &
READ_REG 3852 dev/pci/if_san_te1.c led= READ_REG(REG_GLOBAL_CFG);
READ_REG 353 dev/pci/if_txp.c r = READ_REG(sc, TXP_A2H_0);
READ_REG 378 dev/pci/if_txp.c ier = READ_REG(sc, TXP_IER);
READ_REG 381 dev/pci/if_txp.c imr = READ_REG(sc, TXP_IMR);
READ_REG 385 dev/pci/if_txp.c r = READ_REG(sc, TXP_A2H_0);
READ_REG 434 dev/pci/if_txp.c r = READ_REG(sc, TXP_A2H_0);
READ_REG 462 dev/pci/if_txp.c r = READ_REG(sc, TXP_ISR);
READ_REG 475 dev/pci/if_txp.c r = READ_REG(sc, TXP_A2H_0);
READ_REG 583 dev/pci/if_txp.c isr = READ_REG(sc, TXP_ISR);
READ_REG 604 dev/pci/if_txp.c isr = READ_REG(sc, TXP_ISR);
READ_REG 1122 dev/pci/if_txp.c r = READ_REG(sc, TXP_A2H_0);
READ_REG 1137 dev/pci/if_txp.c r = READ_REG(sc, TXP_A2H_0);
READ_REG 287 dev/pci/ises.c p = ISES_STAT_IDP_STATE(READ_REG(sc, ISES_A_STAT));
READ_REG 300 dev/pci/ises.c stat = READ_REG(sc, ISES_BO_STAT);
READ_REG 339 dev/pci/ises.c stat = READ_REG(sc, ISES_BO_STAT);
READ_REG 344 dev/pci/ises.c if (READ_REG(sc, ISES_A_STAT) & ISES_STAT_HW_DA) {
READ_REG 355 dev/pci/ises.c p = ISES_STAT_IDP_STATE(READ_REG(sc, ISES_A_STAT));
READ_REG 368 dev/pci/ises.c stat = READ_REG(sc, ISES_BO_STAT);
READ_REG 376 dev/pci/ises.c stat = READ_REG(sc, ISES_BO_STAT);
READ_REG 384 dev/pci/ises.c stat = READ_REG(sc, ISES_BO_STAT);
READ_REG 396 dev/pci/ises.c p = ISES_STAT_IDP_STATE(READ_REG(sc, ISES_A_STAT));
READ_REG 397 dev/pci/ises.c if (READ_REG(sc, ISES_A_IQF) < 4 || p != ISES_IDP_WFPL) {
READ_REG 416 dev/pci/ises.c if (READ_REG(sc, ISES_A_IQF) < 4)
READ_REG 428 dev/pci/ises.c if (READ_REG(sc, ISES_A_STAT) & ISES_STAT_HW_DA) {
READ_REG 465 dev/pci/ises.c stat = READ_REG(sc, ISES_A_STAT);
READ_REG 538 dev/pci/ises.c if (len > READ_REG(sc, ISES_A_IQF)) {
READ_REG 586 dev/pci/ises.c r = READ_REG(sc, ISES_A_OQS);
READ_REG 591 dev/pci/ises.c while ((oqs = READ_REG(sc, ISES_A_OQS)) > 0) {
READ_REG 593 dev/pci/ises.c r = READ_REG(sc, ISES_A_OQD);
READ_REG 641 dev/pci/ises.c d = READ_REG(sc, ISES_A_OQD);
READ_REG 655 dev/pci/ises.c READ_REG(sc, ISES_A_OQD);
READ_REG 668 dev/pci/ises.c READ_REG(sc, ISES_A_OQD);
READ_REG 674 dev/pci/ises.c ses->omr = READ_REG(sc, ISES_A_OQD);
READ_REG 691 dev/pci/ises.c READ_REG(sc, ISES_A_OQD);
READ_REG 717 dev/pci/ises.c d = READ_REG(sc, ISES_A_OQD);
READ_REG 731 dev/pci/ises.c dma_status = READ_REG(sc, ISES_DMA_STATUS);
READ_REG 760 dev/pci/ises.c ints = READ_REG(sc, ISES_A_INTS);
READ_REG 771 dev/pci/ises.c if (READ_REG(sc, ISES_A_STAT) &
READ_REG 845 dev/pci/ises.c (READ_REG(sc, ISES_A_STAT) & ISES_STAT_BCHU_IFF)) {
READ_REG 900 dev/pci/ises.c dma_status = READ_REG(sc, ISES_DMA_STATUS);
READ_REG 1529 dev/pci/ises.c for (i = 1000; i && READ_REG(sc, ISES_A_OQS) == 0; i--)
READ_REG 1532 dev/pci/ises.c if (!READ_REG(sc, ISES_A_OQS))
READ_REG 1537 dev/pci/ises.c (void)READ_REG(sc, ISES_A_OQD);
READ_REG 1564 dev/pci/ises.c while (READ_REG(sc, ISES_A_OQS) == 0) ; /* Wait for response */
READ_REG 1566 dev/pci/ises.c (void)READ_REG(sc, ISES_A_OQD); /* read response */
READ_REG 1568 dev/pci/ises.c (void)READ_REG(sc, ISES_A_OQD); /* read data */
READ_REG 1619 dev/pci/ises.c for (i = 100; i > 0 && READ_REG(sc, ISES_A_OQS) == 0; i--)
READ_REG 1625 dev/pci/ises.c r = READ_REG(sc, ISES_A_OQD);
READ_REG 1632 dev/pci/ises.c (void)READ_REG(sc, ISES_A_OQD);
READ_REG 1637 dev/pci/ises.c r = READ_REG(sc, ISES_A_OQD); /* read version */
READ_REG 1638 dev/pci/ises.c (void)READ_REG(sc, ISES_A_OQD); /* Discard 64bit "chip-id" */
READ_REG 1639 dev/pci/ises.c (void)READ_REG(sc, ISES_A_OQD);
READ_REG 1655 dev/pci/ises.c switch (ISES_STAT_SW_MODE(READ_REG(sc, ISES_A_STAT))) {
READ_REG 1658 dev/pci/ises.c if (ISES_STAT_SW_MODE(READ_REG(sc, ISES_A_STAT)) == 0)
READ_REG 1667 dev/pci/ises.c return ((ISES_STAT_SW_MODE(READ_REG(sc, ISES_A_STAT)) == 0) ?
READ_REG 1673 dev/pci/ises.c return ((ISES_STAT_SW_MODE(READ_REG(sc, ISES_A_STAT)) == 0) ?
READ_REG 1690 dev/pci/ises.c if ((8 * 2 + sizeof (*ss) / 2) > READ_REG(sc, ISES_A_IQF))
READ_REG 1757 dev/pci/ises.c dma_status = READ_REG(sc, ISES_DMA_STATUS);
READ_REG 1808 dev/pci/ises.c stat = READ_REG(sc, ISES_A_OQS);
READ_REG 1809 dev/pci/ises.c cmd = READ_REG(sc, ISES_A_IQS);
READ_REG 1812 dev/pci/ises.c cmd, stat, READ_REG(sc, ISES_A_IQF),
READ_REG 1813 dev/pci/ises.c READ_REG(sc, ISES_A_OQF));
READ_REG 1913 dev/pci/ises.c stat = READ_REG(sc, ISES_BO_STAT);
READ_REG 1932 dev/pci/ises.c stat = READ_REG(sc, ISES_A_STAT);
READ_REG 2000 dev/pci/ises.c READ_REG(sc, ISES_A_OQS), READ_REG(sc, ISES_A_IQS),
READ_REG 2001 dev/pci/ises.c READ_REG(sc, ISES_A_OQF), READ_REG(sc, ISES_A_IQF));
READ_REG 2006 dev/pci/ises.c READ_REG(sc, ISES_B_STAT));
READ_REG 2011 dev/pci/ises.c READ_REG(sc, ISES_DMA_READ_START),
READ_REG 2012 dev/pci/ises.c READ_REG(sc, ISES_DMA_READ_COUNT) >> 16);
READ_REG 2015 dev/pci/ises.c READ_REG(sc, ISES_DMA_WRITE_START),
READ_REG 2016 dev/pci/ises.c READ_REG(sc, ISES_DMA_WRITE_COUNT) & 0x00ff);
READ_REG 2018 dev/pci/ises.c stat = READ_REG(sc, ISES_DMA_STATUS);
READ_REG 258 dev/pci/lofn.c READ_REG(sc, LOFN_LENADDR(LOFN_WIN_2, ridx)) & LOFN_LENMASK);
READ_REG 261 dev/pci/lofn.c printf("%08X", READ_REG(sc, LOFN_REGADDR(LOFN_WIN_3, ridx, i)));
READ_REG 471 dev/pci/lofn.c reglen = ((READ_REG(sc, LOFN_LENADDR(LOFN_WIN_2, 3)) & LOFN_LENMASK) +
READ_REG 59 dev/pci/lofnvar.h #define READ_REG_0(sc,r) READ_REG((sc), (r) | LOFN_WIN_0)
READ_REG 60 dev/pci/lofnvar.h #define READ_REG_1(sc,r) READ_REG((sc), (r) | LOFN_WIN_1)
READ_REG 61 dev/pci/lofnvar.h #define READ_REG_2(sc,r) READ_REG((sc), (r) | LOFN_WIN_2)
READ_REG 62 dev/pci/lofnvar.h #define READ_REG_3(sc,r) READ_REG((sc), (r) | LOFN_WIN_3)
READ_REG 200 dev/pci/safe.c sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) &
READ_REG 261 dev/pci/safe.c devinfo = READ_REG(sc, SAFE_DEVINFO);
READ_REG 991 dev/pci/safe.c v = READ_REG(sc, SAFE_PE_DMACFG) &
READ_REG 1009 dev/pci/safe.c v = READ_REG(sc, SAFE_PE_DMACFG);
READ_REG 1040 dev/pci/safe.c (READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff,
READ_REG 1170 dev/pci/safe.c w = READ_REG(sc, SAFE_RNG_OUT);
READ_REG 1172 dev/pci/safe.c v = READ_REG(sc, SAFE_RNG_OUT);
READ_REG 1183 dev/pci/safe.c v = READ_REG(sc, SAFE_RNG_OUT);
READ_REG 1196 dev/pci/safe.c while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT)
READ_REG 1198 dev/pci/safe.c return (READ_REG(sc, SAFE_RNG_OUT));
READ_REG 1224 dev/pci/safe.c if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) {
READ_REG 1228 dev/pci/safe.c READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm));
READ_REG 1231 dev/pci/safe.c READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN);
READ_REG 1234 dev/pci/safe.c w = READ_REG(sc, SAFE_RNG_CNFG);
READ_REG 1244 dev/pci/safe.c if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) {
READ_REG 1246 dev/pci/safe.c READ_REG(sc, SAFE_RNG_CTRL) &
READ_REG 1253 dev/pci/safe.c READ_REG(sc, SAFE_RNG_CTRL) & ~SAFE_RNG_CTRL_SHORTEN);
READ_REG 1739 dev/pci/safe.c stat = READ_REG(sc, SAFE_HM_STAT);
READ_REG 1996 dev/pci/safe.c if (READ_REG(sc, SAFE_PK_FUNC) & SAFE_PK_FUNC_RUN) {
READ_REG 2007 dev/pci/safe.c buf[i] = letoh32(READ_REG(sc, SAFE_PK_RAM_START +
READ_REG 2045 dev/pci/safe.c READ_REG(sc, SAFE_DMA_ENDIAN), READ_REG(sc, SAFE_DMA_SRCADDR),
READ_REG 2046 dev/pci/safe.c READ_REG(sc, SAFE_DMA_DSTADDR), READ_REG(sc, SAFE_DMA_STAT));
READ_REG 2053 dev/pci/safe.c tag, READ_REG(sc, SAFE_HI_CFG), READ_REG(sc, SAFE_HI_MASK),
READ_REG 2054 dev/pci/safe.c READ_REG(sc, SAFE_HI_DESC_CNT), READ_REG(sc, SAFE_HU_STAT),
READ_REG 2055 dev/pci/safe.c READ_REG(sc, SAFE_HM_STAT));
READ_REG 2061 dev/pci/safe.c u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT);
READ_REG 339 dev/pci/ubsec.c stat = READ_REG(sc, BS_STAT);
READ_REG 422 dev/pci/ubsec.c volatile u_int32_t a = READ_REG(sc, BS_ERR);
READ_REG 456 dev/pci/ubsec.c if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
READ_REG 512 dev/pci/ubsec.c if ((stat = READ_REG(sc, BS_STAT)) &
READ_REG 1327 dev/pci/ubsec.c if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
READ_REG 1564 dev/pci/ubsec.c ctrl = READ_REG(sc, BS_CTRL);
READ_REG 1582 dev/pci/ubsec.c ctrl = READ_REG(sc, BS_CTRL);