ints             1344 dev/pci/if_tl.c 	u_int16_t		ints = 0;
ints             1350 dev/pci/if_tl.c 	ints = CSR_READ_2(sc, TL_HOST_INT);
ints             1351 dev/pci/if_tl.c 	CSR_WRITE_2(sc, TL_HOST_INT, ints);
ints             1352 dev/pci/if_tl.c 	type = (ints << 16) & 0xFFFF0000;
ints             1353 dev/pci/if_tl.c 	ivec = (ints & TL_VEC_MASK) >> 5;
ints             1354 dev/pci/if_tl.c 	ints = (ints & TL_INT_MASK) >> 2;
ints             1358 dev/pci/if_tl.c 	switch(ints) {
ints              728 dev/pci/ises.c 	u_int32_t ints, dma_status, cmd; 
ints              760 dev/pci/ises.c 	ints = READ_REG(sc, ISES_A_INTS);
ints              761 dev/pci/ises.c 	if (!(ints & sc->sc_intrmask)) {
ints              762 dev/pci/ises.c 		DPRINTF (("%s: other intr mask [%08x]\n", ints));
ints              767 dev/pci/ises.c 	WRITE_REG(sc, ISES_A_INTS, ints);
ints              777 dev/pci/ises.c 	if (ints & ISES_STAT_SW_OQSINC)
ints              780 dev/pci/ises.c 	if (ints & ISES_STAT_LNAU_BUSY_1) {
ints              787 dev/pci/ises.c 	if (ints & ISES_STAT_LNAU_BUSY_2) {
ints              794 dev/pci/ises.c 	if (ints & ISES_STAT_LNAU_ERR_1) {
ints              799 dev/pci/ises.c 	if (ints & ISES_STAT_LNAU_ERR_2) {
ints              804 dev/pci/ises.c 	if (ints & ISES_STAT_BCHU_OAF) {	/* output data available */
ints              810 dev/pci/ises.c 	if (ints & ISES_STAT_BCHU_ERR) {	/* We got a BCHU error */
ints              815 dev/pci/ises.c 	if (ints & ISES_STAT_BCHU_OFHF) {	/* Output is half full */
ints              821 dev/pci/ises.c 	if (ints & ISES_STAT_BCHU_OFF) {	/* Output is full */