root/dev/pci/pcscp.c

DEFINITIONS

1. pcscp_match
2. pcscp_attach
3. pcscp_read_reg
4. pcscp_write_reg
5. pcscp_dma_isintr
6. pcscp_dma_reset
7. pcscp_dma_intr
8. pcscp_dma_setup
9. pcscp_dma_go
10. pcscp_dma_stop
11. pcscp_dma_isactive

    1 /*      $OpenBSD: pcscp.c,v 1.14 2006/04/30 00:35:40 brad Exp $ */
    2 /*      $NetBSD: pcscp.c,v 1.26 2003/10/19 10:25:42 tsutsui Exp $       */
    4 /*-
    5  * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
   10  * NASA Ames Research Center; Izumi Tsutsui.
   11  *
   12  * Redistribution and use in source and binary forms, with or without
   13  * modification, are permitted provided that the following conditions
   14  * are met:
   15  * 1. Redistributions of source code must retain the above copyright
   16  *    notice, this list of conditions and the following disclaimer.
   17  * 2. Redistributions in binary form must reproduce the above copyright
   18  *    notice, this list of conditions and the following disclaimer in the
   19  *    documentation and/or other materials provided with the distribution.
   20  * 3. All advertising materials mentioning features or use of this software
   21  *    must display the following acknowledgement:
   22  *      This product includes software developed by the NetBSD
   23  *      Foundation, Inc. and its contributors.
   24  * 4. Neither the name of The NetBSD Foundation nor the names of its
   25  *    contributors may be used to endorse or promote products derived
   26  *    from this software without specific prior written permission.
   27  *
   28  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   29  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   30  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   31  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   32  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   38  * POSSIBILITY OF SUCH DAMAGE.
   39  */
   41 /*
   42  * pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI)
   43  * written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
   44  *
   45  * Technical manual available at
   46  * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/19113.pdf
   47  */
   49 #include <sys/param.h>
   50 #include <sys/systm.h>
   51 #include <sys/device.h>
   52 #include <sys/buf.h>
   54 #include <machine/bus.h>
   55 #include <machine/intr.h>
   57 #include <scsi/scsi_all.h>
   58 #include <scsi/scsiconf.h>
   59 #include <scsi/scsi_message.h>
   61 #include <dev/pci/pcireg.h>
   62 #include <dev/pci/pcivar.h>
   63 #include <dev/pci/pcidevs.h>
   65 #include <dev/ic/ncr53c9xreg.h>
   66 #include <dev/ic/ncr53c9xvar.h>
   68 #include <dev/pci/pcscpreg.h>
   70 #define IO_MAP_REG      0x10
   72 struct pcscp_softc {
   73         struct ncr53c9x_softc sc_ncr53c9x;      /* glue to MI code */
bus_space_tag_t sc_st;          /* bus space tag */
bus_space_handle_t sc_sh;       /* bus space handle */
   77         void *sc_ih;                    /* interrupt cookie */
bus_dma_tag_t sc_dmat;          /* DMA tag */
bus_dmamap_t sc_xfermap;        /* DMA map for transfers */
u_int32_t *sc_mdladdr;          /* MDL array */
bus_dmamap_t sc_mdldmap;        /* MDL DMA map */
   86         int     sc_active;              /* DMA state */
   87         int     sc_datain;              /* DMA Data Direction */
size_t  sc_dmasize;             /* DMA size */
   89         char    **sc_dmaaddr;           /* DMA address */
size_t  *sc_dmalen;             /* DMA length */
   91 };
   93 #define READ_DMAREG(sc, reg) \
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
   95 #define WRITE_DMAREG(sc, reg, var) \
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var))
   98 #define PCSCP_READ_REG(sc, reg) \
bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2)
  100 #define PCSCP_WRITE_REG(sc, reg, val) \
bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val))
  103 int     pcscp_match(struct device *, void *, void *); 
  104 void    pcscp_attach(struct device *, struct device *, void *);  
  106 struct cfattach pcscp_ca = {
  107         sizeof(struct pcscp_softc), pcscp_match, pcscp_attach
  108 };
  110 struct cfdriver pcscp_cd = {
NULL, "pcscp", DV_DULL
  112 };
  114 /*
  115  * Functions and the switch for the MI code.
  116  */
u_char  pcscp_read_reg(struct ncr53c9x_softc *, int);
  119 void    pcscp_write_reg(struct ncr53c9x_softc *, int, u_char);
  120 int     pcscp_dma_isintr(struct ncr53c9x_softc *);
  121 void    pcscp_dma_reset(struct ncr53c9x_softc *);
  122 int     pcscp_dma_intr(struct ncr53c9x_softc *);
  123 int     pcscp_dma_setup(struct ncr53c9x_softc *, caddr_t *,
size_t *, int, size_t *);
  125 void    pcscp_dma_go(struct ncr53c9x_softc *);
  126 void    pcscp_dma_stop(struct ncr53c9x_softc *);
  127 int     pcscp_dma_isactive(struct ncr53c9x_softc *);
  129 struct scsi_adapter pcscp_adapter = {
ncr53c9x_scsi_cmd,      /* cmd */
minphys,                /* minphys */
  132         0,                      /* open */
  133         0,                      /* close */
  134 };
  136 struct ncr53c9x_glue pcscp_glue = {
pcscp_read_reg,
pcscp_write_reg,
pcscp_dma_isintr,
pcscp_dma_reset,
pcscp_dma_intr,
pcscp_dma_setup,
pcscp_dma_go,
pcscp_dma_stop,
pcscp_dma_isactive,
NULL,                   /* gl_clear_latched_intr */
  147 };
  149 int
pcscp_match(struct device *parent, void *match, void *aux)
  151 {
  152         struct pci_attach_args *pa = aux;
  154         if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD)
  155                 return 0;
  157         switch (PCI_PRODUCT(pa->pa_id)) {
  158         case PCI_PRODUCT_AMD_PCSCSI_PCI:
  159                 return 1;
  160         }
  161         return 0;
  162 }
  164 /*
  165  * Attach this instance, and then all the sub-devices
  166  */
  167 void
pcscp_attach(struct device *parent, struct device *self, void *aux)
  169 {
  170         struct pci_attach_args *pa = aux;
  171         struct pcscp_softc *esc = (void *)self;
  172         struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
bus_space_tag_t iot;
bus_space_handle_t ioh;
pci_intr_handle_t ih;
  176         const char *intrstr;
bus_dma_segment_t seg;
  178         int error, rseg;
  180         if (pci_mapreg_map(pa, IO_MAP_REG, PCI_MAPREG_TYPE_IO, 0,
  181              &iot, &ioh, NULL, NULL, NULL)) {
printf("%s: unable to map registers\n", sc->sc_dev.dv_xname);
  183                 return;
  184         }
sc->sc_glue = &pcscp_glue;
esc->sc_st = iot;
esc->sc_sh = ioh;
esc->sc_dmat = pa->pa_dmat;
  192         /*
  193          * XXX More of this should be in ncr53c9x_attach(), but
  194          * XXX should we really poke around the chip that much in
  195          * XXX the MI code?  Think about this more...
  196          */
  198         /*
  199          * Set up static configuration info.
  200          */
  202         /*
  203          * XXX should read configuration from EEPROM?
  204          *
  205          * MI ncr53c9x driver does not support configuration
  206          * per each target device, though...
  207          */
sc->sc_id = 7;
sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK;
sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE;
sc->sc_rev = NCR_VARIANT_AM53C974;
sc->sc_features = NCR_F_FASTSCSI;
sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI;
sc->sc_freq = 40; /* MHz */
  218         /*
  219          * XXX minsync and maxxfer _should_ be set up in MI code,
  220          * XXX but it appears to have some dependency on what sort
  221          * XXX of DMA we're hooked up to, etc.
  222          */
  224         /*
  225          * This is the value used to start sync negotiations
  226          * Note that the NCR register "SYNCTP" is programmed
  227          * in "clocks per byte", and has a minimum value of 4.
  228          * The SCSI period used in negotiation is one-fourth
  229          * of the time (in nanoseconds) needed to transfer one byte.
  230          * Since the chip's clock is given in MHz, we have the following
  231          * formula: 4 * period = (1000 / freq) * 4
  232          */
sc->sc_minsync = 1000 / sc->sc_freq; 
  236         /* Really no limit, but since we want to fit into the TCR... */
sc->sc_maxxfer = 16 * 1024 * 1024;
  239         /*
  240          * Create the DMA maps for the data transfers.
  241          */
  243 #define MDL_SEG_SIZE    0x1000 /* 4kbyte per segment */
  244 #define MDL_SEG_OFFSET  0x0FFF
  245 #define MDL_SIZE        (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */
  247         if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MDL_SEG_SIZE,
MDL_SEG_SIZE, BUS_DMA_NOWAIT, &esc->sc_xfermap)) {
printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname);
  250                 return;
  251         }
  253         /*
  254          * Allocate and map memory for the MDL.
  255          */
  257         if ((error = bus_dmamem_alloc(esc->sc_dmat,
  258             sizeof(u_int32_t) * MDL_SIZE, PAGE_SIZE, 0, &seg, 1, &rseg,
BUS_DMA_NOWAIT)) != 0) {
printf("%s: unable to allocate memory for the MDL, "
  261                     "error = %d\n", sc->sc_dev.dv_xname, error);
  262                 goto fail_0;
  263         }
  264         if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg,
  265             sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr,
BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
printf("%s: unable to map the MDL memory, error = %d\n",
sc->sc_dev.dv_xname, error);
  269                 goto fail_1;
  270         }
  271         if ((error = bus_dmamap_create(esc->sc_dmat, 
  272             sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE,
  273             0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) {
printf("%s: unable to map_create for the MDL, error = %d\n",
sc->sc_dev.dv_xname, error);
  276                 goto fail_2;
  277         }
  278         if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap,
esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE,
NULL, BUS_DMA_NOWAIT)) != 0) {
printf("%s: unable to load for the MDL, error = %d\n",
sc->sc_dev.dv_xname, error);
  283                 goto fail_3;
  284         }
  286         /* map and establish interrupt */
  287         if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
  289                 goto fail_4;
  290         }
intrstr = pci_intr_string(pa->pa_pc, ih);
esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
ncr53c9x_intr, esc, sc->sc_dev.dv_xname);
  295         if (esc->sc_ih == NULL) {
printf(": couldn't establish interrupt");
  297                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
  300                 goto fail_4;
  301         }
  302         if (intrstr != NULL)
printf(": %s\n", intrstr);
  305         /* Do the common parts of attachment. */
printf("%s", sc->sc_dev.dv_xname);
ncr53c9x_attach(sc, &pcscp_adapter, NULL);
  310         /* Turn on target selection using the `dma' method */
sc->sc_features |= NCR_F_DMASELECT;
  313         return;
fail_4:
bus_dmamap_unload(esc->sc_dmat, esc->sc_mdldmap);
fail_3:
bus_dmamap_destroy(esc->sc_dmat, esc->sc_mdldmap);
fail_2:
bus_dmamem_unmap(esc->sc_dmat, (caddr_t)esc->sc_mdldmap,
  321             sizeof(uint32_t) * MDL_SIZE);
fail_1:
bus_dmamem_free(esc->sc_dmat, &seg, rseg);
fail_0:
bus_dmamap_destroy(esc->sc_dmat, esc->sc_xfermap);
  326 }
  328 /*
  329  * Glue functions.
  330  */
u_char
pcscp_read_reg(struct ncr53c9x_softc *sc, int reg)
  334 {
  335         struct pcscp_softc *esc = (struct pcscp_softc *)sc;
  337         return PCSCP_READ_REG(esc, reg);
  338 }
  340 void
pcscp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v)
  342 {
  343         struct pcscp_softc *esc = (struct pcscp_softc *)sc;
PCSCP_WRITE_REG(esc, reg, v);
  346 }
  348 int
pcscp_dma_isintr(struct ncr53c9x_softc *sc)
  350 {
  351         struct pcscp_softc *esc = (struct pcscp_softc *)sc;
  353         return (PCSCP_READ_REG(esc, NCR_STAT) & NCRSTAT_INT) != 0;
  354 }
  356 void
pcscp_dma_reset(struct ncr53c9x_softc *sc)
  358 {
  359         struct pcscp_softc *esc = (struct pcscp_softc *)sc;
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE);
esc->sc_active = 0;
  364 }
  366 int
pcscp_dma_intr(struct ncr53c9x_softc *sc)
  368 {
  369         struct pcscp_softc *esc = (struct pcscp_softc *)sc;
  370         int trans, resid, i;
bus_dmamap_t dmap = esc->sc_xfermap;
  372         int datain = esc->sc_datain;
u_int32_t dmastat;
  374         char *p = NULL;
dmastat = READ_DMAREG(esc, DMA_STAT);
  378         if (dmastat & DMASTAT_ERR) {
  379                 /* XXX not tested... */
WRITE_DMAREG(esc, DMA_CMD,
DMACMD_ABORT | (datain ? DMACMD_DIR : 0));
printf("%s: error: DMA error detected; Aborting.\n",
sc->sc_dev.dv_xname);
bus_dmamap_unload(esc->sc_dmat, dmap);
  386                 return -1;
  387         }
  389         if (dmastat & DMASTAT_ABT) {
  390                 /* XXX What should be done? */
printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname);
WRITE_DMAREG(esc, DMA_CMD,
DMACMD_IDLE | (datain ? DMACMD_DIR : 0));
esc->sc_active = 0;
  395                 return 0;
  396         }
  398 #ifdef DIAGNOSTIC
  399         /* This is an "assertion" :) */
  400         if (esc->sc_active == 0)
panic("pcscp dmaintr: DMA wasn't active");
  402 #endif
  404         /* DMA has stopped */
esc->sc_active = 0;
  408         if (esc->sc_dmasize == 0) {
  409                 /* A "Transfer Pad" operation completed */
NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
PCSCP_READ_REG(esc, NCR_TCL) |
  412                     (PCSCP_READ_REG(esc, NCR_TCM) << 8),
PCSCP_READ_REG(esc, NCR_TCL),
PCSCP_READ_REG(esc, NCR_TCM)));
  415                 return 0;
  416         }
resid = 0;
  419         /*
  420          * If a transfer onto the SCSI bus gets interrupted by the device
  421          * (e.g. for a SAVEPOINTER message), the data in the FIFO counts
  422          * as residual since the ESP counter registers get decremented as
  423          * bytes are clocked into the FIFO.
  424          */
  425         if (!datain &&
  426             (resid = (PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid));
  428         }
  430         if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
  431                 /*
  432                  * `Terminal count' is off, so read the residue
  433                  * out of the ESP counter registers.
  434                  */
  435                 if (datain) {
resid = PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF;
  437                         while (resid > 1)
resid =
PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF;
WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL |
  441                             (datain ? DMACMD_DIR : 0));
  443                         for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */
  444                                 if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP)
  445                                         break;
  447                         /* See the below comments... */
  448                         if (resid)
p = *esc->sc_dmaaddr;
  450                 }
resid += PCSCP_READ_REG(esc, NCR_TCL) |
  453                     (PCSCP_READ_REG(esc, NCR_TCM) << 8) |
  454                     (PCSCP_READ_REG(esc, NCR_TCH) << 16);
  455         } else {
  456                 while ((dmastat & DMASTAT_DONE) == 0)
dmastat = READ_DMAREG(esc, DMA_STAT);
  458         }
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0));
  462         /* sync MDL */
bus_dmamap_sync(esc->sc_dmat, esc->sc_mdldmap,
  464             0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_POSTWRITE);
  465         /* sync transfer buffer */
bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize,
datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(esc->sc_dmat, dmap);
trans = esc->sc_dmasize - resid;
  472         /*
  473          * From the technical manual notes:
  474          *
  475          * `In some odd byte conditions, one residual byte will be left
  476          *  in the SCSI FIFO, and the FIFO flags will never count to 0.
  477          *  When this happens, the residual byte should be retrieved
  478          *  via PIO following completion of the BLAST operation.'
  479          */
  481         if (p) {
p += trans;
  483                 *p = PCSCP_READ_REG(esc, NCR_FIFO);
trans++;
  485         }
  487         if (trans < 0) {                        /* transferred < 0 ? */
  488 #if 0
  489                 /*
  490                  * This situation can happen in perfectly normal operation
  491                  * if the ESP is reselected while using DMA to select
  492                  * another target.  As such, don't print the warning.
  493                  */
printf("%s: xfer (%d) > req (%d)\n",
sc->sc_dev.dv_xname, trans, esc->sc_dmasize);
  496 #endif
trans = esc->sc_dmasize;
  498         }
NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
PCSCP_READ_REG(esc, NCR_TCL),
PCSCP_READ_REG(esc, NCR_TCM),
PCSCP_READ_REG(esc, NCR_TCH),
trans, resid));
  506         *esc->sc_dmalen -= trans;
  507         *esc->sc_dmaaddr += trans;
  509         return 0;
  510 }
  512 int
pcscp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
  514     int datain, size_t *dmasize)
  515 {
  516         struct pcscp_softc *esc = (struct pcscp_softc *)sc;
bus_dmamap_t dmap = esc->sc_xfermap;
u_int32_t *mdl;
  519         int error, nseg, seg;
bus_addr_t s_offset, s_addr;
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0));
esc->sc_dmaaddr = addr;
esc->sc_dmalen = len;
esc->sc_dmasize = *dmasize;
esc->sc_datain = datain;
  529 #ifdef DIAGNOSTIC
  530         if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE)
panic("pcscp: transfer size too large");
  532 #endif
  534         /*
  535          * No need to set up DMA in `Transfer Pad' operation.
  536          * (case of *dmasize == 0)
  537          */
  538         if (*dmasize == 0)
  539                 return 0;
error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr,
  542             *esc->sc_dmalen, NULL,
  543             ((sc->sc_nexus->xs->flags & SCSI_NOSLEEP) ?
BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING |
  545             ((sc->sc_nexus->xs->flags & SCSI_DATA_IN) ?
BUS_DMA_READ : BUS_DMA_WRITE));
  547         if (error) {
printf("%s: unable to load dmamap, error = %d\n",
sc->sc_dev.dv_xname, error);
  550                 return error;
  551         }
  553         /* set transfer length */
WRITE_DMAREG(esc, DMA_STC, *dmasize); 
  556         /* set up MDL */
mdl = esc->sc_mdladdr;
nseg = dmap->dm_nsegs;
  560         /* the first segment is possibly not aligned with 4k MDL boundary */
s_addr = dmap->dm_segs[0].ds_addr;
s_offset = s_addr & MDL_SEG_OFFSET;
s_addr -= s_offset;
  565         /* set the first MDL and offset */
WRITE_DMAREG(esc, DMA_SPA, s_offset); 
  567         *mdl++ = htole32(s_addr);
  569         /* the rest dmamap segments are aligned with 4k boundary */
  570         for (seg = 1; seg < nseg; seg++)
  571                 *mdl++ = htole32(dmap->dm_segs[seg].ds_addr);
  573         return 0;
  574 }
  576 void
pcscp_dma_go(struct ncr53c9x_softc *sc)
  578 {
  579         struct pcscp_softc *esc = (struct pcscp_softc *)sc;
bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap;
  581         int datain = esc->sc_datain;
  583         /* No DMA transfer in Transfer Pad operation */
  584         if (esc->sc_dmasize == 0)
  585                 return;
  587         /* sync transfer buffer */
bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize,
datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
  591         /* sync MDL */
bus_dmamap_sync(esc->sc_dmat, mdldmap,
  593             0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_PREWRITE); 
  595         /* set Starting MDL Address */
WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr);
  598         /* set DMA command register bits */
  599         /* XXX DMA Transfer Interrupt Enable bit is broken? */
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL |
  601             /* DMACMD_INTE | */
  602             (datain ? DMACMD_DIR : 0));
  604         /* issue DMA start command */
WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL |
  606             /* DMACMD_INTE | */
  607             (datain ? DMACMD_DIR : 0));
esc->sc_active = 1;
  610 }
  612 void
pcscp_dma_stop(struct ncr53c9x_softc *sc)
  614 {
  615         struct pcscp_softc *esc = (struct pcscp_softc *)sc;
  617         /* dma stop */
  618         /* XXX What should we do here ? */
WRITE_DMAREG(esc, DMA_CMD,
DMACMD_ABORT | (esc->sc_datain ? DMACMD_DIR : 0));
bus_dmamap_unload(esc->sc_dmat, esc->sc_xfermap);
esc->sc_active = 0;
  624 }
  626 int
pcscp_dma_isactive(struct ncr53c9x_softc *sc)
  628 {
  629         struct pcscp_softc *esc = (struct pcscp_softc *)sc;
  631         /* XXX should check esc->sc_active? */
  632         if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE)
  633                 return 1;
  634         return 0;
  635 }