_sc 1881 dev/ic/ath.c #define PA2DESC(_sc, _pa) \ _sc 1882 dev/ic/ath.c ((struct ath_desc *)((caddr_t)(_sc)->sc_desc + \ _sc 1883 dev/ic/ath.c ((_pa) - (_sc)->sc_desc_paddr))) _sc 2640 dev/ic/ath.c #define PA2DESC(_sc, _pa) \ _sc 2641 dev/ic/ath.c ((struct ath_desc *)((caddr_t)(_sc)->sc_desc + \ _sc 2642 dev/ic/ath.c ((_pa) - (_sc)->sc_desc_paddr))) _sc 369 dev/ic/athvar.h #define ATH_LOCK_INIT(_sc) \ _sc 370 dev/ic/athvar.h mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ _sc 372 dev/ic/athvar.h #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) _sc 373 dev/ic/athvar.h #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) _sc 374 dev/ic/athvar.h #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) _sc 375 dev/ic/athvar.h #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) _sc 377 dev/ic/athvar.h #define ATH_TXBUF_LOCK_INIT(_sc) \ _sc 378 dev/ic/athvar.h mtx_init(&(_sc)->sc_txbuflock, \ _sc 379 dev/ic/athvar.h device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF) _sc 380 dev/ic/athvar.h #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) _sc 381 dev/ic/athvar.h #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) _sc 382 dev/ic/athvar.h #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) _sc 383 dev/ic/athvar.h #define ATH_TXBUF_LOCK_ASSERT(_sc) \ _sc 384 dev/ic/athvar.h mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) _sc 386 dev/ic/athvar.h #define ATH_TXQ_LOCK_INIT(_sc) \ _sc 387 dev/ic/athvar.h mtx_init(&(_sc)->sc_txqlock, \ _sc 388 dev/ic/athvar.h device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF) _sc 389 dev/ic/athvar.h #define ATH_TXQ_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txqlock) _sc 390 dev/ic/athvar.h #define ATH_TXQ_LOCK(_sc) mtx_lock(&(_sc)->sc_txqlock) _sc 391 dev/ic/athvar.h #define ATH_TXQ_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txqlock) _sc 392 dev/ic/athvar.h #define ATH_TXQ_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_txqlock, MA_OWNED) _sc 41 dev/ic/silivar.h #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) _sc 196 dev/pci/if_che.c #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) _sc 807 dev/pci/if_nxe.c #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) _sc 54 dev/pci/if_stgereg.h #define CSR_WRITE_4(_sc, reg, val) \ _sc 55 dev/pci/if_stgereg.h bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) _sc 56 dev/pci/if_stgereg.h #define CSR_WRITE_2(_sc, reg, val) \ _sc 57 dev/pci/if_stgereg.h bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) _sc 58 dev/pci/if_stgereg.h #define CSR_WRITE_1(_sc, reg, val) \ _sc 59 dev/pci/if_stgereg.h bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) _sc 61 dev/pci/if_stgereg.h #define CSR_READ_4(_sc, reg) \ _sc 62 dev/pci/if_stgereg.h bus_space_read_4((_sc)->sc_st, (_sc)->sc_sh, (reg)) _sc 63 dev/pci/if_stgereg.h #define CSR_READ_2(_sc, reg) \ _sc 64 dev/pci/if_stgereg.h bus_space_read_2((_sc)->sc_st, (_sc)->sc_sh, (reg)) _sc 65 dev/pci/if_stgereg.h #define CSR_READ_1(_sc, reg) \ _sc 66 dev/pci/if_stgereg.h bus_space_read_1((_sc)->sc_st, (_sc)->sc_sh, (reg)) _sc 635 dev/pci/if_tht.c #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) _sc 238 dev/pci/if_vic.c #define VIC_TXURN_WARN(_sc) ((_sc)->sc_txpending >= ((_sc)->sc_ntxbuf - 5)) _sc 239 dev/pci/if_vic.c #define VIC_TXURN(_sc) ((_sc)->sc_txpending >= (_sc)->sc_ntxbuf) _sc 279 dev/pci/if_vic.c #define VIC_DMA_DVA(_sc) ((_sc)->sc_dma_map->dm_segs[0].ds_addr) _sc 280 dev/pci/if_vic.c #define VIC_DMA_KVA(_sc) ((void *)(_sc)->sc_dma_kva) _sc 101 dev/pci/safe.c #define safe_dma_sync(_sc, _dma, _flags) \ _sc 102 dev/pci/safe.c bus_dmamap_sync((_sc)->sc_dmat, (_dma)->dma_map, 0, \