root/dev/pci/if_tht.c

DEFINITIONS

1. thtc_lookup
2. thtc_match
3. thtc_attach
4. thtc_print
5. tht_match
6. tht_attach
7. tht_mountroot
8. tht_intr
9. tht_ioctl
10. tht_up
11. tht_iff
12. tht_down
13. tht_start
14. tht_load_pkt
15. tht_txf
16. tht_rxf_fill
17. tht_rxf_drain
18. tht_rxd
19. tht_watchdog
20. tht_media_change
21. tht_media_status
22. tht_fifo_alloc
23. tht_fifo_free
24. tht_fifo_readable
25. tht_fifo_writable
26. tht_fifo_pre
27. tht_fifo_read
28. tht_fifo_write
29. tht_fifo_write_dmap
30. tht_fifo_write_pad
31. tht_fifo_post
32. tht_lladdr_read
33. tht_lladdr_write
34. tht_sw_reset
35. tht_fw_load
36. tht_fw_tick
37. tht_link_state
38. tht_read
39. tht_write
40. tht_write_region
41. tht_wait_eq
42. tht_wait_ne
43. tht_dmamem_alloc
44. tht_dmamem_free
45. tht_pkt_alloc
46. tht_pkt_free
47. tht_pkt_put
48. tht_pkt_get
49. tht_pkt_used

    1 /*      $OpenBSD: if_tht.c,v 1.108 2007/07/22 03:54:15 dlg Exp $ */
    3 /*
    4  * Copyright (c) 2007 David Gwynne <dlg@openbsd.org>
    5  *
    6  * Permission to use, copy, modify, and distribute this software for any
    7  * purpose with or without fee is hereby granted, provided that the above
    8  * copyright notice and this permission notice appear in all copies.
    9  *
   10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   17  */
   19 /*
   20  * Driver for the Tehuti TN30xx multi port 10Gb Ethernet chipsets,
   21  * see http://www.tehutinetworks.net/.
   22  *
   23  * This driver was made possible because Tehuti networks provided
   24  * hardware and documentation. Thanks!
   25  */
   27 #include "bpfilter.h"
   29 #include <sys/param.h>
   30 #include <sys/systm.h>
   31 #include <sys/sockio.h>
   32 #include <sys/mbuf.h>
   33 #include <sys/kernel.h>
   34 #include <sys/socket.h>
   35 #include <sys/malloc.h>
   36 #include <sys/device.h>
   37 #include <sys/proc.h>
   38 #include <sys/queue.h>
   39 #include <sys/rwlock.h>
   41 #include <machine/bus.h>
   43 #include <dev/pci/pcireg.h>
   44 #include <dev/pci/pcivar.h>
   45 #include <dev/pci/pcidevs.h>
   47 #include <net/if.h>
   48 #include <net/if_dl.h>
   49 #include <net/if_media.h>
   50 #include <net/if_types.h>
   52 #if NBPFILTER > 0
   53 #include <net/bpf.h>
   54 #endif
   56 #ifdef INET
   57 #include <netinet/in.h>
   58 #include <netinet/if_ether.h>
   59 #endif
   61 #ifdef THT_DEBUG
   62 #define THT_D_FIFO              (1<<0)
   63 #define THT_D_TX                (1<<1)
   64 #define THT_D_RX                (1<<2)
   65 #define THT_D_INTR              (1<<3)
   67 int thtdebug = THT_D_TX | THT_D_RX | THT_D_INTR;
   69 #define DPRINTF(l, f...)        do { if (thtdebug & (l)) printf(f); } while (0)
   70 #else
   71 #define DPRINTF(l, f...)
   72 #endif
   74 /* registers */
   76 #define THT_PCI_BAR             0x10
   78 #define _Q(_q)                  ((_q) * 4)
   80 /* General Configuration */
   81 #define THT_REG_END_SEL         0x5448 /* PCI Endian Select */
   82 #define THT_REG_CLKPLL          0x5000
   83 #define  THT_REG_CLKPLL_PLLLK           (1<<9) /* PLL is locked */
   84 #define  THT_REG_CLKPLL_RSTEND          (1<<8) /* Reset ended */
   85 #define  THT_REG_CLKPLL_TXF_DIS         (1<<3) /* TX Free disabled */
   86 #define  THT_REG_CLKPLL_VNT_STOP        (1<<2) /* VENETO Stop */
   87 #define  THT_REG_CLKPLL_PLLRST          (1<<1) /* PLL Reset */
   88 #define  THT_REG_CLKPLL_SFTRST          (1<<0) /* Software Reset */
   89 /* Descriptors and FIFO Registers */
   90 #define THT_REG_TXT_CFG0(_q)    (0x4040 + _Q(_q)) /* CFG0 TX Task queues */
   91 #define THT_REG_RXF_CFG0(_q)    (0x4050 + _Q(_q)) /* CFG0 RX Free queues */
   92 #define THT_REG_RXD_CFG0(_q)    (0x4060 + _Q(_q)) /* CFG0 RX DSC queues */
   93 #define THT_REG_TXF_CFG0(_q)    (0x4070 + _Q(_q)) /* CFG0 TX Free queues */
   94 #define THT_REG_TXT_CFG1(_q)    (0x4000 + _Q(_q)) /* CFG1 TX Task queues */
   95 #define THT_REG_RXF_CFG1(_q)    (0x4010 + _Q(_q)) /* CFG1 RX Free queues */
   96 #define THT_REG_RXD_CFG1(_q)    (0x4020 + _Q(_q)) /* CFG1 RX DSC queues */
   97 #define THT_REG_TXF_CFG1(_q)    (0x4030 + _Q(_q)) /* CFG1 TX Free queues */
   98 #define THT_REG_TXT_RPTR(_q)    (0x40c0 + _Q(_q)) /* TX Task read ptr */
   99 #define THT_REG_RXF_RPTR(_q)    (0x40d0 + _Q(_q)) /* RX Free read ptr */
  100 #define THT_REG_RXD_RPTR(_q)    (0x40e0 + _Q(_q)) /* RX DSC read ptr */
  101 #define THT_REG_TXF_RPTR(_q)    (0x40f0 + _Q(_q)) /* TX Free read ptr */
  102 #define THT_REG_TXT_WPTR(_q)    (0x4080 + _Q(_q)) /* TX Task write ptr */
  103 #define THT_REG_RXF_WPTR(_q)    (0x4090 + _Q(_q)) /* RX Free write ptr */
  104 #define THT_REG_RXD_WPTR(_q)    (0x40a0 + _Q(_q)) /* RX DSC write ptr */
  105 #define THT_REG_TXF_WPTR(_q)    (0x40b0 + _Q(_q)) /* TX Free write ptr */
  106 #define THT_REG_HTB_ADDR        0x4100 /* HTB Addressing Mechanism enable */
  107 #define THT_REG_HTB_ADDR_HI     0x4110 /* High HTB Address */
  108 #define THT_REG_HTB_ST_TMR      0x3290 /* HTB Timer */
  109 #define THT_REG_RDINTCM(_q)     (0x5120 + _Q(_q)) /* RX DSC Intr Coalescing */
  110 #define  THT_REG_RDINTCM_PKT_TH(_c)     ((_c)<<20) /* pkt count threshold */
  111 #define  THT_REG_RDINTCM_RXF_TH(_c)     ((_c)<<16) /* rxf intr req thresh */
  112 #define  THT_REG_RDINTCM_COAL_RC        (1<<15) /* coalescing timer recharge */
  113 #define  THT_REG_RDINTCM_COAL(_c)       (_c) /* coalescing timer */
  114 #define THT_REG_TDINTCM(_q)     (0x5130 + _Q(_q)) /* TX DSC Intr Coalescing */
  115 #define  THT_REG_TDINTCM_PKT_TH(_c)     ((_c)<<20) /* pkt count threshold */
  116 #define  THT_REG_TDINTCM_COAL_RC        (1<<15) /* coalescing timer recharge */
  117 #define  THT_REG_TDINTCM_COAL(_c)       (_c) /* coalescing timer */
  118 /* 10G Ethernet MAC */
  119 #define THT_REG_10G_REV         0x6000 /* Revision */
  120 #define THT_REG_10G_SCR         0x6004 /* Scratch */
  121 #define THT_REG_10G_CTL         0x6008 /* Control/Status */
  122 #define  THT_REG_10G_CTL_CMD_FRAME_EN   (1<<13) /* cmd frame enable */
  123 #define  THT_REG_10G_CTL_SW_RESET       (1<<12) /* sw reset */
  124 #define  THT_REG_10G_CTL_STATS_AUTO_CLR (1<<11) /* auto clear statistics */
  125 #define  THT_REG_10G_CTL_LOOPBACK       (1<<10) /* enable loopback */
  126 #define  THT_REG_10G_CTL_TX_ADDR_INS    (1<<9) /* set mac on tx */
  127 #define  THT_REG_10G_CTL_PAUSE_IGNORE   (1<<8) /* ignore pause */
  128 #define  THT_REG_10G_CTL_PAUSE_FWD      (1<<7) /* forward pause */
  129 #define  THT_REG_10G_CTL_CRC_FWD        (1<<6) /* crc forward */
  130 #define  THT_REG_10G_CTL_PAD            (1<<5) /* frame padding */
  131 #define  THT_REG_10G_CTL_PROMISC        (1<<4) /* promiscuous mode */
  132 #define  THT_REG_10G_CTL_WAN_MODE       (1<<3) /* WAN mode */
  133 #define  THT_REG_10G_CTL_RX_EN          (1<<1) /* RX enable */
  134 #define  THT_REG_10G_CTL_TX_EN          (1<<0) /* TX enable */
  135 #define THT_REG_10G_FRM_LEN     0x6014 /* Frame Length */
  136 #define THT_REG_10G_PAUSE       0x6018 /* Pause Quanta */
  137 #define THT_REG_10G_RX_SEC      0x601c /* RX Section */
  138 #define THT_REG_10G_TX_SEC      0x6020 /* TX Section */
  139 #define  THT_REG_10G_SEC_AVAIL(_t)      (_t) /* section available thresh*/
  140 #define  THT_REG_10G_SEC_EMPTY(_t)      ((_t)<<16) /* section empty avail */
  141 #define THT_REG_10G_RFIFO_AEF   0x6024 /* RX FIFO Almost Empty/Full */
  142 #define THT_REG_10G_TFIFO_AEF   0x6028 /* TX FIFO Almost Empty/Full */
  143 #define  THT_REG_10G_FIFO_AE(_t)        (_t) /* almost empty */
  144 #define  THT_REG_10G_FIFO_AF(_t)        ((_t)<<16) /* almost full */
  145 #define THT_REG_10G_SM_STAT     0x6030 /* MDIO Status */
  146 #define THT_REG_10G_SM_CMD      0x6034 /* MDIO Command */
  147 #define THT_REG_10G_SM_DAT      0x6038 /* MDIO Data */
  148 #define THT_REG_10G_SM_ADD      0x603c /* MDIO Address */
  149 #define THT_REG_10G_STAT        0x6040 /* Status */
  150 /* Statistic Counters */
  151 /* XXX todo */
  152 /* Status Registers */
  153 #define THT_REG_MAC_LNK_STAT    0x0200 /* Link Status */
  154 #define  THT_REG_MAC_LNK_STAT_DIS       (1<<4) /* Mac Stats read disable */
  155 #define  THT_REG_MAC_LNK_STAT_LINK      (1<<2) /* Link State */
  156 #define  THT_REG_MAC_LNK_STAT_REM_FAULT (1<<1) /* Remote Fault */
  157 #define  THT_REG_MAC_LNK_STAT_LOC_FAULT (1<<0) /* Local Fault */
  158 /* Interrupt Registers */
  159 #define THT_REG_ISR             0x5100 /* Interrupt Status */
  160 #define THT_REG_ISR_LINKCHG(_p)         (1<<(27+(_p))) /* link changed */
  161 #define THT_REG_ISR_GPIO                (1<<26) /* GPIO */
  162 #define THT_REG_ISR_RFRSH               (1<<25) /* DDR Refresh */
  163 #define THT_REG_ISR_SWI                 (1<<23) /* software interrupt */
  164 #define THT_REG_ISR_RXF(_q)             (1<<(19+(_q))) /* rx free fifo */
  165 #define THT_REG_ISR_TXF(_q)             (1<<(15+(_q))) /* tx free fifo */
  166 #define THT_REG_ISR_RXD(_q)             (1<<(11+(_q))) /* rx desc fifo */
  167 #define THT_REG_ISR_TMR(_t)             (1<<(6+(_t))) /* timer */
  168 #define THT_REG_ISR_VNT                 (1<<5) /* optistrata */
  169 #define THT_REG_ISR_RxFL                (1<<4) /* RX Full */
  170 #define THT_REG_ISR_TR                  (1<<2) /* table read */
  171 #define THT_REG_ISR_PCIE_LNK_INT        (1<<1) /* pcie link fail */
  172 #define THT_REG_ISR_GPLE_CLR            (1<<0) /* pcie timeout */
  173 #define THT_FMT_ISR             "\020" "\035LINKCHG1" "\034LINKCHG0" \
  174                                     "\033GPIO" "\032RFRSH" "\030SWI" \
  175                                     "\027RXF3" "\026RXF2" "\025RXF1" \
  176                                     "\024RXF0" "\023TXF3" "\022TXF2" \
  177                                     "\021TXF1" "\020TXF0" "\017RXD3" \
  178                                     "\016RXD2" "\015RXD1" "\014RXD0" \
  179                                     "\012TMR3" "\011TMR2" "\010TMR1" \
  180                                     "\007TMR0" "\006VNT" "\005RxFL" \
  181                                     "\003TR" "\002PCI_LNK_INT" \
  182                                     "\001GPLE_CLR"
  183 #define THT_REG_ISR_GTI         0x5080 /* GTI Interrupt Status */
  184 #define THT_REG_IMR             0x5110 /* Interrupt Mask */
  185 #define THT_REG_IMR_LINKCHG(_p)         (1<<(27+(_p))) /* link changed */
  186 #define THT_REG_IMR_GPIO                (1<<26) /* GPIO */
  187 #define THT_REG_IMR_RFRSH               (1<<25) /* DDR Refresh */
  188 #define THT_REG_IMR_SWI                 (1<<23) /* software interrupt */
  189 #define THT_REG_IMR_RXF(_q)             (1<<(19+(_q))) /* rx free fifo */
  190 #define THT_REG_IMR_TXF(_q)             (1<<(15+(_q))) /* tx free fifo */
  191 #define THT_REG_IMR_RXD(_q)             (1<<(11+(_q))) /* rx desc fifo */
  192 #define THT_REG_IMR_TMR(_t)             (1<<(6+(_t))) /* timer */
  193 #define THT_REG_IMR_VNT                 (1<<5) /* optistrata */
  194 #define THT_REG_IMR_RxFL                (1<<4) /* RX Full */
  195 #define THT_REG_IMR_TR                  (1<<2) /* table read */
  196 #define THT_REG_IMR_PCIE_LNK_INT        (1<<1) /* pcie link fail */
  197 #define THT_REG_IMR_GPLE_CLR            (1<<0) /* pcie timeout */
  198 #define THT_REG_IMR_GTI         0x5090 /* GTI Interrupt Mask */
  199 #define THT_REG_ISR_MSK         0x5140 /* ISR Masked */
  200 /* Global Counters */
  201 /* XXX todo */
  202 /* DDR2 SDRAM Controller Registers */
  203 /* XXX TBD */
  204 /* EEPROM Registers */
  205 /* XXX todo */
  206 /* Init arbitration and status registers */
  207 #define THT_REG_INIT_SEMAPHORE  0x5170 /* Init Semaphore */
  208 #define THT_REG_INIT_STATUS     0x5180 /* Init Status */
  209 /* PCI Credits Registers */
  210 /* XXX todo */
  211 /* TX Arbitration Registers */
  212 #define THT_REG_TXTSK_PR(_q)    (0x41b0 + _Q(_q)) /* TX Queue Priority */
  213 /* RX Part Registers */
  214 #define THT_REG_RX_FLT          0x1240 /* RX Filter Configuration */
  215 #define  THT_REG_RX_FLT_ATXER           (1<<15) /* accept with xfer err */
  216 #define  THT_REG_RX_FLT_ATRM            (1<<14) /* accept with term err */
  217 #define  THT_REG_RX_FLT_AFTSQ           (1<<13) /* accept with fault seq */
  218 #define  THT_REG_RX_FLT_OSEN            (1<<12) /* enable pkts */
  219 #define  THT_REG_RX_FLT_APHER           (1<<11) /* accept with phy err */
  220 #define  THT_REG_RX_FLT_TXFC            (1<<10) /* TX flow control */
  221 #define  THT_REG_RX_FLT_FDA             (1<<8) /* filter direct address */
  222 #define  THT_REG_RX_FLT_AOF             (1<<7) /* accept overflow frame */
  223 #define  THT_REG_RX_FLT_ACF             (1<<6) /* accept control frame */
  224 #define  THT_REG_RX_FLT_ARUNT           (1<<5) /* accept runt */
  225 #define  THT_REG_RX_FLT_ACRC            (1<<4) /* accept crc error */
  226 #define  THT_REG_RX_FLT_AM              (1<<3) /* accept multicast */
  227 #define  THT_REG_RX_FLT_AB              (1<<2) /* accept broadcast */
  228 #define  THT_REG_RX_FLT_PRM_MASK        0x3 /* promiscuous mode */
  229 #define  THT_REG_RX_FLT_PRM_NORMAL      0x0 /* normal mode */
  230 #define  THT_REG_RX_FLT_PRM_ALL         0x1 /* pass all incoming frames */
  231 #define THT_REG_RX_MAX_FRAME    0x12c0 /* Max Frame Size */
  232 #define THT_REG_RX_UNC_MAC0     0x1250 /* MAC Address low word */
  233 #define THT_REG_RX_UNC_MAC1     0x1260 /* MAC Address mid word */
  234 #define THT_REG_RX_UNC_MAC2     0x1270 /* MAC Address high word */
  235 #define THT_REG_RX_MAC_MCST0(_m) (0x1a80 + (_m)*8)
  236 #define THT_REG_RX_MAC_MCST1(_m) (0x1a84 + (_m)*8)
  237 #define  THT_REG_RX_MAC_MCST_CNT        15
  238 #define THT_REG_RX_MCST_HASH    0x1a00 /* imperfect multicast filter hash */
  239 #define  THT_REG_RX_MCST_HASH_SIZE      (256 / NBBY)
  240 /* OptiStrata Debug Registers */
  241 #define THT_REG_VPC             0x2300 /* Program Counter */
  242 #define THT_REG_VLI             0x2310 /* Last Interrupt */
  243 #define THT_REG_VIC             0x2320 /* Interrupts Count */
  244 #define THT_REG_VTMR            0x2330 /* Timer */
  245 #define THT_REG_VGLB            0x2340 /* Global */
  246 /* SW Reset Registers */
  247 #define THT_REG_RST_PRT         0x7000 /* Reset Port */
  248 #define  THT_REG_RST_PRT_ACTIVE         0x1 /* port reset is active */
  249 #define THT_REG_DIS_PRT         0x7010 /* Disable Port */
  250 #define THT_REG_RST_QU_0        0x7020 /* Reset Queue 0 */
  251 #define THT_REG_RST_QU_1        0x7028 /* Reset Queue 1 */
  252 #define THT_REG_DIS_QU_0        0x7030 /* Disable Queue 0 */
  253 #define THT_REG_DIS_QU_1        0x7038 /* Disable Queue 1 */
  255 #define THT_PORT_SIZE           0x8000
  256 #define THT_PORT_REGION(_p)     ((_p) * THT_PORT_SIZE)
  257 #define THT_NQUEUES             4
  259 #define THT_FIFO_ALIGN          4096
  260 #define THT_FIFO_SIZE_4k        0x0
  261 #define THT_FIFO_SIZE_8k        0x1
  262 #define THT_FIFO_SIZE_16k       0x2
  263 #define THT_FIFO_SIZE_32k       0x3
  264 #define THT_FIFO_SIZE(_r)       (4096 * (1<<(_r)))
  265 #define THT_FIFO_GAP            8 /* keep 8 bytes between ptrs */
  266 #define THT_FIFO_PTR_MASK       0x00007ff8 /* rptr/wptr mask */
  268 #define THT_FIFO_DESC_LEN       208 /* a descriptor cant be bigger than this */
  270 #define THT_IMR_DOWN(_p)        (THT_REG_IMR_LINKCHG(_p))
  271 #define THT_IMR_UP(_p)          (THT_REG_IMR_LINKCHG(_p) | \
THT_REG_IMR_RXF(0) | THT_REG_IMR_TXF(0) | \
THT_REG_IMR_RXD(0))
  275 /* hardware structures (we're using the 64 bit variants) */
  277 /* physical buffer descriptor */
  278 struct tht_pbd {
u_int32_t               addr_lo;
u_int32_t               addr_hi;
u_int32_t               len;
  282 } __packed;
  283 #define THT_PBD_PKTLEN          (64 * 1024)
  285 /* rx free fifo */
  286 struct tht_rx_free {
u_int16_t               bc; /* buffer count (0:4) */
u_int16_t               type;
u_int64_t               uid;
  292         /* followed by a pdb list */
  293 } __packed;
  294 #define THT_RXF_TYPE            1
  295 #define THT_RXF_1ST_PDB_LEN     128
  296 #define THT_RXF_SGL_LEN         ((THT_FIFO_DESC_LEN - \
  297                                     sizeof(struct tht_rx_free)) / \
  298                                     sizeof(struct tht_pbd))
  300 /* rx descriptor */
  301 struct tht_rx_desc {
u_int32_t               flags;
  303 #define THT_RXD_FLAGS_BC(_f)            ((_f) & 0x1f) /* buffer count */
  304 #define THT_RXD_FLAGS_RXFQ(_f)          (((_f)>>8) & 0x3) /* rxf queue id */
  305 #define THT_RXD_FLAGS_TO                (1<<15)
  306 #define THT_RXD_FLAGS_TYPE(_f)          (((_f)>>16) & 0xf) /* desc type */
  307 #define THT_RXD_FLAGS_OVF               (1<<21) /* overflow error */
  308 #define THT_RXD_FLAGS_RUNT              (1<<22) /* runt error */
  309 #define THT_RXD_FLAGS_CRC               (1<<23) /* crc error */
  310 #define THT_RXD_FLAGS_UDPCS             (1<<24) /* udp checksum error */
  311 #define THT_RXD_FLAGS_TCPCS             (1<<25) /* tcp checksum error */
  312 #define THT_RXD_FLAGS_IPCS              (1<<26) /* ip checksum error */
  313 #define THT_RXD_FLAGS_PKT_ID            0x70000000
  314 #define THT_RXD_FLAGS_PKT_ID_NONIP      0x00000000
  315 #define THT_RXD_FLAGS_PKT_ID_TCP4       0x10000000
  316 #define THT_RXD_FLAGS_PKT_ID_UDP4       0x20000000
  317 #define THT_RXD_FLAGS_PKT_ID_IPV4       0x30000000
  318 #define THT_RXD_FLAGS_PKT_ID_TCP6       0x50000000
  319 #define THT_RXD_FLAGS_PKT_ID_UDP6       0x60000000
  320 #define THT_RXD_FLAGS_PKT_ID_IPV6       0x70000000
  321 #define THT_RXD_FLAGS_VTAG              (1<<31)
u_int16_t               len;
u_int16_t               vlan;
  324 #define THT_RXD_VLAN_ID(_v)             ((_v) & 0xfff)
  325 #define THT_RXD_VLAN_CFI                (1<<12)
  326 #define THT_RXD_VLAN_PRI(_v)            ((_v) & 0x7) >> 13)
u_int64_t               uid;
  329 } __packed;
  330 #define THT_RXD_TYPE            2
  332 /* rx decriptor type 3: data chain instruction */
  333 struct tht_rx_desc_dc {
  334         /* preceded by tht_rx_desc */
u_int16_t               cd_offset;
u_int16_t               flags;
u_int8_t                data[4];
  340 } __packed;
  341 #define THT_RXD_TYPE_DC         3
  343 /* rx descriptor type 4: rss (recv side scaling) information */
  344 struct tht_rx_desc_rss {
  345         /* preceded by tht_rx_desc */
u_int8_t                rss_hft;
u_int8_t                rss_type;
u_int8_t                rss_tcpu;
u_int8_t                reserved;
u_int32_t               rss_hash;
  353 } __packed;
  354 #define THT_RXD_TYPE_RSS        4
  356 /* tx task fifo */
  357 struct tht_tx_task {
u_int32_t               flags;
  359 #define THT_TXT_FLAGS_BC(_f)    (_f) /* buffer count */
  360 #define THT_TXT_FLAGS_UDPCS     (1<<5) /* udp checksum */
  361 #define THT_TXT_FLAGS_TCPCS     (1<<6) /* tcp checksum */
  362 #define THT_TXT_FLAGS_IPCS      (1<<7) /* ip checksum */
  363 #define THT_TXT_FLAGS_VTAG      (1<<8) /* insert vlan tag */
  364 #define THT_TXT_FLAGS_LGSND     (1<<9) /* tcp large send enabled */
  365 #define THT_TXT_FLAGS_FRAG      (1<<10) /* ip fragmentation enabled */
  366 #define THT_TXT_FLAGS_CFI       (1<<12) /* canonical format indicator */
  367 #define THT_TXT_FLAGS_PRIO(_f)  ((_f)<<13) /* vlan priority */
  368 #define THT_TXT_FLAGS_VLAN(_f)  ((_f)<<20) /* vlan id */
u_int16_t               mss_mtu;
u_int16_t               len;
u_int64_t               uid;
  374         /* followed by a pbd list */
  375 } __packed;
  376 #define THT_TXT_TYPE            (3<<16)
  377 #define THT_TXT_SGL_LEN         ((THT_FIFO_DESC_LEN - \
  378                                     sizeof(struct tht_tx_task)) / \
  379                                     sizeof(struct tht_pbd))
  381 /* tx free fifo */
  382 struct tht_tx_free {
u_int32_t               status;
u_int64_t               uid;
u_int32_t               pad;
  388 } __packed;
  390 /* pci controller autoconf glue */
  392 struct thtc_softc {
  393         struct device           sc_dev;
bus_dma_tag_t           sc_dmat;
bus_space_tag_t         sc_memt;
bus_space_handle_t      sc_memh;
bus_size_t              sc_mems;
  400 };
  402 int                     thtc_match(struct device *, void *, void *);
  403 void                    thtc_attach(struct device *, struct device *, void *);
  404 int                     thtc_print(void *, const char *);
  406 struct cfattach thtc_ca = {
  407         sizeof(struct thtc_softc), thtc_match, thtc_attach
  408 };
  410 struct cfdriver thtc_cd = {
NULL, "thtc", DV_DULL
  412 };
  414 /* glue between the controller and the port */
  416 struct tht_attach_args {
  417         int                     taa_port;
  419         struct pci_attach_args  *taa_pa;
pci_intr_handle_t       taa_ih;
  421 };
  423 /* tht itself */
  425 struct tht_dmamem {
bus_dmamap_t            tdm_map;
bus_dma_segment_t       tdm_seg;
size_t                  tdm_size;
caddr_t                 tdm_kva;
  430 };
  431 #define THT_DMA_MAP(_tdm)       ((_tdm)->tdm_map)
  432 #define THT_DMA_DVA(_tdm)       ((_tdm)->tdm_map->dm_segs[0].ds_addr)
  433 #define THT_DMA_KVA(_tdm)       ((void *)(_tdm)->tdm_kva)
  435 struct tht_fifo_desc {
bus_size_t              tfd_cfg0;
bus_size_t              tfd_cfg1;
bus_size_t              tfd_rptr;
bus_size_t              tfd_wptr;
u_int32_t               tfd_size;
  441         int                     tfd_write;
  442 };
  443 #define THT_FIFO_PRE_SYNC(_d)   ((_d)->tfd_write ? \
BUS_DMASYNC_PREWRITE : \
BUS_DMASYNC_PREREAD)
  446 #define THT_FIFO_POST_SYNC(_d)  ((_d)->tfd_write ? \
BUS_DMASYNC_POSTWRITE : \
BUS_DMASYNC_POSTREAD)
  450 struct tht_fifo {
  451         struct tht_fifo_desc    *tf_desc;
  452         struct tht_dmamem       *tf_mem;
  453         int                     tf_len;
  454         int                     tf_rptr;
  455         int                     tf_wptr;
  456         int                     tf_ready;
  457 };
  459 struct tht_pkt {
u_int64_t               tp_id;
bus_dmamap_t            tp_dmap;
  463         struct mbuf             *tp_m;
TAILQ_ENTRY(tht_pkt)    tp_link;
  466 };
  468 struct tht_pkt_list {
  469         struct tht_pkt          *tpl_pkts;
TAILQ_HEAD(, tht_pkt)   tpl_free;
TAILQ_HEAD(, tht_pkt)   tpl_used;
  472 };
  474 struct tht_softc {
  475         struct device           sc_dev;
  476         struct thtc_softc       *sc_thtc;
  477         int                     sc_port;
  479         void                    *sc_ih;
bus_space_handle_t      sc_memh;
  483         struct arpcom           sc_ac;
  484         struct ifmedia          sc_media;
u_int16_t               sc_lladdr[3];
  488         struct tht_pkt_list     sc_tx_list;
  489         struct tht_pkt_list     sc_rx_list;
  491         struct tht_fifo         sc_txt;
  492         struct tht_fifo         sc_rxf;
  493         struct tht_fifo         sc_rxd;
  494         struct tht_fifo         sc_txf;
u_int32_t               sc_imr;
  498         struct rwlock           sc_lock;
  499 };
  501 int                     tht_match(struct device *, void *, void *);
  502 void                    tht_attach(struct device *, struct device *, void *);
  503 void                    tht_mountroot(void *);
  504 int                     tht_intr(void *);
  506 struct cfattach tht_ca = {
  507         sizeof(struct tht_softc), tht_match, tht_attach
  508 };
  510 struct cfdriver tht_cd = {
NULL, "tht", DV_IFNET
  512 };
  514 /* pkts */
  515 int                     tht_pkt_alloc(struct tht_softc *,
  516                             struct tht_pkt_list *, int, int);
  517 void                    tht_pkt_free(struct tht_softc *,
  518                             struct tht_pkt_list *);
  519 void                    tht_pkt_put(struct tht_pkt_list *, struct tht_pkt *);
  520 struct tht_pkt          *tht_pkt_get(struct tht_pkt_list *);
  521 struct tht_pkt          *tht_pkt_used(struct tht_pkt_list *);
  523 /* fifos */
  525 struct tht_fifo_desc tht_txt_desc = {
THT_REG_TXT_CFG0(0),
THT_REG_TXT_CFG1(0),
THT_REG_TXT_RPTR(0),
THT_REG_TXT_WPTR(0),
THT_FIFO_SIZE_16k,
  531         1
  532 };
  534 struct tht_fifo_desc tht_rxf_desc = {
THT_REG_RXF_CFG0(0),
THT_REG_RXF_CFG1(0),
THT_REG_RXF_RPTR(0),
THT_REG_RXF_WPTR(0),
THT_FIFO_SIZE_16k,
  540         1
  541 };
  543 struct tht_fifo_desc tht_rxd_desc = {
THT_REG_RXD_CFG0(0),
THT_REG_RXD_CFG1(0),
THT_REG_RXD_RPTR(0),
THT_REG_RXD_WPTR(0),
THT_FIFO_SIZE_16k,
  549         0
  550 };
  552 struct tht_fifo_desc tht_txf_desc = {
THT_REG_TXF_CFG0(0),
THT_REG_TXF_CFG1(0),
THT_REG_TXF_RPTR(0),
THT_REG_TXF_WPTR(0),
THT_FIFO_SIZE_4k,
  558         0
  559 };
  561 int                     tht_fifo_alloc(struct tht_softc *, struct tht_fifo *,
  562                             struct tht_fifo_desc *);
  563 void                    tht_fifo_free(struct tht_softc *, struct tht_fifo *);
size_t                  tht_fifo_readable(struct tht_softc *,
  566                             struct tht_fifo *);
size_t                  tht_fifo_writable(struct tht_softc *,
  568                             struct tht_fifo *);
  569 void                    tht_fifo_pre(struct tht_softc *,
  570                             struct tht_fifo *);
  571 void                    tht_fifo_read(struct tht_softc *, struct tht_fifo *,
  572                             void *, size_t);
  573 void                    tht_fifo_write(struct tht_softc *, struct tht_fifo *,
  574                             void *, size_t);
  575 void                    tht_fifo_write_dmap(struct tht_softc *,
  576                             struct tht_fifo *, bus_dmamap_t);
  577 void                    tht_fifo_write_pad(struct tht_softc *,
  578                             struct tht_fifo *, int);
  579 void                    tht_fifo_post(struct tht_softc *,
  580                             struct tht_fifo *);
  582 /* port operations */
  583 void                    tht_lladdr_read(struct tht_softc *);
  584 void                    tht_lladdr_write(struct tht_softc *);
  585 int                     tht_sw_reset(struct tht_softc *);
  586 int                     tht_fw_load(struct tht_softc *);
  587 void                    tht_fw_tick(void *arg);
  588 void                    tht_link_state(struct tht_softc *);
  590 /* interface operations */
  591 int                     tht_ioctl(struct ifnet *, u_long, caddr_t);
  592 void                    tht_watchdog(struct ifnet *);
  593 void                    tht_start(struct ifnet *);
  594 int                     tht_load_pkt(struct tht_softc *, struct tht_pkt *,
  595                             struct mbuf *);
  596 void                    tht_txf(struct tht_softc *sc);
  598 void                    tht_rxf_fill(struct tht_softc *, int);
  599 void                    tht_rxf_drain(struct tht_softc *);
  600 void                    tht_rxd(struct tht_softc *);
  602 void                    tht_up(struct tht_softc *);
  603 void                    tht_iff(struct tht_softc *);
  604 void                    tht_down(struct tht_softc *);
  606 /* ifmedia operations */
  607 int                     tht_media_change(struct ifnet *);
  608 void                    tht_media_status(struct ifnet *, struct ifmediareq *);
  610 /* wrapper around dma memory */
  611 struct tht_dmamem       *tht_dmamem_alloc(struct tht_softc *, bus_size_t,
bus_size_t);
  613 void                    tht_dmamem_free(struct tht_softc *,
  614                             struct tht_dmamem *);
  616 /* bus space operations */
u_int32_t               tht_read(struct tht_softc *, bus_size_t);
  618 void                    tht_write(struct tht_softc *, bus_size_t, u_int32_t);
  619 void                    tht_write_region(struct tht_softc *, bus_size_t,
  620                             void *, size_t);
  621 int                     tht_wait_eq(struct tht_softc *, bus_size_t, u_int32_t,
u_int32_t, int);
  623 int                     tht_wait_ne(struct tht_softc *, bus_size_t, u_int32_t,
u_int32_t, int);
  626 #define tht_set(_s, _r, _b)             tht_write((_s), (_r), \
tht_read((_s), (_r)) | (_b))
  628 #define tht_clr(_s, _r, _b)             tht_write((_s), (_r), \
tht_read((_s), (_r)) & ~(_b))
  630 #define tht_wait_set(_s, _r, _b, _t)    tht_wait_eq((_s), (_r), \
  631                                             (_b), (_b), (_t))
  634 /* misc */
  635 #define DEVNAME(_sc)    ((_sc)->sc_dev.dv_xname)
  636 #define sizeofa(_a)     (sizeof(_a) / sizeof((_a)[0]))
  637 #define LWORDS(_b)      (((_b) + 7) >> 3)
  640 struct thtc_device {
pci_vendor_id_t         td_vendor;
pci_vendor_id_t         td_product;
u_int                   td_nports;
  644 };
  646 const struct thtc_device *thtc_lookup(struct pci_attach_args *);
  648 static const struct thtc_device thtc_devices[] = {
  649         { PCI_VENDOR_TEHUTI,    PCI_PRODUCT_TEHUTI_TN3009, 1 },
  650         { PCI_VENDOR_TEHUTI,    PCI_PRODUCT_TEHUTI_TN3010, 1 },
  651         { PCI_VENDOR_TEHUTI,    PCI_PRODUCT_TEHUTI_TN3014, 2 }
  652 };
  654 const struct thtc_device *
thtc_lookup(struct pci_attach_args *pa)
  656 {
  657         int                             i;
  658         const struct thtc_device        *td;
  660         for (i = 0; i < sizeofa(thtc_devices); i++) {
td = &thtc_devices[i];
  662                 if (td->td_vendor == PCI_VENDOR(pa->pa_id) &&
td->td_product == PCI_PRODUCT(pa->pa_id))
  664                         return (td);
  665         }
  667         return (NULL);
  668 }
  670 int
thtc_match(struct device *parent, void *match, void *aux)
  672 {
  673         struct pci_attach_args          *pa = aux;
  675         if (thtc_lookup(pa) != NULL)
  676                 return (1);
  678         return (0);
  679 }
  681 void
thtc_attach(struct device *parent, struct device *self, void *aux)
  683 {
  684         struct thtc_softc               *sc = (struct thtc_softc *)self;
  685         struct pci_attach_args          *pa = aux;
pcireg_t                        memtype;
  687         const struct thtc_device        *td;
  688         struct tht_attach_args          taa;
  689         int                             i;
bzero(&taa, sizeof(taa));
td = thtc_lookup(pa);
sc->sc_dmat = pa->pa_dmat;
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, THT_PCI_BAR);
  697         if (pci_mapreg_map(pa, THT_PCI_BAR, memtype, 0, &sc->sc_memt,
  698             &sc->sc_memh, NULL, &sc->sc_mems, 0) != 0) {
printf(": unable to map host registers\n");
  700                 return;
  701         }
  703         if (pci_intr_map(pa, &taa.taa_ih) != 0) {
printf(": unable to map interrupt\n");
  705                 goto unmap;
  706         }
printf(": %s\n", pci_intr_string(pa->pa_pc, taa.taa_ih));
taa.taa_pa = pa;
  710         for (i = 0; i < td->td_nports; i++) {
taa.taa_port = i;
config_found(self, &taa, thtc_print);
  714         }
  716         return;
unmap:
bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems);
sc->sc_mems = 0;
  721 }
  723 int
thtc_print(void *aux, const char *pnp)
  725 {
  726         struct tht_attach_args          *taa = aux;
  728         if (pnp != NULL)
printf("\"%s\" at %s", tht_cd.cd_name, pnp);
printf(" port %d", taa->taa_port);
  733         return (UNCONF);
  734 }
  736 int
tht_match(struct device *parent, void *match, void *aux)
  738 {
  739         return (1);
  740 }
  742 void
tht_attach(struct device *parent, struct device *self, void *aux)
  744 {
  745         struct thtc_softc               *csc = (struct thtc_softc *)parent;
  746         struct tht_softc                *sc = (struct tht_softc *)self;
  747         struct tht_attach_args          *taa = aux;
  748         struct ifnet                    *ifp;
sc->sc_thtc = csc;
sc->sc_port = taa->taa_port;
sc->sc_imr = THT_IMR_DOWN(sc->sc_port);
rw_init(&sc->sc_lock, "thtioc");
  755         if (bus_space_subregion(csc->sc_memt, csc->sc_memh,
THT_PORT_REGION(sc->sc_port), THT_PORT_SIZE,
  757             &sc->sc_memh) != 0) {
printf(": unable to map port registers\n");
  759                 return;
  760         }
  762         if (tht_sw_reset(sc) != 0) {
printf(": unable to reset port\n");
  764                 /* bus_space(9) says we dont have to free subregions */
  765                 return;
  766         }
sc->sc_ih = pci_intr_establish(taa->taa_pa->pa_pc, taa->taa_ih,
IPL_NET, tht_intr, sc, DEVNAME(sc));
  770         if (sc->sc_ih == NULL) {
printf(": unable to establish interrupt\n");
  772                 /* bus_space(9) says we dont have to free subregions */
  773                 return;
  774         }
tht_lladdr_read(sc);
bcopy(sc->sc_lladdr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN);
ifp = &sc->sc_ac.ac_if;
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 |
IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
ifp->if_ioctl = tht_ioctl;
ifp->if_start = tht_start;
ifp->if_watchdog = tht_watchdog;
ifp->if_hardmtu = MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN; /* XXX */
strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ);
IFQ_SET_MAXLEN(&ifp->if_snd, 400);
IFQ_SET_READY(&ifp->if_snd);
ifmedia_init(&sc->sc_media, 0, tht_media_change, tht_media_status);
ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_AUTO, 0, NULL);
ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO);
if_attach(ifp);
ether_ifattach(ifp);
printf(": address %s\n", ether_sprintf(sc->sc_ac.ac_enaddr));
mountroothook_establish(tht_mountroot, sc);
  802 }
  804 void
tht_mountroot(void *arg)
  806 {
  807         struct tht_softc                *sc = arg;
  809         if (tht_fifo_alloc(sc, &sc->sc_txt, &tht_txt_desc) != 0)
  810                 return;
  812         if (tht_fw_load(sc) != 0)
printf("%s: firmware load failed\n", DEVNAME(sc));
tht_sw_reset(sc);
tht_fifo_free(sc, &sc->sc_txt);
tht_link_state(sc);
tht_write(sc, THT_REG_IMR, sc->sc_imr);
  821 }
  823 int
tht_intr(void *arg)
  825 {
  826         struct tht_softc                *sc = arg;
  827         struct ifnet                    *ifp;
u_int32_t                       isr;
isr = tht_read(sc, THT_REG_ISR);
  831         if (isr == 0x0) {
tht_write(sc, THT_REG_IMR, sc->sc_imr);
  833                 return (0);
  834         }
DPRINTF(THT_D_INTR, "%s: isr: 0x%b\n", DEVNAME(sc), isr, THT_FMT_ISR);
  838         if (ISSET(isr, THT_REG_ISR_LINKCHG(0) | THT_REG_ISR_LINKCHG(1)))
tht_link_state(sc);
ifp = &sc->sc_ac.ac_if;
  842         if (ifp->if_flags & IFF_RUNNING) {
  843                 if (ISSET(isr, THT_REG_ISR_RXD(0)))
tht_rxd(sc);
  846                 if (ISSET(isr, THT_REG_ISR_RXF(0)))
tht_rxf_fill(sc, 0);
  849                 if (ISSET(isr, THT_REG_ISR_TXF(0)))
tht_txf(sc);
tht_start(ifp);
  853         }
tht_write(sc, THT_REG_IMR, sc->sc_imr);
  856         return (1);
  857 }
  859 int
tht_ioctl(struct ifnet *ifp, u_long cmd, caddr_t addr)
  861 {
  862         struct tht_softc                *sc = ifp->if_softc;
  863         struct ifreq                    *ifr = (struct ifreq *)addr;
  864         struct ifaddr                   *ifa;
  865         int                             error;
  866         int                             s;
rw_enter_write(&sc->sc_lock);
s = splnet();
error = ether_ioctl(ifp, &sc->sc_ac, cmd, addr);
  872         if (error > 0)
  873                 goto err;
  875         switch (cmd) {
  876         case SIOCSIFADDR:
ifa = (struct ifaddr *)addr;
  879 #ifdef INET
  880                 if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc->sc_ac, ifa);
  882 #endif
ifp->if_flags |= IFF_UP;
  885                 /* FALLTHROUGH */
  886         case SIOCSIFFLAGS:
  887                 if (ifp->if_flags & IFF_UP) {
  888                         if (ifp->if_flags & IFF_RUNNING)
tht_iff(sc);
  890                         else
tht_up(sc);
  892                 } else {
  893                         if (ifp->if_flags & IFF_RUNNING)
tht_down(sc);
  895                 }
  896                 break;
  898         case SIOCSIFMTU:
  899                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
error = EINVAL;
  901                 else
ifp->if_mtu = ifr->ifr_mtu;
  903                 break;
  905         case SIOCADDMULTI:
error = ether_addmulti(ifr, &sc->sc_ac);
  907                 break;
  908         case SIOCDELMULTI:
error = ether_delmulti(ifr, &sc->sc_ac);
  910                 break;
  912         case SIOCGIFMEDIA:
  913         case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
  915                 break;
  917         default:
error = ENOTTY;
  919                 break;
  920         }
  922         if (error == ENETRESET) {
  923                 if (ifp->if_flags & IFF_RUNNING)
tht_iff(sc);
error = 0;
  926         }
err:
splx(s);
rw_exit_write(&sc->sc_lock);
  932         return (error);
  933 }
  935 void
tht_up(struct tht_softc *sc)
  937 {
  938         struct ifnet                    *ifp = &sc->sc_ac.ac_if;
  940         if (ISSET(ifp->if_flags, IFF_RUNNING)) {
printf("%s: interface is already up\n", DEVNAME(sc));
  942                 return;
  943         }
  945         if (tht_pkt_alloc(sc, &sc->sc_tx_list, 128, THT_TXT_SGL_LEN) != 0)
  946                 return;
  947         if (tht_pkt_alloc(sc, &sc->sc_rx_list, 128, THT_RXF_SGL_LEN) != 0)
  948                 goto free_tx_list;
  950         if (tht_fifo_alloc(sc, &sc->sc_txt, &tht_txt_desc) != 0)
  951                 goto free_rx_list;
  952         if (tht_fifo_alloc(sc, &sc->sc_rxf, &tht_rxf_desc) != 0)
  953                 goto free_txt;
  954         if (tht_fifo_alloc(sc, &sc->sc_rxd, &tht_rxd_desc) != 0)
  955                 goto free_rxf;
  956         if (tht_fifo_alloc(sc, &sc->sc_txf, &tht_txf_desc) != 0)
  957                 goto free_rxd;
tht_write(sc, THT_REG_10G_FRM_LEN, MCLBYTES - ETHER_ALIGN);
tht_write(sc, THT_REG_10G_PAUSE, 0x96);
tht_write(sc, THT_REG_10G_RX_SEC, THT_REG_10G_SEC_AVAIL(0x10) |
THT_REG_10G_SEC_EMPTY(0x80));
tht_write(sc, THT_REG_10G_TX_SEC, THT_REG_10G_SEC_AVAIL(0x10) |
THT_REG_10G_SEC_EMPTY(0xe0));
tht_write(sc, THT_REG_10G_RFIFO_AEF, THT_REG_10G_FIFO_AE(0x0) |
THT_REG_10G_FIFO_AF(0x0));
tht_write(sc, THT_REG_10G_TFIFO_AEF, THT_REG_10G_FIFO_AE(0x0) |
THT_REG_10G_FIFO_AF(0x0));
tht_write(sc, THT_REG_10G_CTL, THT_REG_10G_CTL_TX_EN |
THT_REG_10G_CTL_RX_EN | THT_REG_10G_CTL_PAD |
THT_REG_10G_CTL_PROMISC);
tht_write(sc, THT_REG_VGLB, 0);
tht_write(sc, THT_REG_RX_MAX_FRAME, MCLBYTES - ETHER_ALIGN);
tht_write(sc, THT_REG_RDINTCM(0), THT_REG_RDINTCM_PKT_TH(12) |
THT_REG_RDINTCM_RXF_TH(4) | THT_REG_RDINTCM_COAL_RC |
THT_REG_RDINTCM_COAL(0x20));
tht_write(sc, THT_REG_TDINTCM(0), THT_REG_TDINTCM_PKT_TH(12) |
THT_REG_TDINTCM_COAL_RC | THT_REG_TDINTCM_COAL(0x20));
bcopy(sc->sc_ac.ac_enaddr, sc->sc_lladdr, ETHER_ADDR_LEN);
tht_lladdr_write(sc);
  986         /* populate rxf fifo */
tht_rxf_fill(sc, 1);
tht_iff(sc);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
  994         /* enable interrupts */
sc->sc_imr = THT_IMR_UP(sc->sc_port);
tht_write(sc, THT_REG_IMR, sc->sc_imr);
  998         return;
free_rxd:
tht_fifo_free(sc, &sc->sc_rxd);
free_rxf:
tht_fifo_free(sc, &sc->sc_rxf);
free_txt:
tht_fifo_free(sc, &sc->sc_txt);
tht_sw_reset(sc);
free_rx_list:
tht_pkt_free(sc, &sc->sc_rx_list);
free_tx_list:
tht_pkt_free(sc, &sc->sc_tx_list);
 1013 }
 1015 void
tht_iff(struct tht_softc *sc)
 1017 {
 1018         struct ifnet                    *ifp = &sc->sc_ac.ac_if;
 1019         struct ether_multi              *enm;
 1020         struct ether_multistep          step;
u_int32_t                       rxf;
u_int8_t                        imf[THT_REG_RX_MCST_HASH_SIZE];
u_int8_t                        hash;
 1024         int                             i;
ifp->if_flags &= ~IFF_ALLMULTI;
rxf = THT_REG_RX_FLT_OSEN | THT_REG_RX_FLT_AM | THT_REG_RX_FLT_AB;
 1029         for (i = 0; i < THT_REG_RX_MAC_MCST_CNT; i++) {
tht_write(sc, THT_REG_RX_MAC_MCST0(i), 0);
tht_write(sc, THT_REG_RX_MAC_MCST1(i), 0);
 1032         }
memset(imf, 0x00, sizeof(imf));
 1035         if (ifp->if_flags & IFF_PROMISC)
rxf |= THT_REG_RX_FLT_PRM_ALL;
 1037         else if (sc->sc_ac.ac_multirangecnt > 0) {
ifp->if_flags |= IFF_ALLMULTI;
memset(imf, 0xff, sizeof(imf));
 1040         } else {
ETHER_FIRST_MULTI(step, &sc->sc_ac, enm);
 1043 #if 0
 1044                 /* fill the perfect multicast filters */
 1045                 for (i = 0; i < THT_REG_RX_MAC_MCST_CNT; i++) {
 1046                         if (enm == NULL)
 1047                                 break;
tht_write(sc, THT_REG_RX_MAC_MCST0(i),
 1050                             (enm->enm_addrlo[0] << 0) |
 1051                             (enm->enm_addrlo[1] << 8) |
 1052                             (enm->enm_addrlo[2] << 16) |
 1053                             (enm->enm_addrlo[3] << 24));
tht_write(sc, THT_REG_RX_MAC_MCST1(i),
 1055                             (enm->enm_addrlo[4] << 0) |
 1056                             (enm->enm_addrlo[5] << 8));
ETHER_NEXT_MULTI(step, enm);
 1059                 }
 1060 #endif
 1062                 /* fill the imperfect multicast filter with whats left */
 1063                 while (enm != NULL) {
hash = 0x00;
 1065                         for (i = 0; i < ETHER_ADDR_LEN; i++)
hash ^= enm->enm_addrlo[i];
setbit(imf, hash);
ETHER_NEXT_MULTI(step, enm);
 1070                 }
 1071         }
tht_write_region(sc, THT_REG_RX_MCST_HASH, imf, sizeof(imf));
tht_write(sc, THT_REG_RX_FLT, rxf);
 1075 }
 1077 void
tht_down(struct tht_softc *sc)
 1079 {
 1080         struct ifnet                    *ifp = &sc->sc_ac.ac_if;
 1082         if (!ISSET(ifp->if_flags, IFF_RUNNING)) {
printf("%s: interface is already down\n", DEVNAME(sc));
 1084                 return;
 1085         }
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE | IFF_ALLMULTI);
 1089         while (tht_fifo_writable(sc, &sc->sc_txt) < sc->sc_txt.tf_len &&
tht_fifo_readable(sc, &sc->sc_txf) > 0)
tsleep(sc, 0, "thtdown", hz);
sc->sc_imr = THT_IMR_DOWN(sc->sc_port);
tht_write(sc, THT_REG_IMR, sc->sc_imr);
tht_sw_reset(sc);
tht_fifo_free(sc, &sc->sc_txf);
tht_fifo_free(sc, &sc->sc_rxd);
tht_fifo_free(sc, &sc->sc_rxf);
tht_fifo_free(sc, &sc->sc_txt);
 1103         /* free mbufs that were on the rxf fifo */
tht_rxf_drain(sc);
tht_pkt_free(sc, &sc->sc_rx_list);
tht_pkt_free(sc, &sc->sc_tx_list);
 1108 }
 1110 void
tht_start(struct ifnet *ifp)
 1112 {
 1113         struct tht_softc                *sc = ifp->if_softc;
 1114         struct tht_pkt                  *pkt;
 1115         struct tht_tx_task              txt;
u_int32_t                       flags;
 1117         struct mbuf                     *m;
 1118         int                             bc;
 1120         if (!(ifp->if_flags & IFF_RUNNING))
 1121                 return;
 1122         if (ifp->if_flags & IFF_OACTIVE)
 1123                 return;
 1124         if (IFQ_IS_EMPTY(&ifp->if_snd))
 1125                 return;
 1127         if (tht_fifo_writable(sc, &sc->sc_txt) <= THT_FIFO_DESC_LEN)
 1128                 return;
bzero(&txt, sizeof(txt));
tht_fifo_pre(sc, &sc->sc_txt);
 1134         do {
IFQ_POLL(&ifp->if_snd, m);
 1136                 if (m == NULL)
 1137                         break;
pkt = tht_pkt_get(&sc->sc_tx_list);
 1140                 if (pkt == NULL) {
ifp->if_flags |= IFF_OACTIVE;
 1142                         break;
 1143                 }
IFQ_DEQUEUE(&ifp->if_snd, m);
 1146                 if (tht_load_pkt(sc, pkt, m) != 0) {
m_freem(m);
tht_pkt_put(&sc->sc_tx_list, pkt);
ifp->if_oerrors++;
 1150                         break;
 1151                 }
 1152                 /* thou shalt not use m after this point, only pkt->tp_m */
 1154 #if NBPFILTER > 0
 1155                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, pkt->tp_m, BPF_DIRECTION_OUT);
 1157 #endif
bc = sizeof(txt) +
 1160                     sizeof(struct tht_pbd) * pkt->tp_dmap->dm_nsegs;
flags = THT_TXT_TYPE | THT_TXT_FLAGS_UDPCS |
THT_TXT_FLAGS_TCPCS | THT_TXT_FLAGS_IPCS | LWORDS(bc);
txt.flags = htole32(flags);
txt.len = htole16(pkt->tp_m->m_pkthdr.len);
txt.uid = pkt->tp_id;
DPRINTF(THT_D_TX, "%s: txt uid 0x%llx flags 0x%08x len %d\n",
DEVNAME(sc), pkt->tp_id, flags, pkt->tp_m->m_pkthdr.len);
tht_fifo_write(sc, &sc->sc_txt, &txt, sizeof(txt));
tht_fifo_write_dmap(sc, &sc->sc_txt, pkt->tp_dmap);
tht_fifo_write_pad(sc, &sc->sc_txt, bc);
bus_dmamap_sync(sc->sc_thtc->sc_dmat, pkt->tp_dmap, 0,
pkt->tp_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE);
ifp->if_opackets++;
 1180         } while (sc->sc_txt.tf_ready > THT_FIFO_DESC_LEN);
tht_fifo_post(sc, &sc->sc_txt);
 1183 }
 1185 int
tht_load_pkt(struct tht_softc *sc, struct tht_pkt *pkt, struct mbuf *m)
 1187 {
bus_dma_tag_t                   dmat = sc->sc_thtc->sc_dmat;
bus_dmamap_t                    dmap = pkt->tp_dmap;
 1190         struct mbuf                     *m0 = NULL;
 1192         switch(bus_dmamap_load_mbuf(dmat, dmap, m, BUS_DMA_NOWAIT)) {
 1193         case 0:
pkt->tp_m = m;
 1195                 break;
 1197         case EFBIG: /* mbuf chain is too fragmented */
MGETHDR(m0, M_DONTWAIT, MT_DATA);
 1199                 if (m0 == NULL)
 1200                         return (ENOBUFS);
 1201                 if (m->m_pkthdr.len > MHLEN) {
MCLGET(m0, M_DONTWAIT);
 1203                         if (!(m0->m_flags & M_EXT)) {
m_freem(m0);
 1205                                 return (ENOBUFS);
 1206                         }
 1207                 }
m_copydata(m, 0, m->m_pkthdr.len, mtod(m0, caddr_t));
m0->m_pkthdr.len = m0->m_len = m->m_pkthdr.len;
 1210                 if (bus_dmamap_load_mbuf(dmat, dmap, m0, BUS_DMA_NOWAIT)) {
m_freem(m0);
 1212                         return (ENOBUFS);
 1213                 }
m_freem(m);
pkt->tp_m = m0;
 1217                 break;
 1219         default:
 1220                 return (ENOBUFS);
 1221         }
 1223         return (0);
 1224 }
 1226 void
tht_txf(struct tht_softc *sc)
 1228 {
 1229         struct ifnet                    *ifp = &sc->sc_ac.ac_if;
bus_dma_tag_t                   dmat = sc->sc_thtc->sc_dmat;
bus_dmamap_t                    dmap;
 1232         struct tht_tx_free              txf;
 1233         struct tht_pkt                  *pkt;
 1235         if (tht_fifo_readable(sc, &sc->sc_txf) < sizeof(txf))
 1236                 return;
tht_fifo_pre(sc, &sc->sc_txf);
 1240         do {
tht_fifo_read(sc, &sc->sc_txf, &txf, sizeof(txf));
DPRINTF(THT_D_TX, "%s: txf uid 0x%llx\n", DEVNAME(sc), txf.uid);
pkt = &sc->sc_tx_list.tpl_pkts[txf.uid];
dmap = pkt->tp_dmap;
bus_dmamap_sync(dmat, dmap, 0, dmap->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(dmat, dmap);
m_freem(pkt->tp_m);
tht_pkt_put(&sc->sc_tx_list, pkt);
 1256         } while (sc->sc_txf.tf_ready >= sizeof(txf));
ifp->if_flags &= ~IFF_OACTIVE;
tht_fifo_post(sc, &sc->sc_txf);
 1261 }
 1263 void
tht_rxf_fill(struct tht_softc *sc, int wait)
 1265 {
bus_dma_tag_t                   dmat = sc->sc_thtc->sc_dmat;
bus_dmamap_t                    dmap;
 1268         struct tht_rx_free              rxf;
 1269         struct tht_pkt                  *pkt;
 1270         struct mbuf                     *m;
 1271         int                             bc;
 1273         if (tht_fifo_writable(sc, &sc->sc_rxf) <= THT_FIFO_DESC_LEN)
 1274                 return;
tht_fifo_pre(sc, &sc->sc_rxf);
 1278         for (;;) {
 1279                 if ((pkt = tht_pkt_get(&sc->sc_rx_list)) == NULL)
 1280                         goto done;
MGETHDR(m, wait ? M_WAIT : M_DONTWAIT, MT_DATA);
 1283                 if (m == NULL)
 1284                         goto put_pkt;
MCLGET(m, wait ? M_WAIT : M_DONTWAIT);
 1287                 if (!ISSET(m->m_flags, M_EXT))
 1288                         goto free_m;
m->m_data += ETHER_ALIGN;
m->m_len = m->m_pkthdr.len = MCLBYTES - ETHER_ALIGN;
dmap = pkt->tp_dmap;
 1294                 if (bus_dmamap_load_mbuf(dmat, dmap, m,
wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT) != 0)
 1296                         goto free_m;
pkt->tp_m = m;
bc = sizeof(rxf) + sizeof(struct tht_pbd) * dmap->dm_nsegs;
rxf.bc = htole16(LWORDS(bc));
rxf.type = htole16(THT_RXF_TYPE);
rxf.uid = pkt->tp_id;
tht_fifo_write(sc, &sc->sc_rxf, &rxf, sizeof(rxf));
tht_fifo_write_dmap(sc, &sc->sc_rxf, dmap);
tht_fifo_write_pad(sc, &sc->sc_rxf, bc);
bus_dmamap_sync(dmat, dmap, 0, dmap->dm_mapsize,
BUS_DMASYNC_PREREAD);
 1313                 if (sc->sc_rxf.tf_ready <= THT_FIFO_DESC_LEN)
 1314                         goto done;
 1315         }
free_m:
m_freem(m);
put_pkt:
tht_pkt_put(&sc->sc_rx_list, pkt);
done:
tht_fifo_post(sc, &sc->sc_rxf);
 1323 }
 1325 void
tht_rxf_drain(struct tht_softc *sc)
 1327 {
bus_dma_tag_t                   dmat = sc->sc_thtc->sc_dmat;
bus_dmamap_t                    dmap;
 1330         struct tht_pkt                  *pkt;
 1332         while ((pkt = tht_pkt_used(&sc->sc_rx_list)) != NULL) {
dmap = pkt->tp_dmap;
bus_dmamap_sync(dmat, dmap, 0, dmap->dm_mapsize,
BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(dmat, dmap);
m_freem(pkt->tp_m);
tht_pkt_put(&sc->sc_rx_list, pkt);
 1342         }
 1343 }
 1345 void
tht_rxd(struct tht_softc *sc)
 1347 {
 1348         struct ifnet                    *ifp = &sc->sc_ac.ac_if;
bus_dma_tag_t                   dmat = sc->sc_thtc->sc_dmat;
bus_dmamap_t                    dmap;
 1351         struct tht_rx_desc              rxd;
 1352         struct tht_pkt                  *pkt;
 1353         struct mbuf                     *m;
 1354         int                             bc;
u_int32_t                       flags;
 1357         if (tht_fifo_readable(sc, &sc->sc_rxd) < sizeof(rxd))
 1358                 return;
tht_fifo_pre(sc, &sc->sc_rxd);
 1362         do {
tht_fifo_read(sc, &sc->sc_rxd, &rxd, sizeof(rxd));
flags = letoh32(rxd.flags);
bc = THT_RXD_FLAGS_BC(flags) * 8;
bc -= sizeof(rxd);
pkt = &sc->sc_rx_list.tpl_pkts[rxd.uid];
dmap = pkt->tp_dmap;
bus_dmamap_sync(dmat, dmap, 0, dmap->dm_mapsize,
BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(dmat, dmap);
m = pkt->tp_m;
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = m->m_len = letoh16(rxd.len);
 1380                 if (!ISSET(flags, THT_RXD_FLAGS_IPCS))
m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK;
 1382                 if (!ISSET(flags, THT_RXD_FLAGS_TCPCS))
m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK;
 1384                 if (!ISSET(flags, THT_RXD_FLAGS_UDPCS))
m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK;
 1387                 /* XXX process type 3 rx descriptors */
 1389 #if NBPFILTER > 0
 1390                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
 1392 #endif
ether_input_mbuf(ifp, m);
tht_pkt_put(&sc->sc_rx_list, pkt);
 1398                 while (bc > 0) {
 1399                         static u_int32_t pad;
tht_fifo_read(sc, &sc->sc_rxd, &pad, sizeof(pad));
bc -= sizeof(pad);
 1403                 }
ifp->if_ipackets++;
 1407         } while (sc->sc_rxd.tf_ready >= sizeof(rxd));
tht_fifo_post(sc, &sc->sc_rxd);
 1411         /* put more pkts on the fifo */
tht_rxf_fill(sc, 0);
 1413 }
 1415 void
tht_watchdog(struct ifnet *ifp)
 1417 {
 1418         /* do nothing */
 1419 }
 1421 int
tht_media_change(struct ifnet *ifp)
 1423 {
 1424         /* ignore */
 1425         return (0);
 1426 }
 1428 void
tht_media_status(struct ifnet *ifp, struct ifmediareq *imr)
 1430 {
 1431         struct tht_softc                *sc = ifp->if_softc;
imr->ifm_active = IFM_ETHER | IFM_AUTO;
imr->ifm_status = IFM_AVALID;
tht_link_state(sc);
 1438         if (LINK_STATE_IS_UP(ifp->if_link_state))
imr->ifm_status |= IFM_ACTIVE;
 1440 }
 1442 int
tht_fifo_alloc(struct tht_softc *sc, struct tht_fifo *tf,
 1444     struct tht_fifo_desc *tfd)
 1445 {
u_int64_t                       dva;
tf->tf_len = THT_FIFO_SIZE(tfd->tfd_size);
tf->tf_mem = tht_dmamem_alloc(sc, tf->tf_len, THT_FIFO_ALIGN);
 1450         if (tf->tf_mem == NULL)
 1451                 return (1);
tf->tf_desc = tfd;
tf->tf_rptr = tf->tf_wptr = 0;
bus_dmamap_sync(sc->sc_thtc->sc_dmat, THT_DMA_MAP(tf->tf_mem),
 1457             0, tf->tf_len, THT_FIFO_PRE_SYNC(tfd));
dva = THT_DMA_DVA(tf->tf_mem);
tht_write(sc, tfd->tfd_cfg0, (u_int32_t)dva | tfd->tfd_size);
tht_write(sc, tfd->tfd_cfg1, (u_int32_t)(dva >> 32));
 1463         return (0);
 1464 }
 1466 void
tht_fifo_free(struct tht_softc *sc, struct tht_fifo *tf)
 1468 {
bus_dmamap_sync(sc->sc_thtc->sc_dmat, THT_DMA_MAP(tf->tf_mem),
 1470             0, tf->tf_len, THT_FIFO_POST_SYNC(tf->tf_desc));
tht_dmamem_free(sc, tf->tf_mem);
 1472 }
size_t
tht_fifo_readable(struct tht_softc *sc, struct tht_fifo *tf)
 1476 {
tf->tf_wptr = tht_read(sc, tf->tf_desc->tfd_wptr);
tf->tf_wptr &= THT_FIFO_PTR_MASK;
tf->tf_ready = tf->tf_wptr - tf->tf_rptr;
 1480         if (tf->tf_ready < 0)
tf->tf_ready += tf->tf_len;
DPRINTF(THT_D_FIFO, "%s: fifo rdable wptr: %d rptr: %d ready: %d\n",
DEVNAME(sc), tf->tf_wptr, tf->tf_rptr, tf->tf_ready);
 1486         return (tf->tf_ready);
 1487 }
size_t
tht_fifo_writable(struct tht_softc *sc, struct tht_fifo *tf)
 1491 {
tf->tf_rptr = tht_read(sc, tf->tf_desc->tfd_rptr);
tf->tf_rptr &= THT_FIFO_PTR_MASK;
tf->tf_ready = tf->tf_rptr - tf->tf_wptr;
 1495         if (tf->tf_ready <= 0)
tf->tf_ready += tf->tf_len;
DPRINTF(THT_D_FIFO, "%s: fifo wrable wptr: %d rptr: %d ready: %d\n",
DEVNAME(sc), tf->tf_wptr, tf->tf_rptr, tf->tf_ready);
 1501         return (tf->tf_ready);
 1502 }
 1504 void
tht_fifo_pre(struct tht_softc *sc, struct tht_fifo *tf)
 1506 {
bus_dmamap_sync(sc->sc_thtc->sc_dmat, THT_DMA_MAP(tf->tf_mem),
 1508             0, tf->tf_len, THT_FIFO_POST_SYNC(tf->tf_desc));
 1509 }
 1511 void
tht_fifo_read(struct tht_softc *sc, struct tht_fifo *tf,
 1513     void *buf, size_t buflen)
 1514 {
u_int8_t                        *fifo = THT_DMA_KVA(tf->tf_mem);
u_int8_t                        *desc = buf;
size_t                          len;
tf->tf_ready -= buflen;
len = tf->tf_len - tf->tf_rptr;
 1523         if (len < buflen) {
memcpy(desc, fifo + tf->tf_rptr, len);
buflen -= len;
desc += len;
tf->tf_rptr = 0;
 1530         }
memcpy(desc, fifo + tf->tf_rptr, buflen);
tf->tf_rptr += buflen;
DPRINTF(THT_D_FIFO, "%s: fifo rd wptr: %d rptr: %d ready: %d\n",
DEVNAME(sc), tf->tf_wptr, tf->tf_rptr, tf->tf_ready);
 1537 }
 1539 void
tht_fifo_write(struct tht_softc *sc, struct tht_fifo *tf,
 1541     void *buf, size_t buflen)
 1542 {
u_int8_t                        *fifo = THT_DMA_KVA(tf->tf_mem);
u_int8_t                        *desc = buf;
size_t                          len;
tf->tf_ready -= buflen;
len = tf->tf_len - tf->tf_wptr;
 1551         if (len < buflen) {
memcpy(fifo + tf->tf_wptr, desc, len);
buflen -= len;
desc += len;
tf->tf_wptr = 0;
 1558         }
memcpy(fifo + tf->tf_wptr, desc, buflen);
tf->tf_wptr += buflen;
tf->tf_wptr %= tf->tf_len;
DPRINTF(THT_D_FIFO, "%s: fifo wr wptr: %d rptr: %d ready: %d\n",
DEVNAME(sc), tf->tf_wptr, tf->tf_rptr, tf->tf_ready);
 1566 }
 1568 void
tht_fifo_write_dmap(struct tht_softc *sc, struct tht_fifo *tf,
bus_dmamap_t dmap)
 1571 {
 1572         struct tht_pbd                  pbd;
u_int64_t                       dva;
 1574         int                             i;
 1576         for (i = 0; i < dmap->dm_nsegs; i++) {
dva = dmap->dm_segs[i].ds_addr;
pbd.addr_lo = htole32(dva);
pbd.addr_hi = htole32(dva >> 32);
pbd.len = htole32(dmap->dm_segs[i].ds_len);
tht_fifo_write(sc, tf, &pbd, sizeof(pbd));
 1584         }
 1585 }
 1587 void
tht_fifo_write_pad(struct tht_softc *sc, struct tht_fifo *tf, int bc)
 1589 {
 1590         const static u_int32_t pad = 0x0;
 1592         /* this assumes you'll only ever be writing multiples of 4 bytes */
 1593         if (bc % 8)
tht_fifo_write(sc, tf, (void *)&pad, sizeof(pad));
 1595 }
 1597 void
tht_fifo_post(struct tht_softc *sc, struct tht_fifo *tf)
 1599 {
bus_dmamap_sync(sc->sc_thtc->sc_dmat, THT_DMA_MAP(tf->tf_mem),
 1601             0, tf->tf_len, THT_FIFO_PRE_SYNC(tf->tf_desc));
 1602         if (tf->tf_desc->tfd_write)
tht_write(sc, tf->tf_desc->tfd_wptr, tf->tf_wptr);
 1604         else
tht_write(sc, tf->tf_desc->tfd_rptr, tf->tf_rptr);
DPRINTF(THT_D_FIFO, "%s: fifo post wptr: %d rptr: %d\n", DEVNAME(sc),
tf->tf_wptr, tf->tf_rptr);
 1609 }
 1611 const static bus_size_t tht_mac_regs[3] = {
THT_REG_RX_UNC_MAC2, THT_REG_RX_UNC_MAC1, THT_REG_RX_UNC_MAC0
 1613 };
 1615 void
tht_lladdr_read(struct tht_softc *sc)
 1617 {
 1618         int                             i;
 1620         for (i = 0; i < sizeofa(tht_mac_regs); i++)
sc->sc_lladdr[i] = betoh16(tht_read(sc, tht_mac_regs[i]));
 1622 }
 1624 void
tht_lladdr_write(struct tht_softc *sc)
 1626 {
 1627         int                             i;
 1629         for (i = 0; i < sizeofa(tht_mac_regs); i++)
tht_write(sc, tht_mac_regs[i], htobe16(sc->sc_lladdr[i]));
 1631 }
 1633 #define tht_swrst_set(_s, _r) tht_write((_s), (_r), 0x1)
 1634 #define tht_swrst_clr(_s, _r) tht_write((_s), (_r), 0x0)
 1635 int
tht_sw_reset(struct tht_softc *sc)
 1637 {
 1638         int                             i;
 1640         /* this follows SW Reset process in 8.8 of the doco */
 1642         /* 1. disable rx */
tht_clr(sc, THT_REG_RX_FLT, THT_REG_RX_FLT_OSEN);
 1645         /* 2. initiate port disable */
tht_swrst_set(sc, THT_REG_DIS_PRT);
 1648         /* 3. initiate queue disable */
tht_swrst_set(sc, THT_REG_DIS_QU_0);
tht_swrst_set(sc, THT_REG_DIS_QU_1);
 1652         /* 4. wait for successful finish of previous tasks */
 1653         if (!tht_wait_set(sc, THT_REG_RST_PRT, THT_REG_RST_PRT_ACTIVE, 1000))
 1654                 return (1);
 1656         /* 5. Reset interrupt registers */
tht_write(sc, THT_REG_IMR, 0x0); /* 5.a */
tht_read(sc, THT_REG_ISR); /* 5.b */
 1659         for (i = 0; i < THT_NQUEUES; i++) {
tht_write(sc, THT_REG_RDINTCM(i), 0x0); /* 5.c/5.d */
tht_write(sc, THT_REG_TDINTCM(i), 0x0); /* 5.e */
 1662         }
 1664         /* 6. initiate queue reset */
tht_swrst_set(sc, THT_REG_RST_QU_0);
tht_swrst_set(sc, THT_REG_RST_QU_1);
 1668         /* 7. initiate port reset */
tht_swrst_set(sc, THT_REG_RST_PRT);
 1671         /* 8. clear txt/rxf/rxd/txf read and write ptrs */
 1672         for (i = 0; i < THT_NQUEUES; i++) {
tht_write(sc, THT_REG_TXT_RPTR(i), 0);
tht_write(sc, THT_REG_RXF_RPTR(i), 0);
tht_write(sc, THT_REG_RXD_RPTR(i), 0);
tht_write(sc, THT_REG_TXF_RPTR(i), 0);
tht_write(sc, THT_REG_TXT_WPTR(i), 0);
tht_write(sc, THT_REG_RXF_WPTR(i), 0);
tht_write(sc, THT_REG_RXD_WPTR(i), 0);
tht_write(sc, THT_REG_TXF_WPTR(i), 0);
 1682         }
 1684         /* 9. unset port disable */
tht_swrst_clr(sc, THT_REG_DIS_PRT);
 1687         /* 10. unset queue disable */
tht_swrst_clr(sc, THT_REG_DIS_QU_0);
tht_swrst_clr(sc, THT_REG_DIS_QU_1);
 1691         /* 11. unset queue reset */
tht_swrst_clr(sc, THT_REG_RST_QU_0);
tht_swrst_clr(sc, THT_REG_RST_QU_1);
 1695         /* 12. unset port reset */
tht_swrst_clr(sc, THT_REG_RST_PRT);
 1698         /* 13. enable rx */
tht_set(sc, THT_REG_RX_FLT, THT_REG_RX_FLT_OSEN);
 1701         return (0);
 1702 }
 1704 int
tht_fw_load(struct tht_softc *sc)
 1706 {
 1707         struct timeout                  ticker;
 1708         volatile int                    ok = 1;
u_int8_t                        *fw, *buf;
size_t                          fwlen, wrlen;
 1711         int                             error = 1;
 1713         if (loadfirmware("tht", &fw, &fwlen) != 0)
 1714                 return (1);
 1716         if ((fwlen % 8) != 0)
 1717                 goto err;
buf = fw;
 1720         while (fwlen > 0) {
 1721                 while (tht_fifo_writable(sc, &sc->sc_txt) <= THT_FIFO_GAP) {
 1722                         if (tsleep(sc, PCATCH, "thtfw", 1) == EINTR)
 1723                                 goto err;
 1724                 }
wrlen = MIN(sc->sc_txt.tf_ready - THT_FIFO_GAP, fwlen);
tht_fifo_pre(sc, &sc->sc_txt);
tht_fifo_write(sc, &sc->sc_txt, buf, wrlen);
tht_fifo_post(sc, &sc->sc_txt);
fwlen -= wrlen;
buf += wrlen;
 1733         }
timeout_set(&ticker, tht_fw_tick, &ticker);
timeout_add(&ticker, 2*hz);
 1737         while (ok) {
 1738                 if (tht_read(sc, THT_REG_INIT_STATUS) != 0) {
error = 0;
 1740                         break;
 1741                 }
 1743                 if (tsleep(sc, PCATCH, "thtinit", 1) == EINTR)
 1744                         goto err;
 1745         }
timeout_del(&ticker);
tht_write(sc, THT_REG_INIT_SEMAPHORE, 0x1);
err:
free(fw, M_DEVBUF);
 1752         return (error);
 1753 }
 1755 void
tht_fw_tick(void *arg)
 1757 {
 1758         volatile int                    *ok = arg;
 1760         *ok = 0;
 1761 }
 1763 void
tht_link_state(struct tht_softc *sc)
 1765 {
 1766         struct ifnet                    *ifp = &sc->sc_ac.ac_if;
 1767         int                             link_state = LINK_STATE_DOWN;
 1769         if (tht_read(sc, THT_REG_MAC_LNK_STAT) & THT_REG_MAC_LNK_STAT_LINK)
link_state = LINK_STATE_UP;
 1772         if (ifp->if_link_state != link_state) {
ifp->if_link_state = link_state;
if_link_state_change(ifp);
 1775         }
 1776 }
u_int32_t
tht_read(struct tht_softc *sc, bus_size_t r)
 1780 {
bus_space_barrier(sc->sc_thtc->sc_memt, sc->sc_memh, r, 4,
BUS_SPACE_BARRIER_READ);
 1783         return (bus_space_read_4(sc->sc_thtc->sc_memt, sc->sc_memh, r));
 1784 }
 1786 void
tht_write(struct tht_softc *sc, bus_size_t r, u_int32_t v)
 1788 {
bus_space_write_4(sc->sc_thtc->sc_memt, sc->sc_memh, r, v);
bus_space_barrier(sc->sc_thtc->sc_memt, sc->sc_memh, r, 4,
BUS_SPACE_BARRIER_WRITE);
 1792 }
 1794 void
tht_write_region(struct tht_softc *sc, bus_size_t r, void *buf, size_t len)
 1796 {
bus_space_write_raw_region_4(sc->sc_thtc->sc_memt, sc->sc_memh, r,
buf, len);
bus_space_barrier(sc->sc_thtc->sc_memt, sc->sc_memh, r, len,
BUS_SPACE_BARRIER_WRITE);
 1801 }
 1803 int
tht_wait_eq(struct tht_softc *sc, bus_size_t r, u_int32_t m, u_int32_t v,
 1805     int timeout)
 1806 {
 1807         while ((tht_read(sc, r) & m) != v) {
 1808                 if (timeout == 0)
 1809                         return (0);
delay(1000);
timeout--;
 1813         }
 1815         return (1);
 1816 }
 1818 int
tht_wait_ne(struct tht_softc *sc, bus_size_t r, u_int32_t m, u_int32_t v,
 1820     int timeout)
 1821 {
 1822         while ((tht_read(sc, r) & m) == v) {
 1823                 if (timeout == 0)
 1824                         return (0);
delay(1000);
timeout--;
 1828         }
 1830         return (1);
 1831 }
 1833 struct tht_dmamem *
tht_dmamem_alloc(struct tht_softc *sc, bus_size_t size, bus_size_t align)
 1835 {
bus_dma_tag_t                   dmat = sc->sc_thtc->sc_dmat;
 1837         struct tht_dmamem               *tdm;
 1838         int                             nsegs;
tdm = malloc(sizeof(struct tht_dmamem), M_DEVBUF, M_WAITOK);
bzero(tdm, sizeof(struct tht_dmamem));
tdm->tdm_size = size;
 1844         if (bus_dmamap_create(dmat, size, 1, size, 0,
BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &tdm->tdm_map) != 0)
 1846                 goto tdmfree;
 1848         if (bus_dmamem_alloc(dmat, size, align, 0, &tdm->tdm_seg, 1, &nsegs,
BUS_DMA_WAITOK) != 0)
 1850                 goto destroy;
 1852         if (bus_dmamem_map(dmat, &tdm->tdm_seg, nsegs, size, &tdm->tdm_kva,
BUS_DMA_WAITOK) != 0)
 1854                 goto free;
 1856         if (bus_dmamap_load(dmat, tdm->tdm_map, tdm->tdm_kva, size,
NULL, BUS_DMA_WAITOK) != 0)
 1858                 goto unmap;
bzero(tdm->tdm_kva, size);
 1862         return (tdm);
unmap:
bus_dmamem_unmap(dmat, tdm->tdm_kva, size);
free:
bus_dmamem_free(dmat, &tdm->tdm_seg, 1);
destroy:
bus_dmamap_destroy(dmat, tdm->tdm_map);
tdmfree:
free(tdm, M_DEVBUF);
 1873         return (NULL);
 1874 }
 1876 void
tht_dmamem_free(struct tht_softc *sc, struct tht_dmamem *tdm)
 1878 {
bus_dma_tag_t                   dmat = sc->sc_thtc->sc_dmat;
bus_dmamap_unload(dmat, tdm->tdm_map);
bus_dmamem_unmap(dmat, tdm->tdm_kva, tdm->tdm_size);
bus_dmamem_free(dmat, &tdm->tdm_seg, 1);
bus_dmamap_destroy(dmat, tdm->tdm_map);
free(tdm, M_DEVBUF);
 1886 }
 1888 int
tht_pkt_alloc(struct tht_softc *sc, struct tht_pkt_list *tpl, int npkts,
 1890     int nsegs)
 1891 {
bus_dma_tag_t                   dmat = sc->sc_thtc->sc_dmat;
 1893         struct tht_pkt                  *pkt;
 1894         int                             i;
tpl->tpl_pkts = malloc(sizeof(struct tht_pkt) * npkts, M_DEVBUF,
M_WAITOK);
bzero(tpl->tpl_pkts, sizeof(struct tht_pkt) * npkts);
TAILQ_INIT(&tpl->tpl_free);
TAILQ_INIT(&tpl->tpl_used);
 1902         for (i = 0; i < npkts; i++) {
pkt = &tpl->tpl_pkts[i];
pkt->tp_id = i;
 1906                 if (bus_dmamap_create(dmat, THT_PBD_PKTLEN, nsegs,
THT_PBD_PKTLEN, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
 1908                     &pkt->tp_dmap) != 0) {
tht_pkt_free(sc, tpl);
 1910                         return (1);
 1911                 }
TAILQ_INSERT_TAIL(&tpl->tpl_free, pkt, tp_link);
 1914         }
 1916         return (0);
 1917 }
 1919 void
tht_pkt_free(struct tht_softc *sc, struct tht_pkt_list *tpl)
 1921 {
bus_dma_tag_t                   dmat = sc->sc_thtc->sc_dmat;
 1923         struct tht_pkt                  *pkt;
 1925         while ((pkt = tht_pkt_get(tpl)) != NULL)
bus_dmamap_destroy(dmat, pkt->tp_dmap);
free(tpl->tpl_pkts, M_DEVBUF);
tpl->tpl_pkts = NULL;
 1929 }
 1931 void
tht_pkt_put(struct tht_pkt_list *tpl, struct tht_pkt *pkt)
 1933 {
TAILQ_REMOVE(&tpl->tpl_used, pkt, tp_link);
TAILQ_INSERT_TAIL(&tpl->tpl_free, pkt, tp_link);
 1936 }
 1938 struct tht_pkt *
tht_pkt_get(struct tht_pkt_list *tpl)
 1940 {
 1941         struct tht_pkt                  *pkt;
pkt = TAILQ_FIRST(&tpl->tpl_free);
 1944         if (pkt != NULL) {
TAILQ_REMOVE(&tpl->tpl_free, pkt, tp_link);
TAILQ_INSERT_TAIL(&tpl->tpl_used, pkt, tp_link);
 1948         }
 1950         return (pkt);
 1951 }
 1953 struct tht_pkt *
tht_pkt_used(struct tht_pkt_list *tpl)
 1955 {
 1956         return (TAILQ_FIRST(&tpl->tpl_used));
 1957 }