root/dev/ic/athvar.h

INCLUDED FROM

DEFINITIONS

1. ath_task_t

    1 /*      $OpenBSD: athvar.h,v 1.20 2007/06/06 21:41:32 reyk Exp $  */
    2 /*      $NetBSD: athvar.h,v 1.10 2004/08/10 01:03:53 dyoung Exp $       */
    4 /*-
    5  * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer,
   13  *    without modification.
   14  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
   15  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
   16  *    redistribution must be conditioned upon including a substantially
   17  *    similar Disclaimer requirement for further binary redistribution.
   18  * 3. Neither the names of the above-listed copyright holders nor the names
   19  *    of any contributors may be used to endorse or promote products derived
   20  *    from this software without specific prior written permission.
   21  *
   22  * NO WARRANTY
   23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   24  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   25  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
   26  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
   27  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
   28  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
   31  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   33  * THE POSSIBILITY OF SUCH DAMAGES.
   34  *
   35  * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.14 2004/04/03 03:33:02 sam Exp $
   36  */
   38 /*
   39  * Definitions for the Atheros Wireless LAN controller driver.
   40  */
   41 #ifndef _DEV_ATH_ATHVAR_H
   42 #define _DEV_ATH_ATHVAR_H
   44 #include <net80211/ieee80211_radiotap.h>
   45 #include <dev/ic/ar5xxx.h>
   47 #ifdef notyet
   48 #include "gpio.h"
   49 #endif
   51 #define ATH_TIMEOUT             1000
   53 #define ATH_RXBUF       40              /* number of RX buffers */
   54 #define ATH_TXBUF       60              /* number of TX buffers */
   55 #define ATH_TXDESC      8               /* number of descriptors per buffer */
   56 #define ATH_MAXGPIO     10              /* maximal number of gpio pins */
   58 struct ath_recv_hist {
   59         int             arh_ticks;      /* sample time by system clock */
u_int8_t        arh_rssi;       /* rssi */
u_int8_t        arh_antenna;    /* antenna */
   62 };
   63 #define ATH_RHIST_SIZE          16      /* number of samples */
   64 #define ATH_RHIST_NOTIME        (~0)
   66 /*
   67  * Ioctl-related definitions for the Atheros Wireless LAN controller driver.
   68  */
   69 struct ath_stats {
u_int32_t       ast_watchdog;   /* device reset by watchdog */
u_int32_t       ast_hardware;   /* fatal hardware error interrupts */
u_int32_t       ast_bmiss;      /* beacon miss interrupts */
u_int32_t       ast_mib;        /* MIB counter interrupts */
u_int32_t       ast_rxorn;      /* rx overrun interrupts */
u_int32_t       ast_rxeol;      /* rx eol interrupts */
u_int32_t       ast_txurn;      /* tx underrun interrupts */
u_int32_t       ast_intrcoal;   /* interrupts coalesced */
u_int32_t       ast_tx_mgmt;    /* management frames transmitted */
u_int32_t       ast_tx_discard; /* frames discarded prior to assoc */
u_int32_t       ast_tx_qstop;   /* output stopped 'cuz no buffer */
u_int32_t       ast_tx_encap;   /* tx encapsulation failed */
u_int32_t       ast_tx_nonode;  /* tx failed 'cuz no node */
u_int32_t       ast_tx_nombuf;  /* tx failed 'cuz no mbuf */
u_int32_t       ast_tx_nomcl;   /* tx failed 'cuz no cluster */
u_int32_t       ast_tx_linear;  /* tx linearized to cluster */
u_int32_t       ast_tx_nodata;  /* tx discarded empty frame */
u_int32_t       ast_tx_busdma;  /* tx failed for dma resrcs */
u_int32_t       ast_tx_xretries;/* tx failed 'cuz too many retries */
u_int32_t       ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
u_int32_t       ast_tx_filtered;/* tx failed 'cuz xmit filtered */
u_int32_t       ast_tx_shortretry;/* tx on-chip retries (short) */
u_int32_t       ast_tx_longretry;/* tx on-chip retries (long) */
u_int32_t       ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
u_int32_t       ast_tx_noack;   /* tx frames with no ack marked */
u_int32_t       ast_tx_rts;     /* tx frames with rts enabled */
u_int32_t       ast_tx_cts;     /* tx frames with cts enabled */
u_int32_t       ast_tx_shortpre;/* tx frames with short preamble */
u_int32_t       ast_tx_altrate; /* tx frames with alternate rate */
u_int32_t       ast_tx_protect; /* tx frames with protection */
u_int32_t       ast_rx_nombuf;  /* rx setup failed 'cuz no mbuf */
u_int32_t       ast_rx_busdma;  /* rx setup failed for dma resrcs */
u_int32_t       ast_rx_orn;     /* rx failed 'cuz of desc overrun */
u_int32_t       ast_rx_crcerr;  /* rx failed 'cuz of bad CRC */
u_int32_t       ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
u_int32_t       ast_rx_badcrypt;/* rx failed 'cuz decryption */
u_int32_t       ast_rx_phyerr;  /* rx failed 'cuz of PHY err */
u_int32_t       ast_rx_phy[32]; /* rx PHY error per-code counts */
u_int32_t       ast_rx_tooshort;/* rx discarded 'cuz frame too short */
u_int32_t       ast_rx_toobig;  /* rx discarded 'cuz frame too large */
u_int32_t       ast_rx_ctl;     /* rx discarded 'cuz ctl frame */
u_int32_t       ast_be_nombuf;  /* beacon setup failed 'cuz no mbuf */
u_int32_t       ast_per_cal;    /* periodic calibration calls */
u_int32_t       ast_per_calfail;/* periodic calibration failed */
u_int32_t       ast_per_rfgain; /* periodic calibration rfgain reset */
u_int32_t       ast_rate_calls; /* rate control checks */
u_int32_t       ast_rate_raise; /* rate control raised xmit rate */
u_int32_t       ast_rate_drop;  /* rate control dropped xmit rate */
  118 };
  120 #define SIOCGATHSTATS   _IOWR('i', 137, struct ifreq)
  122 /*
  123  * Radio capture format.
  124  */
  125 #define ATH_RX_RADIOTAP_PRESENT (               \
  126         (1 << IEEE80211_RADIOTAP_FLAGS)         | \
  127         (1 << IEEE80211_RADIOTAP_RATE)          | \
  128         (1 << IEEE80211_RADIOTAP_CHANNEL)       | \
  129         (1 << IEEE80211_RADIOTAP_ANTENNA)       | \
  130         (1 << IEEE80211_RADIOTAP_RSSI)          | \
  131         0)
  133 struct ath_rx_radiotap_header {
  134         struct ieee80211_radiotap_header wr_ihdr;
u_int8_t        wr_flags;
u_int8_t        wr_rate;
u_int16_t       wr_chan_freq;
u_int16_t       wr_chan_flags;
u_int8_t        wr_antenna;
u_int8_t        wr_rssi;
u_int8_t        wr_max_rssi;
  142 } __packed;
  144 #define ATH_TX_RADIOTAP_PRESENT (               \
  145         (1 << IEEE80211_RADIOTAP_FLAGS)         | \
  146         (1 << IEEE80211_RADIOTAP_RATE)          | \
  147         (1 << IEEE80211_RADIOTAP_CHANNEL)       | \
  148         (1 << IEEE80211_RADIOTAP_DBM_TX_POWER)  | \
  149         (1 << IEEE80211_RADIOTAP_ANTENNA)       | \
  150         (1 << IEEE80211_RADIOTAP_HWQUEUE)       | \
  151         0)
  153 struct ath_tx_radiotap_header {
  154         struct ieee80211_radiotap_header wt_ihdr;
u_int8_t        wt_flags;
u_int8_t        wt_rate;
u_int16_t       wt_chan_freq;
u_int16_t       wt_chan_flags;
u_int8_t        wt_txpower;
u_int8_t        wt_antenna;
u_int8_t        wt_hwqueue;
  162 } __packed;
  164 /* 
  165  * driver-specific node 
  166  */
  167 struct ath_node {
  168         struct ieee80211_node           an_node;        /* base class */
  169         struct ieee80211_rssadapt       an_rssadapt;    /* rate adaption */
u_int                           an_tx_antenna;  /* antenna for last good frame */
u_int                           an_rx_antenna;  /* antenna for last rcvd frame */
  172         struct ath_recv_hist            an_rx_hist[ATH_RHIST_SIZE];
u_int                           an_rx_hist_next;/* index of next ``free entry'' */
  174 };
  175 #define ATH_NODE(_n)    ((struct ath_node *)(_n))
  177 struct ath_buf {
TAILQ_ENTRY(ath_buf)            bf_list;
bus_dmamap_t                    bf_dmamap;      /* DMA map of the buffer */
  180 #define bf_nseg                         bf_dmamap->dm_nsegs
  181 #define bf_mapsize                      bf_dmamap->dm_mapsize
  182 #define bf_segs                         bf_dmamap->dm_segs
  183         struct ath_desc                 *bf_desc;       /* virtual addr of desc */
bus_addr_t                      bf_daddr;       /* physical addr of desc */
  185         struct mbuf                     *bf_m;          /* mbuf for buf */
  186         struct ieee80211_node           *bf_node;       /* pointer to the node */
  187         struct ieee80211_rssdesc        bf_id;
  188 #define ATH_MAX_SCATTER                 64
  189 };
  191 typedef struct ath_task {
  192         void    (*t_func)(void*, int);
  193         void    *t_context;
  194 } ath_task_t;
  196 struct ath_softc {
  197 #ifndef __FreeBSD__
  198         struct device           sc_dev;
  199 #endif
  200         struct ieee80211com     sc_ic;          /* IEEE 802.11 common */
  201 #ifndef __FreeBSD__
  202         int                     (*sc_enable)(struct ath_softc *);
  203         void                    (*sc_disable)(struct ath_softc *);
  204         void                    (*sc_power)(struct ath_softc *, int);
  205 #endif
  206         int                     (*sc_newstate)(struct ieee80211com *,
  207                                         enum ieee80211_state, int);
  208         void                    (*sc_node_free)(struct ieee80211com *,
  209                                         struct ieee80211_node *);
  210         void                    (*sc_node_copy)(struct ieee80211com *,
  211                                         struct ieee80211_node *,
  212                                         const struct ieee80211_node *);
  213         void                    (*sc_recv_mgmt)(struct ieee80211com *,
  214                                     struct mbuf *, struct ieee80211_node *,
  215                                     int, int, u_int32_t);
  216 #ifdef __FreeBSD__
device_t                sc_dev;
  218 #endif
bus_space_tag_t         sc_st;          /* bus space tag */
bus_space_handle_t      sc_sh;          /* bus space handle */
bus_dma_tag_t           sc_dmat;        /* bus DMA tag */
  222 #ifdef __FreeBSD__
  223         struct mtx              sc_mtx;         /* master lock (recursive) */
  224 #endif
  225         struct ath_hal          *sc_ah;         /* Atheros HAL */
  226         unsigned int            sc_invalid : 1, /* disable hardware accesses */
sc_doani : 1,   /* dynamic noise immunity */
sc_veol : 1,    /* tx VEOL support */
sc_softled : 1, /* GPIO software LED */
sc_probing : 1, /* probing AP on beacon miss */
sc_64bit : 1;   /* indicates PCI Express */
u_int                   sc_nchan;       /* number of valid channels */
  233         const HAL_RATE_TABLE    *sc_rates[IEEE80211_MODE_MAX];
  234         const HAL_RATE_TABLE    *sc_currates;   /* current rate table */
  235         enum ieee80211_phymode  sc_curmode;     /* current phy mode */
u_int8_t                sc_rixmap[256]; /* IEEE to h/w rate table ix */
u_int8_t                sc_hwmap[32];   /* h/w rate ix to IEEE table */
HAL_INT                 sc_imask;       /* interrupt mask copy */
  240 #if NBPFILTER > 0
caddr_t                 sc_drvbpf;
  243         union {
  244                 struct ath_rx_radiotap_header   th;
uint8_t                         pad[IEEE80211_RADIOTAP_HDRLEN];
  246         }                       sc_rxtapu;
  247 #define sc_rxtap                sc_rxtapu.th
  248         int                     sc_rxtap_len;
  250         union {
  251                 struct ath_tx_radiotap_header   th;
uint8_t                         pad[IEEE80211_RADIOTAP_HDRLEN];
  253         }                       sc_txtapu;
  254 #define sc_txtap                sc_txtapu.th
  255         int                     sc_txtap_len;
  256 #endif
  258         struct ath_desc         *sc_desc;       /* TX/RX descriptors */
bus_dma_segment_t       sc_dseg;
  260 #ifndef __NetBSD__
  261         int                     sc_dnseg;       /* number of segments */
  262 #endif
bus_dmamap_t            sc_ddmamap;     /* DMA map for descriptors */
bus_addr_t              sc_desc_paddr;  /* physical addr of sc_desc */
bus_addr_t              sc_desc_len;    /* size of sc_desc */
ath_task_t              sc_fataltask;   /* fatal int processing */
ath_task_t              sc_rxorntask;   /* rxorn int processing */
TAILQ_HEAD(, ath_buf)   sc_rxbuf;       /* receive buffer */
u_int32_t               *sc_rxlink;     /* link ptr in last RX desc */
ath_task_t              sc_rxtask;      /* rx int processing */
u_int                   sc_txhalq[HAL_NUM_TX_QUEUES];   /* HAL q for outgoing frames */
u_int32_t               *sc_txlink;     /* link ptr in last TX desc */
  276         int                     sc_tx_timer;    /* transmit timeout */
TAILQ_HEAD(, ath_buf)   sc_txbuf;       /* transmit buffer */
  278 #ifdef __FreeBSD__
  279         struct mtx              sc_txbuflock;   /* txbuf lock */
  280 #endif
TAILQ_HEAD(, ath_buf)   sc_txq;         /* transmitting queue */
  282 #ifdef __FreeBSD__
  283         struct mtx              sc_txqlock;     /* lock on txq and txlink */
  284 #endif
ath_task_t              sc_txtask;      /* tx int processing */
u_int                   sc_bhalq;       /* HAL q for outgoing beacons */
  288         struct ath_buf          *sc_bcbuf;      /* beacon buffer */
  289         struct ath_buf          *sc_bufptr;     /* allocated buffer ptr */
ath_task_t              sc_swbatask;    /* swba int processing */
ath_task_t              sc_bmisstask;   /* bmiss int processing */
  293 #ifdef __OpenBSD__
  294         struct timeval          sc_last_ch;
  295         struct timeout          sc_cal_to;
  296         struct timeval          sc_last_beacon;
  297         struct timeout          sc_scan_to;
  298         struct timeout          sc_rssadapt_to;
  299 #else
  300         struct callout          sc_cal_ch;      /* callout handle for cals */
  301         struct callout          sc_scan_ch;     /* callout handle for scan */
  302 #endif
  303         struct ath_stats        sc_stats;       /* interface statistics */
HAL_MIB_STATS           sc_mib_stats;   /* MIB counter statistics */
  306 #ifndef __FreeBSD__
  307         void                    *sc_sdhook;     /* shutdown hook */
  308         void                    *sc_powerhook;  /* power management hook */
u_int                   sc_flags;       /* misc flags */
  310 #endif
u_int8_t                sc_broadcast_addr[IEEE80211_ADDR_LEN];
  314         struct gpio_chipset_tag sc_gpio_gc;     /* gpio(4) framework */
gpio_pin_t              sc_gpio_pins[ATH_MAXGPIO];
  316 };
  318 /* unaligned little endian access */     
  319 #define LE_READ_2(p)                                                    \
  320         ((u_int16_t)                                                    \
  321          ((((u_int8_t *)(p))[0]      ) | (((u_int8_t *)(p))[1] <<  8)))
  322 #define LE_READ_4(p)                                                    \
  323         ((u_int32_t)                                                    \
  324          ((((u_int8_t *)(p))[0]      ) | (((u_int8_t *)(p))[1] <<  8) | \
  325          (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24)))
  327 #ifdef AR_DEBUG
  328 enum {
ATH_DEBUG_XMIT          = 0x00000001,   /* basic xmit operation */
ATH_DEBUG_XMIT_DESC     = 0x00000002,   /* xmit descriptors */
ATH_DEBUG_RECV          = 0x00000004,   /* basic recv operation */
ATH_DEBUG_RECV_DESC     = 0x00000008,   /* recv descriptors */
ATH_DEBUG_RATE          = 0x00000010,   /* rate control */
ATH_DEBUG_RESET         = 0x00000020,   /* reset processing */
ATH_DEBUG_MODE          = 0x00000040,   /* mode init/setup */
ATH_DEBUG_BEACON        = 0x00000080,   /* beacon handling */
ATH_DEBUG_WATCHDOG      = 0x00000100,   /* watchdog timeout */
ATH_DEBUG_INTR          = 0x00001000,   /* ISR */
ATH_DEBUG_TX_PROC       = 0x00002000,   /* tx ISR proc */
ATH_DEBUG_RX_PROC       = 0x00004000,   /* rx ISR proc */
ATH_DEBUG_BEACON_PROC   = 0x00008000,   /* beacon ISR proc */
ATH_DEBUG_CALIBRATE     = 0x00010000,   /* periodic calibration */
ATH_DEBUG_ANY           = 0xffffffff
  344 };
  345 #define IFF_DUMPPKTS(_ifp, _m) \
  346         ((ath_debug & _m) || \
  347             ((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
  348 #define DPRINTF(_m,X)   if (ath_debug & (_m)) printf X
  349 #else
  350 #define IFF_DUMPPKTS(_ifp, _m) \
  351         (((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
  352 #define DPRINTF(_m, X)
  353 #endif
  355 /*
  356  * Wrapper code
  357  */
  358 #ifndef __FreeBSD__
  359 #undef KASSERT
  360 #define KASSERT(cond, complaint) if (!(cond)) panic complaint
  362 #define ATH_ATTACHED            0x0001          /* attach has succeeded */
  363 #define ATH_ENABLED             0x0002          /* chip is enabled */
  364 #define ATH_GPIO                0x0004          /* gpio device attached */
  366 #define ATH_IS_ENABLED(sc)      ((sc)->sc_flags & ATH_ENABLED)
  367 #endif
  369 #define ATH_LOCK_INIT(_sc) \
mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE)
  372 #define ATH_LOCK_DESTROY(_sc)   mtx_destroy(&(_sc)->sc_mtx)
  373 #define ATH_LOCK(_sc)           mtx_lock(&(_sc)->sc_mtx)
  374 #define ATH_UNLOCK(_sc)         mtx_unlock(&(_sc)->sc_mtx)
  375 #define ATH_LOCK_ASSERT(_sc)    mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
  377 #define ATH_TXBUF_LOCK_INIT(_sc) \
mtx_init(&(_sc)->sc_txbuflock, \
device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF)
  380 #define ATH_TXBUF_LOCK_DESTROY(_sc)     mtx_destroy(&(_sc)->sc_txbuflock)
  381 #define ATH_TXBUF_LOCK(_sc)             mtx_lock(&(_sc)->sc_txbuflock)
  382 #define ATH_TXBUF_UNLOCK(_sc)           mtx_unlock(&(_sc)->sc_txbuflock)
  383 #define ATH_TXBUF_LOCK_ASSERT(_sc) \
mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
  386 #define ATH_TXQ_LOCK_INIT(_sc) \
mtx_init(&(_sc)->sc_txqlock, \
device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF)
  389 #define ATH_TXQ_LOCK_DESTROY(_sc)       mtx_destroy(&(_sc)->sc_txqlock)
  390 #define ATH_TXQ_LOCK(_sc)               mtx_lock(&(_sc)->sc_txqlock)
  391 #define ATH_TXQ_UNLOCK(_sc)             mtx_unlock(&(_sc)->sc_txqlock)
  392 #define ATH_TXQ_LOCK_ASSERT(_sc)        mtx_assert(&(_sc)->sc_txqlock, MA_OWNED)
  394 #define ATH_TICKS() (tick)
  395 #define ATH_CALLOUT_INIT(chp) callout_init((chp))
  396 #define ATH_TASK_INIT(task, func, context)      \
  397         do {                                    \
  398                 (task)->t_func = (func);        \
  399                 (task)->t_context = (context);  \
  400         } while (0)
  401 #define ATH_TASK_RUN_OR_ENQUEUE(task) ((*(task)->t_func)((task)->t_context, 1))
  403 typedef unsigned long u_intptr_t;
  405 int     ath_attach(u_int16_t, struct ath_softc *);
  406 int     ath_detach(struct ath_softc *, int);
  407 int     ath_enable(struct ath_softc *);
  408 void    ath_resume(struct ath_softc *, int);
  409 void    ath_suspend(struct ath_softc *, int);
  410 #ifdef __NetBSD__
  411 int     ath_activate(struct device *, enum devact);
  412 void    ath_power(int, void *);
  413 #endif
  414 void    ath_shutdown(void *);
  415 int     ath_intr(void *);
  416 int     ath_enable(struct ath_softc *);
  418 /*
  419  * HAL definitions to comply with local coding convention.
  420  */
  421 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
  422         ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
  423 #define ath_hal_get_rate_table(_ah, _mode) \
  424         ((*(_ah)->ah_get_rate_table)((_ah), (_mode)))
  425 #define ath_hal_get_lladdr(_ah, _mac) \
  426         ((*(_ah)->ah_get_lladdr)((_ah), (_mac)))
  427 #define ath_hal_set_lladdr(_ah, _mac) \
  428         ((*(_ah)->ah_set_lladdr)((_ah), (_mac)))
  429 #define ath_hal_set_intr(_ah, _mask) \
  430         ((*(_ah)->ah_set_intr)((_ah), (_mask)))
  431 #define ath_hal_get_intr(_ah) \
  432         ((*(_ah)->ah_get_intr)((_ah)))
  433 #define ath_hal_is_intr_pending(_ah) \
  434         ((*(_ah)->ah_is_intr_pending)((_ah)))
  435 #define ath_hal_get_isr(_ah, _pmask) \
  436         ((*(_ah)->ah_get_isr)((_ah), (_pmask)))
  437 #define ath_hal_update_tx_triglevel(_ah, _inc) \
  438         ((*(_ah)->ah_update_tx_triglevel)((_ah), (_inc)))
  439 #define ath_hal_set_power(_ah, _mode, _sleepduration) \
  440         ((*(_ah)->ah_set_power)((_ah), (_mode), AH_TRUE, (_sleepduration)))
  441 #define ath_hal_reset_key(_ah, _ix) \
  442         ((*(_ah)->ah_reset_key)((_ah), (_ix)))
  443 #define ath_hal_set_key(_ah, _ix, _pk) \
  444         ((*(_ah)->ah_set_key)((_ah), (_ix), (_pk), NULL, AH_FALSE))
  445 #define ath_hal_is_key_valid(_ah, _ix) \
  446         (((*(_ah)->ah_is_key_valid)((_ah), (_ix))))
  447 #define ath_hal_set_key_lladdr(_ah, _ix, _mac) \
  448         ((*(_ah)->ah_set_key_lladdr)((_ah), (_ix), (_mac)))
  449 #define ath_hal_get_rx_filter(_ah) \
  450         ((*(_ah)->ah_get_rx_filter)((_ah)))
  451 #define ath_hal_set_rx_filter(_ah, _filter) \
  452         ((*(_ah)->ah_set_rx_filter)((_ah), (_filter)))
  453 #define ath_hal_set_mcast_filter(_ah, _mfilt0, _mfilt1) \
  454         ((*(_ah)->ah_set_mcast_filter)((_ah), (_mfilt0), (_mfilt1)))
  455 #define ath_hal_wait_for_beacon(_ah, _bf) \
  456         ((*(_ah)->ah_wait_for_beacon)((_ah), (_bf)->bf_daddr))
  457 #define ath_hal_put_rx_buf(_ah, _bufaddr) \
  458         ((*(_ah)->ah_put_rx_buf)((_ah), (_bufaddr)))
  459 #define ath_hal_get_tsf32(_ah) \
  460         ((*(_ah)->ah_get_tsf32)((_ah)))
  461 #define ath_hal_get_tsf64(_ah) \
  462         ((*(_ah)->ah_get_tsf64)((_ah)))
  463 #define ath_hal_reset_tsf(_ah) \
  464         ((*(_ah)->ah_reset_tsf)((_ah)))
  465 #define ath_hal_start_rx(_ah) \
  466         ((*(_ah)->ah_start_rx)((_ah)))
  467 #define ath_hal_put_tx_buf(_ah, _q, _bufaddr) \
  468         ((*(_ah)->ah_put_tx_buf)((_ah), (_q), (_bufaddr)))
  469 #define ath_hal_get_tx_buf(_ah, _q) \
  470         ((*(_ah)->ah_get_tx_buf)((_ah), (_q)))
  471 #define ath_hal_get_rx_buf(_ah) \
  472         ((*(_ah)->ah_get_rx_buf)((_ah)))
  473 #define ath_hal_tx_start(_ah, _q) \
  474         ((*(_ah)->ah_tx_start)((_ah), (_q)))
  475 #define ath_hal_setchannel(_ah, _chan) \
  476         ((*(_ah)->ah_setchannel)((_ah), (_chan)))
  477 #define ath_hal_calibrate(_ah, _chan) \
  478         ((*(_ah)->ah_calibrate)((_ah), (_chan)))
  479 #define ath_hal_set_ledstate(_ah, _state) \
  480         ((*(_ah)->ah_set_ledstate)((_ah), (_state)))
  481 #define ath_hal_init_beacon(_ah, _nextb, _bperiod) \
  482         ((*(_ah)->ah_init_beacon)((_ah), (_nextb), (_bperiod)))
  483 #define ath_hal_reset_beacon(_ah) \
  484         ((*(_ah)->ah_reset_beacon)((_ah)))
  485 #define ath_hal_set_beacon_timers(_ah, _bs, _tsf, _dc, _cc) \
  486         ((*(_ah)->ah_set_beacon_timers)((_ah), (_bs), (_tsf), \
  487          (_dc), (_cc)))
  488 #define ath_hal_set_associd(_ah, _bss, _associd) \
  489         ((*(_ah)->ah_set_associd)((_ah), (_bss), (_associd), 0))
  490 #define ath_hal_get_regdomain(_ah, _prd) \
  491         (*(_prd) = (_ah)->ah_get_regdomain(_ah))
  492 #define ath_hal_detach(_ah) \
  493         ((*(_ah)->ah_detach)(_ah))
  494 #define ath_hal_set_slot_time(_ah, _t) \
  495         ((*(_ah)->ah_set_slot_time)(_ah, _t))
  496 #define ath_hal_set_gpio_output(_ah, _gpio) \
  497         ((*(_ah)->ah_set_gpio_output)((_ah), (_gpio)))
  498 #define ath_hal_set_gpio_input(_ah, _gpio) \
  499         ((*(_ah)->ah_set_gpio_input)((_ah), (_gpio)))
  500 #define ath_hal_get_gpio(_ah, _gpio) \
  501         ((*(_ah)->ah_get_gpio)((_ah), (_gpio)))
  502 #define ath_hal_set_gpio(_ah, _gpio, _b) \
  503         ((*(_ah)->ah_set_gpio)((_ah), (_gpio), (_b)))
  504 #define ath_hal_set_gpio_intr(_ah, _gpio, _b) \
  505         ((*(_ah)->ah_set_gpio_intr)((_ah), (_gpio), (_b)))
  507 #define ath_hal_set_opmode(_ah) \
  508         ((*(_ah)->ah_set_opmode)((_ah)))
  509 #define ath_hal_stop_tx_dma(_ah, _qnum) \
  510         ((*(_ah)->ah_stop_tx_dma)((_ah), (_qnum)))
  511 #define ath_hal_stop_pcu_recv(_ah) \
  512         ((*(_ah)->ah_stop_pcu_recv)((_ah)))
  513 #define ath_hal_start_rx_pcu(_ah) \
  514         ((*(_ah)->ah_start_rx_pcu)((_ah)))
  515 #define ath_hal_stop_rx_dma(_ah) \
  516         ((*(_ah)->ah_stop_rx_dma)((_ah)))
  517 #define ath_hal_get_diag_state(_ah, _id, _indata, _insize, _outdata, _outsize) \
  518         ((*(_ah)->ah_get_diag_state)((_ah), (_id), \
  519          (_indata), (_insize), (_outdata), (_outsize)))
  521 #define ath_hal_setup_tx_queue(_ah, _type, _qinfo) \
  522         ((*(_ah)->ah_setup_tx_queue)((_ah), (_type), (_qinfo)))
  523 #define ath_hal_reset_tx_queue(_ah, _q) \
  524         ((*(_ah)->ah_reset_tx_queue)((_ah), (_q)))
  525 #define ath_hal_release_tx_queue(_ah, _q) \
  526         ((*(_ah)->ah_release_tx_queue)((_ah), (_q)))
  527 #define ath_hal_has_veol(_ah) \
  528         ((*(_ah)->ah_has_veol)((_ah)))
  529 #define ath_hal_update_mib_counters(_ah, _stats) \
  530         ((*(_ah)->ah_update_mib_counters)((_ah), (_stats)))
  531 #define ath_hal_get_rf_gain(_ah) \
  532         ((*(_ah)->ah_get_rf_gain)((_ah)))
  533 #define ath_hal_set_rx_signal(_ah) \
  534         ((*(_ah)->ah_set_rx_signal)((_ah)))
  536 #define ath_hal_setup_rx_desc(_ah, _ds, _size, _intreq) \
  537         ((*(_ah)->ah_setup_rx_desc)((_ah), (_ds), (_size), (_intreq)))
  538 #define ath_hal_proc_rx_desc(_ah, _ds, _dspa, _dsnext) \
  539         ((*(_ah)->ah_proc_rx_desc)((_ah), (_ds), (_dspa), (_dsnext)))
  540 #define ath_hal_setup_tx_desc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
_txr0, _txtr0, _keyix, _ant, _flags, \
_rtsrate, _rtsdura) \
  543         ((*(_ah)->ah_setup_tx_desc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
  544             (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
  545             (_flags), (_rtsrate), (_rtsdura)))
  546 #define ath_hal_setup_xtx_desc(_ah, _ds, \
_txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
  548         ((*(_ah)->ah_setup_xtx_desc)((_ah), (_ds), \
  549             (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
  550 #define ath_hal_fill_tx_desc(_ah, _ds, _l, _first, _last) \
  551         ((*(_ah)->ah_fill_tx_desc)((_ah), (_ds), (_l), (_first), (_last)))
  552 #define ath_hal_proc_tx_desc(_ah, _ds) \
  553         ((*(_ah)->ah_proc_tx_desc)((_ah), (_ds)))
  555 #endif /* _DEV_ATH_ATHVAR_H */