root/dev/cardbus/if_rl_cardbus.c

DEFINITIONS

1. rl_cardbus_match
2. rl_cardbus_attach
3. rl_detach
4. rl_cardbus_detach
5. rl_cardbus_setup

    1 /*      $OpenBSD: if_rl_cardbus.c,v 1.16 2007/05/08 18:49:32 deraadt Exp $ */
    2 /*      $NetBSD: if_rl_cardbus.c,v 1.3.8.3 2001/11/14 19:14:02 nathanw Exp $    */
    4 /*
    5  * Copyright (c) 2000 Masanori Kanaoka
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. The name of the author may not be used to endorse or promote products
   17  *    derived from this software without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
   28  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   29  */
   31 /*
   32  * if_rl_cardbus.c:
   33  *      Cardbus specific routines for RealTek 8139 ethernet adapter.
   34  *      Tested for 
   35  *              - elecom-Laneed LD-10/100CBA (Accton MPX5030)
   36  *              - MELCO         LPC3-TX-CB   (RealTek 8139)
   37  */
   39 #include "bpfilter.h"
   41 #include <sys/param.h>
   42 #include <sys/systm.h>
   43 #include <sys/mbuf.h>
   44 #include <sys/socket.h>
   45 #include <sys/ioctl.h>
   46 #include <sys/errno.h>
   47 #include <sys/malloc.h>
   48 #include <sys/kernel.h>
   49 #include <sys/timeout.h>
   50 #include <sys/device.h>
   52 #include <net/if.h>
   53 #include <net/if_dl.h>
   54 #include <net/if_types.h>
   55 #include <net/if_media.h>
   57 #include <machine/endian.h>
   59 #if NBPFILTER > 0
   60 #include <net/bpf.h>
   61 #endif
   63 #ifdef INET
   64 #include <netinet/in.h>
   65 #include <netinet/in_systm.h>
   66 #include <netinet/in_var.h>
   67 #include <netinet/ip.h>
   68 #include <netinet/if_ether.h>
   69 #endif
   71 #include <machine/bus.h>
   72 #include <machine/intr.h>
   74 #include <dev/mii/miivar.h>
   76 #include <dev/pci/pcivar.h>
   77 #include <dev/pci/pcireg.h>
   78 #include <dev/pci/pcidevs.h>
   80 #include <dev/cardbus/cardbusvar.h>
   82 /*
   83  * Default to using PIO access for this driver. On SMP systems,
   84  * there appear to be problems with memory mapped mode: it looks like
   85  * doing too many memory mapped access back to back in rapid succession
   86  * can hang the bus. I'm inclined to blame this on crummy design/construction
   87  * on the part of RealTek. Memory mapped mode does appear to work on
   88  * uniprocessor systems though.
   89  */
   90 #define RL_USEIOSPACE 
   92 #include <dev/ic/rtl81x9reg.h>
   94 /*
   95  * Various supported device vendors/types and their names.
   96  */
   97 const struct cardbus_matchid rl_cardbus_devices[] = {
   98         { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_5030 },
   99         { PCI_VENDOR_ABOCOM, PCI_PRODUCT_ABOCOM_FE2000VX },
  100         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8138 },
  101         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139 },
  102         { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD },
  103         { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD },
  104         { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD },
  105         { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3603_TX },
  106         { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX },
  107 };
  109 struct rl_cardbus_softc {
  110         struct rl_softc sc_rl;  /* real rtk softc */ 
  112         /* CardBus-specific goo. */
  113         void *sc_ih;
cardbus_devfunc_t sc_ct;
cardbustag_t sc_tag;
  116         int sc_csr;
  117         int sc_cben;
  118         int sc_bar_reg;
pcireg_t sc_bar_val;
bus_size_t sc_mapsize;
  121         int sc_intrline;
  122 };
  124 static int rl_cardbus_match(struct device *, void *, void *);
  125 static void rl_cardbus_attach(struct device *, struct device *, void *);
  126 static int rl_cardbus_detach(struct device *, int);
  127 void rl_cardbus_setup(struct rl_cardbus_softc *);
  129 struct cfattach rl_cardbus_ca = {
  130         sizeof(struct rl_cardbus_softc), rl_cardbus_match, rl_cardbus_attach,
rl_cardbus_detach
  132 };
  134 int
rl_cardbus_match(parent, match, aux)
  136         struct device *parent;
  137         void *match;
  138         void *aux;
  139 {
  140         return (cardbus_matchbyid((struct cardbus_attach_args *)aux,
rl_cardbus_devices,
  142             sizeof(rl_cardbus_devices)/sizeof(rl_cardbus_devices[0])));
  143 }
  146 void
rl_cardbus_attach(parent, self, aux)
  148         struct device *parent, *self;
  149         void *aux;
  150 {
  151         struct rl_cardbus_softc *csc = (struct rl_cardbus_softc *)self;
  152         struct rl_softc *sc = &csc->sc_rl;
  153         struct cardbus_attach_args *ca = aux;
  154         struct cardbus_softc *psc =
  155             (struct cardbus_softc *)sc->sc_dev.dv_parent;
cardbus_chipset_tag_t cc = psc->sc_cc;
cardbus_function_tag_t cf = psc->sc_cf;                            
cardbus_devfunc_t ct = ca->ca_ct;
bus_addr_t adr;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_intrline = ca->ca_intrline;
  166         /*
  167          * Map control/status registers.
  168          */
csc->sc_csr = CARDBUS_COMMAND_MASTER_ENABLE;
  170 #ifdef RL_USEIOSPACE
  171         if (Cardbus_mapreg_map(ct, RL_PCI_LOIO, CARDBUS_MAPREG_TYPE_IO, 0,
  172             &sc->rl_btag, &sc->rl_bhandle, &adr, &csc->sc_mapsize) == 0) {
csc->sc_cben = CARDBUS_IO_ENABLE;
csc->sc_csr |= CARDBUS_COMMAND_IO_ENABLE;
csc->sc_bar_reg = RL_PCI_LOIO;
csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_IO;
  177         }
  178 #else
  179         if (Cardbus_mapreg_map(ct, RL_PCI_LOMEM, CARDBUS_MAPREG_TYPE_MEM, 0,
  180             &sc->rl_btag, &sc->rl_bhandle, &adr, &csc->sc_mapsize) == 0) {
csc->sc_cben = CARDBUS_MEM_ENABLE;
csc->sc_csr |= CARDBUS_COMMAND_MEM_ENABLE;
csc->sc_bar_reg = RL_PCI_LOMEM;
csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_MEM;
  185         }
  186 #endif
  187         else {
printf("%s: unable to map deviceregisters\n",
sc->sc_dev.dv_xname);
  190                 return;
  191         }
Cardbus_function_enable(ct);
rl_cardbus_setup(csc);
  197         /*
  198          * Map and establish the interrupt.
  199          */
csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
rl_intr, sc, sc->sc_dev.dv_xname);
  202         if (csc->sc_ih == NULL) {
printf(": couldn't establish interrupt\n");
Cardbus_function_disable(csc->sc_ct);
  205                 return;
  206         }
printf(": irq %d", csc->sc_intrline);
  209         /* XXX - hardcode this, for now */
sc->rl_type = RL_8139;
rl_attach(sc);
  213 }
  215 extern int rl_detach(struct rl_softc *);
  217 int
rl_detach(sc)
  219         struct rl_softc *sc;
  220 {
  221         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  223         /* Unhook our tick handler. */
timeout_del(&sc->sc_tick_tmo);
  226         /* Detach any PHYs we might have. */
  227         if (LIST_FIRST(&sc->sc_mii.mii_phys) != NULL)
mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
  230         /* Delete any remaining media. */
ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
ether_ifdetach(ifp);
if_detach(ifp);
  236         if (sc->sc_sdhook != NULL)
shutdownhook_disestablish(sc->sc_sdhook);
  238         if (sc->sc_pwrhook != NULL)
powerhook_disestablish(sc->sc_pwrhook);
  241         return (0);
  242 }
  244 int 
rl_cardbus_detach(self, flags)
  246         struct device *self;
  247         int flags;
  248 {
  249         struct rl_cardbus_softc *csc = (void *) self;
  250         struct rl_softc *sc = &csc->sc_rl;
  251         struct cardbus_devfunc *ct = csc->sc_ct;
  252         int     rv;
  254 #ifdef DIAGNOSTIC
  255         if (ct == NULL)
panic("%s: data structure lacks", sc->sc_dev.dv_xname);
  257 #endif
rv = rl_detach(sc);
  259         if (rv)
  260                 return (rv);
  261         /*
  262          * Unhook the interrupt handler.
  263          */
  264         if (csc->sc_ih != NULL)
cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
  267         /*
  268          * Release bus space and close window.
  269          */
  270         if (csc->sc_bar_reg != 0)
Cardbus_mapreg_unmap(ct, csc->sc_bar_reg,
sc->rl_btag, sc->rl_bhandle, csc->sc_mapsize);
  274         return (0);
  275 }
  277 void 
rl_cardbus_setup(csc)
  279         struct rl_cardbus_softc *csc;
  280 {
  281         struct rl_softc *sc = &csc->sc_rl;
cardbus_devfunc_t ct = csc->sc_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
pcireg_t        reg, command;
  286         int             pmreg;
  288         /*
  289          * Handle power management nonsense.
  290          */
  291         if (cardbus_get_capability(cc, cf, csc->sc_tag,
PCI_CAP_PWRMGMT, &pmreg, 0)) {
command = cardbus_conf_read(cc, cf, csc->sc_tag, pmreg + 4);
  294                 if (command & RL_PSTATE_MASK) {
pcireg_t                iobase, membase, irq;
  297                         /* Save important PCI config data. */
iobase = cardbus_conf_read(cc, cf, csc->sc_tag,
RL_PCI_LOIO);
membase = cardbus_conf_read(cc, cf,csc->sc_tag,
RL_PCI_LOMEM);
irq = cardbus_conf_read(cc, cf,csc->sc_tag,
PCI_PRODUCT_DELTA_8139);
  305                         /* Reset the power state. */
printf("%s: chip is in D%d power mode "
  307                             "-- setting to D0\n", sc->sc_dev.dv_xname,
command & RL_PSTATE_MASK);
command &= 0xFFFFFFFC;
cardbus_conf_write(cc, cf, csc->sc_tag,
pmreg + 4, command);
  313                         /* Restore PCI config data. */
cardbus_conf_write(cc, cf, csc->sc_tag,
RL_PCI_LOIO, iobase);
cardbus_conf_write(cc, cf, csc->sc_tag,
RL_PCI_LOMEM, membase);
cardbus_conf_write(cc, cf, csc->sc_tag,
PCI_PRODUCT_DELTA_8139, irq);
  320                 }
  321         }
  323         /* Make sure the right access type is on the CardBus bridge. */
  324         (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben);
  325         (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
  327         /* Program the BAR */
cardbus_conf_write(cc, cf, csc->sc_tag,
csc->sc_bar_reg, csc->sc_bar_val);
  331         /* Enable the appropriate bits in the CARDBUS CSR. */
reg = cardbus_conf_read(cc, cf, csc->sc_tag, 
CARDBUS_COMMAND_STATUS_REG);
reg &= ~(CARDBUS_COMMAND_IO_ENABLE|CARDBUS_COMMAND_MEM_ENABLE);
reg |= csc->sc_csr;
cardbus_conf_write(cc, cf, csc->sc_tag, 
CARDBUS_COMMAND_STATUS_REG, reg);
  339         /*
  340          * Make sure the latency timer is set to some reasonable
  341          * value.
  342          */
reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG);
  344         if (CARDBUS_LATTIMER(reg) < 0x20) {
reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg);
  348         }
  349 }