1 /* $OpenBSD: nsgphy.c,v 1.18 2006/12/27 19:11:09 kettenis Exp $ */
2 /*
3 * Copyright (c) 2001 Wind River Systems
4 * Copyright (c) 2001
5 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 /*
37 * Driver for the National Semiconductor DP83891 and DP83861
38 * 10/100/1000 PHYs.
39 * Datasheet available at: http://www.national.com/ds/DP/DP83861.pdf
40 *
41 * The DP83891 is the older NatSemi gigE PHY which isn't being sold
42 * anymore. The DP83861 is its replacement, which is an 'enhanced'
43 * firmware driven component. The major difference between the
44 * two is that the 83891 can't generate interrupts, while the
45 * 83861 can. (I think it wasn't originally designed to do this, but
46 * it can now thanks to firmware updates.) The 83861 also allows
47 * access to its internal RAM via indirect register access.
48 */
49
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/device.h>
54 #include <sys/socket.h>
55
56 #include <net/if.h>
57 #include <net/if_media.h>
58
59 #include <dev/mii/mii.h>
60 #include <dev/mii/miivar.h>
61 #include <dev/mii/miidevs.h>
62
63 #include <dev/mii/nsgphyreg.h>
64
65 int nsgphymatch(struct device*, void *, void *);
66 void nsgphyattach(struct device *, struct device *, void *);
67
68 struct cfattach nsgphy_ca = {
69 sizeof(struct mii_softc), nsgphymatch, nsgphyattach, mii_phy_detach,
70 mii_phy_activate
71 };
72
73 struct cfdriver nsgphy_cd = {
74 NULL, "nsgphy", DV_DULL
75 };
76
77 int nsgphy_service(struct mii_softc *, struct mii_data *, int);
78 void nsgphy_status(struct mii_softc *);
79
80 const struct mii_phy_funcs nsgphy_funcs = {
81 nsgphy_service, nsgphy_status, mii_phy_reset,
82 };
83
84 static const struct mii_phydesc nsgphys[] = {
85 { MII_OUI_NATSEMI, MII_MODEL_NATSEMI_DP83861,
86 MII_STR_NATSEMI_DP83861 },
87 { MII_OUI_NATSEMI, MII_MODEL_NATSEMI_DP83891,
88 MII_STR_NATSEMI_DP83891 },
89
90 { 0, 0,
91 NULL },
92 };
93
94 int
95 nsgphymatch(struct device *parent, void *match, void *aux)
96 {
97 struct mii_attach_args *ma = aux;
98
99 if (mii_phy_match(ma, nsgphys) != NULL)
100 return (10);
101
102 return (0);
103 }
104
105 void
106 nsgphyattach(struct device *parent, struct device *self, void *aux)
107 {
108 struct mii_softc *sc = (struct mii_softc *)self;
109 struct mii_attach_args *ma = aux;
110 struct mii_data *mii = ma->mii_data;
111 const struct mii_phydesc *mpd;
112 int anar;
113
114 mpd = mii_phy_match(ma, nsgphys);
115 printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
116
117 sc->mii_inst = mii->mii_instance;
118 sc->mii_phy = ma->mii_phyno;
119 sc->mii_funcs = &nsgphy_funcs;
120 sc->mii_pdata = mii;
121 sc->mii_flags = ma->mii_flags;
122 sc->mii_anegticks = MII_ANEGTICKS;
123
124 PHY_RESET(sc);
125
126 sc->mii_capabilities =
127 PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
128 if (sc->mii_capabilities & BMSR_EXTSTAT)
129 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
130
131 /*
132 * The PHY seems to have the 10baseT BMSR bits
133 * hard-wired to 0, even though the device supports
134 * 10baseT. What we do instead is read the post-reset
135 * ANAR, who's 10baseT-related bits are set by strapping
136 * pin 180, and fake the BMSR bits.
137 */
138 anar = PHY_READ(sc, MII_ANAR);
139 if (anar & ANAR_10)
140 sc->mii_capabilities |= (BMSR_10THDX & ma->mii_capmask);
141 if (anar & ANAR_10_FD)
142 sc->mii_capabilities |= (BMSR_10TFDX & ma->mii_capmask);
143
144 if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
145 (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
146 mii_phy_add_media(sc);
147 }
148
149 int
150 nsgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
151 {
152 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
153 int reg;
154
155 if ((sc->mii_dev.dv_flags & DVF_ACTIVE) == 0)
156 return (ENXIO);
157
158 switch (cmd) {
159 case MII_POLLSTAT:
160 /*
161 * If we're not polling our PHY instance, just return.
162 */
163 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
164 return (0);
165 break;
166
167 case MII_MEDIACHG:
168 /*
169 * If the media indicates a different PHY instance,
170 * isolate ourselves.
171 */
172 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
173 reg = PHY_READ(sc, MII_BMCR);
174 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
175 return (0);
176 }
177
178 /*
179 * If the interface is not up, don't do anything.
180 */
181 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
182 break;
183
184 mii_phy_setmedia(sc);
185 break;
186
187 case MII_TICK:
188 /*
189 * If we're not currently selected, just return.
190 */
191 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
192 return (0);
193
194 if (mii_phy_tick(sc) == EJUSTRETURN)
195 return (0);
196 break;
197 case MII_DOWN:
198 mii_phy_down(sc);
199 return (0);
200 }
201
202 /* Update the media status. */
203 mii_phy_status(sc);
204
205 /* Callback if something changed. */
206 mii_phy_update(sc, cmd);
207 return (0);
208 }
209
210 void
211 nsgphy_status(struct mii_softc *sc)
212 {
213 struct mii_data *mii = sc->mii_pdata;
214 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
215 int bmsr, bmcr, physup, gtsr;
216
217 mii->mii_media_status = IFM_AVALID;
218 mii->mii_media_active = IFM_ETHER;
219
220 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
221
222 physup = PHY_READ(sc, NSGPHY_MII_PHYSUP);
223
224 if (physup & PHY_SUP_LINK)
225 mii->mii_media_status |= IFM_ACTIVE;
226
227 bmcr = PHY_READ(sc, MII_BMCR);
228 if (bmcr & BMCR_ISO) {
229 mii->mii_media_active |= IFM_NONE;
230 mii->mii_media_status = 0;
231 return;
232 }
233
234 if (bmcr & BMCR_LOOP)
235 mii->mii_media_active |= IFM_LOOP;
236
237 if (bmcr & BMCR_AUTOEN) {
238 if ((bmsr & BMSR_ACOMP) == 0) {
239 /* Erg, still trying, I guess... */
240 mii->mii_media_active |= IFM_NONE;
241 return;
242 }
243
244 switch (physup & (PHY_SUP_SPEED1|PHY_SUP_SPEED0)) {
245 case PHY_SUP_SPEED1:
246 mii->mii_media_active |= IFM_1000_T;
247 gtsr = PHY_READ(sc, MII_100T2SR);
248 if (gtsr & GTSR_MS_RES)
249 mii->mii_media_active |= IFM_ETH_MASTER;
250 break;
251
252 case PHY_SUP_SPEED0:
253 mii->mii_media_active |= IFM_100_TX;
254 break;
255
256 case 0:
257 mii->mii_media_active |= IFM_10_T;
258 break;
259
260 default:
261 mii->mii_media_active |= IFM_NONE;
262 mii->mii_media_status = 0;
263 return;
264 }
265
266 if (physup & PHY_SUP_DUPLEX)
267 mii->mii_media_active |= IFM_FDX;
268 else
269 mii->mii_media_active |= IFM_HDX;
270 } else
271 mii->mii_media_active = ife->ifm_media;
272 }