root/dev/tc/if_le_ioasic.c

DEFINITIONS

1. le_ioasic_match
2. le_ioasic_attach
3. le_ioasic_copytobuf_gap2
4. le_ioasic_copyfrombuf_gap2
5. le_ioasic_copytobuf_gap16
6. le_ioasic_copyfrombuf_gap16
7. le_ioasic_zerobuf_gap16

    1 /*      $OpenBSD: if_le_ioasic.c,v 1.13 2007/06/18 21:24:43 jasper Exp $        */
    2 /*      $NetBSD: if_le_ioasic.c,v 1.18 2001/11/13 06:26:10 lukem Exp $  */
    4 /*
    5  * Copyright (c) 1996 Carnegie-Mellon University.
    6  * All rights reserved.
    7  *
    8  * Author: Chris G. Demetriou
    9  *
   10  * Permission to use, copy, modify and distribute this software and
   11  * its documentation is hereby granted, provided that both the copyright
   12  * notice and this permission notice appear in all copies of the
   13  * software, derivative works or modified versions, and any portions
   14  * thereof, and that both notices appear in supporting documentation.
   15  *
   16  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
   17  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
   18  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   19  *
   20  * Carnegie Mellon requests users of this software to return to
   21  *
   22  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   23  *  School of Computer Science
   24  *  Carnegie Mellon University
   25  *  Pittsburgh PA 15213-3890
   26  *
   27  * any improvements or extensions that they make and grant Carnegie the
   28  * rights to redistribute these changes.
   29  */
   31 /*
   32  * LANCE on DEC IOCTL ASIC.
   33  */
   35 #include <sys/param.h>
   36 #include <sys/systm.h>
   37 #include <sys/mbuf.h>
   38 #include <sys/syslog.h>
   39 #include <sys/socket.h>
   40 #include <sys/device.h>
   42 #include <net/if.h>
   43 #include <net/if_media.h>
   45 #ifdef INET
   46 #include <netinet/in.h>
   47 #include <netinet/if_ether.h>
   48 #endif
   50 #include <dev/ic/am7990reg.h>
   51 #include <dev/ic/am7990var.h>
   53 #include <dev/tc/if_levar.h>
   54 #include <dev/tc/tcvar.h>
   55 #include <dev/tc/ioasicreg.h>
   56 #include <dev/tc/ioasicvar.h>
   58 struct le_ioasic_softc {
   59         struct  am7990_softc sc_am7990; /* glue to MI code */
   60         struct  lereg1 *sc_r1;          /* LANCE registers */
   61         /* XXX must match with le_softc of if_levar.h XXX */
bus_dma_tag_t sc_dmat;          /* bus dma tag */
bus_dmamap_t sc_dmamap;         /* bus dmamap */
   65 };
   67 int  le_ioasic_match(struct device *, void *, void *);
   68 void le_ioasic_attach(struct device *, struct device *, void *);
   70 struct cfattach le_ioasic_ca = {
   71         sizeof(struct le_softc), le_ioasic_match, le_ioasic_attach
   72 };
   74 void le_ioasic_copytobuf_gap2(struct am7990_softc *, void *,
   75             int, int);
   76 void le_ioasic_copyfrombuf_gap2(struct am7990_softc *, void *,
   77             int, int);
   78 void le_ioasic_copytobuf_gap16(struct am7990_softc *, void *,
   79             int, int);
   80 void le_ioasic_copyfrombuf_gap16(struct am7990_softc *, void *,
   81             int, int);
   82 void le_ioasic_zerobuf_gap16(struct am7990_softc *, int, int);
   84 int
le_ioasic_match(struct device *parent, void *match, void *aux)
   86 {
   87         struct ioasicdev_attach_args *d = aux;
   89         if (strncmp("PMAD-BA ", d->iada_modname, TC_ROM_LLEN) != 0)
   90                 return 0;
   92         return 1;
   93 }
   95 /* IOASIC LANCE DMA needs 128KB boundary aligned 128KB chunk */
   96 #define LE_IOASIC_MEMSIZE       (128*1024)
   97 #define LE_IOASIC_MEMALIGN      (128*1024)
   99 void
le_ioasic_attach(struct device *parent, struct device *self, void *aux)
  101 {
  102         struct le_ioasic_softc *sc = (void *)self;
  103         struct ioasicdev_attach_args *d = aux;
  104         struct am7990_softc *le = &sc->sc_am7990;
bus_space_tag_t ioasic_bst;
bus_space_handle_t ioasic_bsh;
bus_dma_tag_t dmat;
bus_dma_segment_t seg;
tc_addr_t tca;
u_int32_t ssr;
  111         int rseg;
caddr_t le_iomem;
ioasic_bst = ((struct ioasic_softc *)parent)->sc_bst;
ioasic_bsh = ((struct ioasic_softc *)parent)->sc_bsh;
dmat = sc->sc_dmat = ((struct ioasic_softc *)parent)->sc_dmat;
  117         /*
  118          * Allocate a DMA area for the chip.
  119          */
  120         if (bus_dmamem_alloc(dmat, LE_IOASIC_MEMSIZE, LE_IOASIC_MEMALIGN,
  121             0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf("can't allocate DMA area for LANCE\n");
  123                 return;
  124         }
  125         if (bus_dmamem_map(dmat, &seg, rseg, LE_IOASIC_MEMSIZE,
  126             &le_iomem, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
printf("can't map DMA area for LANCE\n");
bus_dmamem_free(dmat, &seg, rseg);
  129                 return;
  130         }
  131         /*
  132          * Create and load the DMA map for the DMA area.
  133          */
  134         if (bus_dmamap_create(dmat, LE_IOASIC_MEMSIZE, 1,
LE_IOASIC_MEMSIZE, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
printf("can't create DMA map\n");
  137                 goto bad;
  138         }
  139         if (bus_dmamap_load(dmat, sc->sc_dmamap,
le_iomem, LE_IOASIC_MEMSIZE, NULL, BUS_DMA_NOWAIT)) {
printf("can't load DMA map\n");
  142                 goto bad;
  143         }
  144         /*
  145          * Bind 128KB buffer with IOASIC DMA.
  146          */
tca = IOASIC_DMA_ADDR(sc->sc_dmamap->dm_segs[0].ds_addr);
bus_space_write_4(ioasic_bst, ioasic_bsh, IOASIC_LANCE_DMAPTR, tca);
ssr = bus_space_read_4(ioasic_bst, ioasic_bsh, IOASIC_CSR);
ssr |= IOASIC_CSR_DMAEN_LANCE;
bus_space_write_4(ioasic_bst, ioasic_bsh, IOASIC_CSR, ssr);
sc->sc_r1 = (struct lereg1 *)
TC_DENSE_TO_SPARSE(TC_PHYS_TO_UNCACHED(d->iada_addr));
le->sc_mem = (void *)TC_PHYS_TO_UNCACHED(le_iomem);
le->sc_copytodesc = le_ioasic_copytobuf_gap2;
le->sc_copyfromdesc = le_ioasic_copyfrombuf_gap2;
le->sc_copytobuf = le_ioasic_copytobuf_gap16;
le->sc_copyfrombuf = le_ioasic_copyfrombuf_gap16;
le->sc_zerobuf = le_ioasic_zerobuf_gap16;
dec_le_common_attach(&sc->sc_am7990,
  163             (u_char *)((struct ioasic_softc *)parent)->sc_base
  164                 + IOASIC_SLOT_2_START);
ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_NET,
am7990_intr, sc);
  168         return;
bad:
bus_dmamem_unmap(dmat, le_iomem, LE_IOASIC_MEMSIZE);
bus_dmamem_free(dmat, &seg, rseg);
  173 }
  175 /*
  176  * Special memory access functions needed by ioasic-attached LANCE
  177  * chips.
  178  */
  180 /*
  181  * gap2: two bytes of data followed by two bytes of pad.
  182  *
  183  * Buffers must be 4-byte aligned.  The code doesn't worry about
  184  * doing an extra byte.
  185  */
  187 void
le_ioasic_copytobuf_gap2(struct am7990_softc *sc, void *fromv,
  189     int boff, int len)
  190 {
  191         volatile caddr_t buf = sc->sc_mem;
caddr_t from = fromv;
  193         volatile u_int16_t *bptr;  
  195         if (boff & 0x1) {
  196                 /* handle unaligned first byte */
bptr = ((volatile u_int16_t *)buf) + (boff - 1);
  198                 *bptr = (*from++ << 8) | (*bptr & 0xff);
bptr += 2;  
len--;
  201         } else
bptr = ((volatile u_int16_t *)buf) + boff;
  203         while (len > 1) {
  204                 *bptr = (from[1] << 8) | (from[0] & 0xff);
bptr += 2;
from += 2;
len -= 2;
  208         }
  209         if (len == 1)
  210                 *bptr = (u_int16_t)*from;
  211 }
  213 void
le_ioasic_copyfrombuf_gap2(struct am7990_softc *sc, void *tov,
  215     int boff, int len)
  216 {
  217         volatile caddr_t buf = sc->sc_mem;
caddr_t to = tov;
  219         volatile u_int16_t *bptr;
u_int16_t tmp;
  222         if (boff & 0x1) {
  223                 /* handle unaligned first byte */
bptr = ((volatile u_int16_t *)buf) + (boff - 1);
  225                 *to++ = (*bptr >> 8) & 0xff;
bptr += 2;
len--;
  228         } else
bptr = ((volatile u_int16_t *)buf) + boff;
  230         while (len > 1) {
tmp = *bptr;
  232                 *to++ = tmp & 0xff;
  233                 *to++ = (tmp >> 8) & 0xff;
bptr += 2;
len -= 2;
  236         }
  237         if (len == 1)
  238                 *to = *bptr & 0xff;
  239 }
  241 /*
  242  * gap16: 16 bytes of data followed by 16 bytes of pad.
  243  *
  244  * Buffers must be 32-byte aligned.
  245  */
  247 void
le_ioasic_copytobuf_gap16(struct am7990_softc *sc, void *fromv,
  249     int boff, int len)
  250 {
  251         volatile caddr_t buf = sc->sc_mem;
caddr_t from = fromv;
caddr_t bptr;
bptr = buf + ((boff << 1) & ~0x1f);
boff &= 0xf;
  258         /*
  259          * Dispose of boff so destination of subsequent copies is
  260          * 16-byte aligned.
  261          */
  262         if (boff) {
  263                 int xfer;
xfer = min(len, 16 - boff);
bcopy(from, bptr + boff, xfer);
from += xfer;
bptr += 32;
len -= xfer;
  269         }
  271         /* Destination of  copies is now 16-byte aligned. */
  272         if (len >= 16)
  273                 switch ((u_long)from & (sizeof(u_int32_t) -1)) {
  274                 case 2:
  275                         /*  Ethernet headers make this the dominant case. */
  276                 do {
u_int32_t *dst = (u_int32_t*)bptr;
u_int16_t t0;
u_int32_t t1,  t2, t3, t4;
  281                         /* read from odd-16-bit-aligned, cached src */
t0 = *(u_int16_t*)from;
t1 = *(u_int32_t*)(from+2);
t2 = *(u_int32_t*)(from+6);
t3 = *(u_int32_t*)(from+10);
t4 = *(u_int16_t*)(from+14);
  288                         /* DMA buffer is uncached on mips */
dst[0] =         t0 |  (t1 << 16);
dst[1] = (t1 >> 16) |  (t2 << 16);
dst[2] = (t2 >> 16) |  (t3 << 16);
dst[3] = (t3 >> 16) |  (t4 << 16);
from += 16;
bptr += 32;
len -= 16;
  297                 } while (len >= 16);
  298                 break;
  300                 case 0:
  301                 do {
u_int32_t *src = (u_int32_t*)from;
u_int32_t *dst = (u_int32_t*)bptr;
u_int32_t t0, t1, t2, t3;
t0 = src[0]; t1 = src[1]; t2 = src[2]; t3 = src[3];
dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3;
from += 16;
bptr += 32;
len -= 16;
  312                 } while (len >= 16);
  313                 break;
  315                 default: 
  316                 /* Does odd-aligned case ever happen? */
  317                 do {
bcopy(from, bptr, 16);
from += 16;
bptr += 32;
len -= 16;
  322                 } while (len >= 16);
  323                 break;
  324         }
  325         if (len)
bcopy(from, bptr, len);
  327 }
  329 void
le_ioasic_copyfrombuf_gap16(struct am7990_softc *sc, void *tov,
  331     int boff, int len)
  332 {
  333         volatile caddr_t buf = sc->sc_mem;
caddr_t to = tov;
caddr_t bptr;
bptr = buf + ((boff << 1) & ~0x1f);
boff &= 0xf;
  340         /* Dispose of boff. source of copy is subsequently 16-byte aligned. */
  341         if (boff) {
  342                 int xfer;
xfer = min(len, 16 - boff);
bcopy(bptr+boff, to, xfer);
to += xfer;
bptr += 32;
len -= xfer;
  348         }
  349         if (len >= 16)
  350         switch ((u_long)to & (sizeof(u_int32_t) -1)) {
  351         case 2:
  352                 /*
  353                  * to is aligned to an odd 16-bit boundary.  Ethernet headers
  354                  * make this the dominant case (98% or more).
  355                  */
  356                 do {
u_int32_t *src = (u_int32_t*)bptr;
u_int32_t t0, t1, t2, t3;
  360                         /* read from uncached aligned DMA buf */
t0 = src[0]; t1 = src[1]; t2 = src[2]; t3 = src[3];
  363                         /* write to odd-16-bit-word aligned dst */
  364                         *(u_int16_t *) (to+0)  = (u_short)  t0;
  365                         *(u_int32_t *) (to+2)  = (t0 >> 16) |  (t1 << 16);
  366                         *(u_int32_t *) (to+6)  = (t1 >> 16) |  (t2 << 16);
  367                         *(u_int32_t *) (to+10) = (t2 >> 16) |  (t3 << 16);
  368                         *(u_int16_t *) (to+14) = (t3 >> 16);
bptr += 32;
to += 16;
len -= 16;
  372                 } while (len > 16);
  373                 break;
  374         case 0:
  375                 /* 32-bit aligned aligned copy. Rare. */
  376                 do {
u_int32_t *src = (u_int32_t*)bptr;
u_int32_t *dst = (u_int32_t*)to;
u_int32_t t0, t1, t2, t3;
t0 = src[0]; t1 = src[1]; t2 = src[2]; t3 = src[3];
dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3;
to += 16;
bptr += 32;
len -= 16;
  386                 } while (len  > 16);
  387                 break;
  389         /* XXX Does odd-byte-aligned case ever happen? */
  390         default:
  391                 do {
bcopy(bptr, to, 16);
to += 16;
bptr += 32;
len -= 16;
  396                 } while (len  > 16);
  397                 break;
  398         }
  399         if (len)
bcopy(bptr, to, len);
  401 }
  403 void
le_ioasic_zerobuf_gap16(struct am7990_softc *sc, int boff, int len)
  405 {
  406         volatile caddr_t buf = sc->sc_mem;
caddr_t bptr;
  408         int xfer;
bptr = buf + ((boff << 1) & ~0x1f);
boff &= 0xf;
xfer = min(len, 16 - boff);
  413         while (len > 0) {
bzero(bptr + boff, xfer);
bptr += 32;
boff = 0;
len -= xfer;
xfer = min(len, 16);
  419         }
  420 }