ssr               313 dev/mii/eephy.c 	int bmcr, gsr, ssr;
ssr               319 dev/mii/eephy.c 	ssr = PHY_READ(sc, E1000_SSR);
ssr               321 dev/mii/eephy.c 	if (ssr & E1000_SSR_LINK)
ssr               327 dev/mii/eephy.c 	if (!(ssr & E1000_SSR_SPD_DPLX_RESOLVED)) {
ssr               336 dev/mii/eephy.c 		if (ssr & E1000_SSR_1000MBS)
ssr               338 dev/mii/eephy.c 		else if (ssr & E1000_SSR_100MBS)
ssr               344 dev/mii/eephy.c 	if (ssr & E1000_SSR_DUPLEX)
ssr                82 dev/sbus/vigra.c 	u_int32_t	ssr;
ssr               110 dev/tc/if_le_ioasic.c 	u_int32_t ssr;
ssr               149 dev/tc/if_le_ioasic.c 	ssr = bus_space_read_4(ioasic_bst, ioasic_bsh, IOASIC_CSR);
ssr               150 dev/tc/if_le_ioasic.c 	ssr |= IOASIC_CSR_DMAEN_LANCE;
ssr               151 dev/tc/if_le_ioasic.c 	bus_space_write_4(ioasic_bst, ioasic_bsh, IOASIC_CSR, ssr);