1 /* $OpenBSD: ioasicreg.h,v 1.2 2003/06/02 23:28:04 millert Exp $ */
2 /* $NetBSD: ioasicreg.h,v 1.6 2000/07/17 02:18:17 thorpej Exp $ */
3
4 /*
5 * Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University
6 * All Rights Reserved.
7 *
8 * Permission to use, copy, modify and distribute this software and
9 * its documentation is hereby granted, provided that both the copyright
10 * notice and this permission notice appear in all copies of the
11 * software, derivative works or modified versions, and any portions
12 * thereof, and that both notices appear in supporting documentation.
13 *
14 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
15 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
16 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
17 *
18 * Carnegie Mellon requests users of this software to return to
19 *
20 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
21 * School of Computer Science
22 * Carnegie Mellon University
23 * Pittsburgh PA 15213-3890
24 *
25 * any improvements or extensions that they make and grant Carnegie the
26 * rights to redistribute these changes.
27 */
28
29 /*-
30 * Copyright (c) 1992, 1993
31 * The Regents of the University of California. All rights reserved.
32 *
33 * This code is derived from software contributed to Berkeley by
34 * The Mach Operating System project at Carnegie-Mellon University,
35 * Ralph Campbell and Rick Macklem.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
45 * 3. Neither the name of the University nor the names of its contributors
46 * may be used to endorse or promote products derived from this software
47 * without specific prior written permission.
48 *
49 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
51 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
52 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
53 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
54 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
55 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
56 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
57 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
58 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
59 * SUCH DAMAGE.
60 *
61 * @(#)asic.h 8.1 (Berkeley) 6/10/93
62 */
63
64 /*
65 * Slot definitions
66 */
67
68 #define IOASIC_SLOT_0_START 0x000000
69 #define IOASIC_SLOT_1_START 0x040000
70 #define IOASIC_SLOT_2_START 0x080000
71 #define IOASIC_SLOT_3_START 0x0c0000
72 #define IOASIC_SLOT_4_START 0x100000
73 #define IOASIC_SLOT_5_START 0x140000
74 #define IOASIC_SLOT_6_START 0x180000
75 #define IOASIC_SLOT_7_START 0x1c0000
76 #define IOASIC_SLOT_8_START 0x200000
77 #define IOASIC_SLOT_9_START 0x240000
78 #define IOASIC_SLOT_10_START 0x280000
79 #define IOASIC_SLOT_11_START 0x2c0000
80 #define IOASIC_SLOT_12_START 0x300000
81 #define IOASIC_SLOT_13_START 0x340000
82 #define IOASIC_SLOT_14_START 0x380000
83 #define IOASIC_SLOT_15_START 0x3c0000
84 #define IOASIC_SLOTS_END 0x3fffff
85
86 /*
87 * Register offsets (slot 1)
88 */
89
90 #define IOASIC_SCSI_DMAPTR IOASIC_SLOT_1_START+0x000
91 #define IOASIC_SCSI_NEXTPTR IOASIC_SLOT_1_START+0x010
92 #define IOASIC_LANCE_DMAPTR IOASIC_SLOT_1_START+0x020
93 #define IOASIC_SCC_T1_DMAPTR IOASIC_SLOT_1_START+0x030
94 #define IOASIC_SCC_R1_DMAPTR IOASIC_SLOT_1_START+0x040
95 #define IOASIC_SCC_T2_DMAPTR IOASIC_SLOT_1_START+0x050
96 #define IOASIC_SCC_R2_DMAPTR IOASIC_SLOT_1_START+0x060
97 #define IOASIC_FLOPPY_DMAPTR IOASIC_SLOT_1_START+0x070
98 #define IOASIC_ISDN_X_DMAPTR IOASIC_SLOT_1_START+0x080
99 #define IOASIC_ISDN_X_NEXTPTR IOASIC_SLOT_1_START+0x090
100 #define IOASIC_ISDN_R_DMAPTR IOASIC_SLOT_1_START+0x0a0
101 #define IOASIC_ISDN_R_NEXTPTR IOASIC_SLOT_1_START+0x0b0
102 #define IOASIC_BUFF0 IOASIC_SLOT_1_START+0x0c0
103 #define IOASIC_BUFF1 IOASIC_SLOT_1_START+0x0d0
104 #define IOASIC_BUFF2 IOASIC_SLOT_1_START+0x0e0
105 #define IOASIC_BUFF3 IOASIC_SLOT_1_START+0x0f0
106 #define IOASIC_CSR IOASIC_SLOT_1_START+0x100
107 #define IOASIC_INTR IOASIC_SLOT_1_START+0x110
108 #define IOASIC_IMSK IOASIC_SLOT_1_START+0x120
109 #define IOASIC_CURADDR IOASIC_SLOT_1_START+0x130
110 #define IOASIC_ISDN_X_DATA IOASIC_SLOT_1_START+0x140
111 #define IOASIC_ISDN_R_DATA IOASIC_SLOT_1_START+0x150
112 #define IOASIC_LANCE_DECODE IOASIC_SLOT_1_START+0x160
113 #define IOASIC_SCSI_DECODE IOASIC_SLOT_1_START+0x170
114 #define IOASIC_SCC0_DECODE IOASIC_SLOT_1_START+0x180
115 #define IOASIC_SCC1_DECODE IOASIC_SLOT_1_START+0x190
116 #define IOASIC_FLOPPY_DECODE IOASIC_SLOT_1_START+0x1a0
117 #define IOASIC_SCSI_SCR IOASIC_SLOT_1_START+0x1b0
118 #define IOASIC_SCSI_SDR0 IOASIC_SLOT_1_START+0x1c0
119 #define IOASIC_SCSI_SDR1 IOASIC_SLOT_1_START+0x1d0
120 #define IOASIC_CTR IOASIC_SLOT_1_START+0x1e0 /*3max+/3000*/
121
122 /* System Status and control Register (SSR). */
123 #define IOASIC_CSR_DMAEN_T1 0x80000000 /* rw */
124 #define IOASIC_CSR_DMAEN_R1 0x40000000 /* rw */
125 #define IOASIC_CSR_DMAEN_T2 0x20000000 /* rw */
126 #define IOASIC_CSR_DMAEN_R2 0x10000000 /* rw */
127 #define IOASIC_CSR_FASTMODE 0x08000000 /* rw - 3000 */
128 #define IOASIC_CSR_xxx 0x07800000 /* reserved - 3000 */
129 #define IOASIC_CSR_DS_xxx 0x0f800000 /* reserved - DS */
130 #define IOASIC_CSR_FLOPPY_DIR 0x00400000 /* rw - maxine */
131 #define IOASIC_CSR_DMAEN_FLOPPY 0x00200000 /* rw - maxine */
132 #define IOASIC_CSR_DMAEN_ISDN_T 0x00100000 /* rw */
133 #define IOASIC_CSR_DMAEN_ISDN_R 0x00080000 /* rw */
134 #define IOASIC_CSR_SCSI_DIR 0x00040000 /* rw - DS */
135 #define IOASIC_CSR_DMAEN_SCSI 0x00020000 /* rw - DS */
136 #define IOASIC_CSR_DMAEN_LANCE 0x00010000 /* rw - DS */
137 /* low 16 bits are rw gp outputs */
138 #define IOASIC_CSR_DIAGDN 0x00008000 /* rw */
139 #define IOASIC_CSR_TXDIS_2 0x00004000 /* rw - 3min,3max+ */
140 #define IOASIC_CSR_TXDIS_1 0x00002000 /* rw - 3min,3max+ */
141 #define IOASIC_CSR_ISDN_ENABLE 0x00001000 /* rw - 3000/maxine */
142 #define IOASIC_CSR_SCC_ENABLE 0x00000800 /* rw */
143 #define IOASIC_CSR_RTC_ENABLE 0x00000400 /* rw */
144 #define IOASIC_CSR_SCSI_ENABLE 0x00000200 /* rw - DS */
145 #define IOASIC_CSR_LANCE_ENABLE 0x00000100 /* rw */
146
147 /* System Interrupt Register (and Interrupt Mask Register). */
148 #define IOASIC_INTR_T1_PAGE_END 0x80000000 /* rz */
149 #define IOASIC_INTR_T1_READ_E 0x40000000 /* rz */
150 #define IOASIC_INTR_R1_HALF_PAGE 0x20000000 /* rz */
151 #define IOASIC_INTR_R1_DMA_OVRUN 0x10000000 /* rz */
152 #define IOASIC_INTR_T2_PAGE_END 0x08000000 /* rz */
153 #define IOASIC_INTR_T2_READ_E 0x04000000 /* rz */
154 #define IOASIC_INTR_R2_HALF_PAGE 0x02000000 /* rz */
155 #define IOASIC_INTR_R2_DMA_OVRUN 0x01000000 /* rz */
156 #define IOASIC_INTR_FLOPPY_DMA_E 0x00800000 /* rz - maxine */
157 #define IOASIC_INTR_ISDN_TXLOAD 0x00400000 /* rz - 3000/maxine */
158 #define IOASIC_INTR_ISDN_RXLOAD 0x00200000 /* rz - 3000/maxine */
159 #define IOASIC_INTR_ISDN_OVRUN 0x00100000 /* rz - 3000/maxine */
160 #define IOASIC_INTR_SCSI_PTR_LOAD 0x00080000 /* rz - DS */
161 #define IOASIC_INTR_SCSI_OVRUN 0x00040000 /* rz - DS */
162 #define IOASIC_INTR_SCSI_READ_E 0x00020000 /* rz - DS */
163 #define IOASIC_INTR_LANCE_READ_E 0x00010000 /* rz - DS */
164
165 /* low 16 bits are model-dependent; see also model specific *.h */
166 #define IOASIC_INTR_NVR_JUMPER 0x00004000 /* ro */
167 #define IOASIC_INTR_ISDN 0x00002000 /* ro - 3000 */
168 #define IOASIC_INTR_NRMOD_JUMPER 0x00000400 /* ro */
169 #define IOASIC_INTR_SEC_CON 0x00000200 /* ro */
170 #define IOASIC_INTR_SCSI 0x00000200 /* ro - DS */
171 #define IOASIC_INTR_LANCE 0x00000100 /* ro */
172 #define IOASIC_INTR_SCC_1 0x00000080 /* ro */
173 #define IOASIC_INTR_SCC_0 0x00000040 /* ro */
174 #define IOASIC_INTR_ALT_CON 0x00000008 /* ro - 3000/500 */
175 #define IOASIC_INTR_300_OPT1 0x00000008 /* ro - 3000/300 */
176 #define IOASIC_INTR_300_OPT0 0x00000004 /* ro - 3000/300 */
177
178 /* DMA pointer registers (SCSI, Comm, ...) */
179
180 #define IOASIC_DMA_ADDR(p) \
181 ((((p) << 3) & ~0x1f) | (((p) >> 29) & 0x1f))
182 #define IOASIC_DMA_BLOCKSIZE 0x1000
183
184 /* For the LANCE DMA pointer register initialization the above suffices */
185
186 /* More SCSI DMA registers */
187
188 #define IOASIC_SCR_STATUS 0x00000004
189 #define IOASIC_SCR_WORD 0x00000003
190
191 /* Various Decode registers */
192
193 #define IOASIC_DECODE_HW_ADDRESS 0x000003f0
194 #define IOASIC_DECODE_CHIP_SELECT 0x0000000f
195
196 /*
197 * And slot assignments.
198 */
199 #define IOASIC_SYS_ETHER_ADDRESS(base) ((base) + IOASIC_SLOT_2_START)
200 #define IOASIC_SYS_LANCE(base) ((base) + IOASIC_SLOT_3_START)