root/arch/i386/pci/glxsb.c

DEFINITIONS

1. glxsb_match
2. glxsb_attach
3. glxsb_rnd
4. glxsb_crypto_setup
5. glxsb_crypto_newsession
6. glxsb_crypto_freesession
7. glxsb_aes
8. glxsb_crypto_swauth
9. glxsb_crypto_encdec
10. glxsb_crypto_process
11. glxsb_dma_alloc
12. glxsb_dma_pre_op
13. glxsb_dma_post_op
14. glxsb_dma_free

    1 /*      $OpenBSD: glxsb.c,v 1.8 2007/08/07 09:48:23 markus Exp $        */
    3 /*
    4  * Copyright (c) 2006 Tom Cosgrove <tom@openbsd.org>
    5  * Copyright (c) 2003, 2004 Theo de Raadt
    6  * Copyright (c) 2003 Jason Wright
    7  *
    8  * Permission to use, copy, modify, and distribute this software for any
    9  * purpose with or without fee is hereby granted, provided that the above
   10  * copyright notice and this permission notice appear in all copies.
   11  *
   12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   19  */
   21 /*
   22  * Driver for the security block on the AMD Geode LX processors
   23  * http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33234d_lx_ds.pdf
   24  */
   26 #include <sys/cdefs.h>
   27 #include <sys/param.h>
   28 #include <sys/systm.h>
   29 #include <sys/device.h>
   30 #include <sys/malloc.h>
   31 #include <sys/mbuf.h>
   32 #include <sys/types.h>
   33 #include <sys/timeout.h>
   35 #include <machine/bus.h>
   36 #include <machine/pctr.h>
   38 #include <dev/rndvar.h>
   39 #include <dev/pci/pcivar.h>
   40 #include <dev/pci/pcidevs.h>
   42 #ifdef CRYPTO
   43 #include <crypto/cryptodev.h>
   44 #include <crypto/rijndael.h>
   45 #include <crypto/xform.h>
   46 #include <crypto/cryptosoft.h>
   47 #endif
   49 #define SB_GLD_MSR_CAP          0x58002000      /* RO - Capabilities */
   50 #define SB_GLD_MSR_CONFIG       0x58002001      /* RW - Master Config */
   51 #define SB_GLD_MSR_SMI          0x58002002      /* RW - SMI */
   52 #define SB_GLD_MSR_ERROR        0x58002003      /* RW - Error */
   53 #define SB_GLD_MSR_PM           0x58002004      /* RW - Power Mgmt */
   54 #define SB_GLD_MSR_DIAG         0x58002005      /* RW - Diagnostic */
   55 #define SB_GLD_MSR_CTRL         0x58002006      /* RW - Security Block Cntrl */
   57                                                 /* For GLD_MSR_CTRL: */
   58 #define SB_GMC_DIV0             0x0000          /* AES update divisor values */
   59 #define SB_GMC_DIV1             0x0001
   60 #define SB_GMC_DIV2             0x0002
   61 #define SB_GMC_DIV3             0x0003
   62 #define SB_GMC_DIV_MASK         0x0003
   63 #define SB_GMC_SBI              0x0004          /* AES swap bits */
   64 #define SB_GMC_SBY              0x0008          /* AES swap bytes */
   65 #define SB_GMC_TW               0x0010          /* Time write (EEPROM) */
   66 #define SB_GMC_T_SEL0           0x0000          /* RNG post-proc: none */
   67 #define SB_GMC_T_SEL1           0x0100          /* RNG post-proc: LFSR */
   68 #define SB_GMC_T_SEL2           0x0200          /* RNG post-proc: whitener */
   69 #define SB_GMC_T_SEL3           0x0300          /* RNG LFSR+whitener */
   70 #define SB_GMC_T_SEL_MASK       0x0300
   71 #define SB_GMC_T_NE             0x0400          /* Noise (generator) Enable */
   72 #define SB_GMC_T_TM             0x0800          /* RNG test mode */
   73                                                 /*     (deterministic) */
   75 /* Security Block configuration/control registers (offsets from base) */
   77 #define SB_CTL_A                0x0000          /* RW - SB Control A */
   78 #define SB_CTL_B                0x0004          /* RW - SB Control B */
   79 #define SB_AES_INT              0x0008          /* RW - SB AES Interrupt */
   80 #define SB_SOURCE_A             0x0010          /* RW - Source A */
   81 #define SB_DEST_A               0x0014          /* RW - Destination A */
   82 #define SB_LENGTH_A             0x0018          /* RW - Length A */
   83 #define SB_SOURCE_B             0x0020          /* RW - Source B */
   84 #define SB_DEST_B               0x0024          /* RW - Destination B */
   85 #define SB_LENGTH_B             0x0028          /* RW - Length B */
   86 #define SB_WKEY                 0x0030          /* WO - Writable Key 0-3 */
   87 #define SB_WKEY_0               0x0030          /* WO - Writable Key 0 */
   88 #define SB_WKEY_1               0x0034          /* WO - Writable Key 1 */
   89 #define SB_WKEY_2               0x0038          /* WO - Writable Key 2 */
   90 #define SB_WKEY_3               0x003C          /* WO - Writable Key 3 */
   91 #define SB_CBC_IV               0x0040          /* RW - CBC IV 0-3 */
   92 #define SB_CBC_IV_0             0x0040          /* RW - CBC IV 0 */
   93 #define SB_CBC_IV_1             0x0044          /* RW - CBC IV 1 */
   94 #define SB_CBC_IV_2             0x0048          /* RW - CBC IV 2 */
   95 #define SB_CBC_IV_3             0x004C          /* RW - CBC IV 3 */
   96 #define SB_RANDOM_NUM           0x0050          /* RW - Random Number */
   97 #define SB_RANDOM_NUM_STATUS    0x0054          /* RW - Random Number Status */
   98 #define SB_EEPROM_COMM          0x0800          /* RW - EEPROM Command */
   99 #define SB_EEPROM_ADDR          0x0804          /* RW - EEPROM Address */
  100 #define SB_EEPROM_DATA          0x0808          /* RW - EEPROM Data */
  101 #define SB_EEPROM_SEC_STATE     0x080C          /* RW - EEPROM Security State */
  103                                                 /* For SB_CTL_A and _B */
  104 #define SB_CTL_ST               0x0001          /* Start operation (enc/dec) */
  105 #define SB_CTL_ENC              0x0002          /* Encrypt (0 is decrypt) */
  106 #define SB_CTL_DEC              0x0000          /* Decrypt */
  107 #define SB_CTL_WK               0x0004          /* Use writable key (we set) */
  108 #define SB_CTL_DC               0x0008          /* Destination coherent */
  109 #define SB_CTL_SC               0x0010          /* Source coherent */
  110 #define SB_CTL_CBC              0x0020          /* CBC (0 is ECB) */
  112                                                 /* For SB_AES_INT */
  113 #define SB_AI_DISABLE_AES_A     0x0001          /* Disable AES A compl int */
  114 #define SB_AI_ENABLE_AES_A      0x0000          /* Enable AES A compl int */
  115 #define SB_AI_DISABLE_AES_B     0x0002          /* Disable AES B compl int */
  116 #define SB_AI_ENABLE_AES_B      0x0000          /* Enable AES B compl int */
  117 #define SB_AI_DISABLE_EEPROM    0x0004          /* Disable EEPROM op comp int */
  118 #define SB_AI_ENABLE_EEPROM     0x0000          /* Enable EEPROM op compl int */
  119 #define SB_AI_AES_A_COMPLETE    0x0100          /* AES A operation complete */
  120 #define SB_AI_AES_B_COMPLETE    0x0200          /* AES B operation complete */
  121 #define SB_AI_EEPROM_COMPLETE   0x0400          /* EEPROM operation complete */
  123 #define SB_RNS_TRNG_VALID       0x0001          /* in SB_RANDOM_NUM_STATUS */
  125 #define SB_MEM_SIZE             0x0810          /* Size of memory block */
  127 #define SB_AES_ALIGN            0x0010          /* Source and dest buffers */
  128                                                 /* must be 16-byte aligned */
  129 #define SB_AES_BLOCK_SIZE       0x0010
  131 /*
  132  * The Geode LX security block AES acceleration doesn't perform scatter-
  133  * gather: it just takes source and destination addresses.  Therefore the
  134  * plain- and ciphertexts need to be contiguous.  To this end, we allocate
  135  * a buffer for both, and accept the overhead of copying in and out.  If
  136  * the number of bytes in one operation is bigger than allowed for by the
  137  * buffer (buffer is twice the size of the max length, as it has both input
  138  * and output) then we have to perform multiple encryptions/decryptions.
  139  */
  140 #define GLXSB_MAX_AES_LEN       16384
  142 #ifdef CRYPTO
  143 struct glxsb_dma_map {
bus_dmamap_t            dma_map;
bus_dma_segment_t       dma_seg;
  146         int                     dma_nsegs;
  147         int                     dma_size;
caddr_t                 dma_vaddr;
uint32_t                dma_paddr;
  150 };
  151 struct glxsb_session {
uint32_t        ses_key[4];
uint8_t         ses_iv[SB_AES_BLOCK_SIZE];
  154         int             ses_klen;
  155         int             ses_used;
  156         struct swcr_data *ses_swd;
  157 };
  158 #endif /* CRYPTO */
  160 struct glxsb_softc {
  161         struct device           sc_dev;
bus_space_tag_t         sc_iot;
bus_space_handle_t      sc_ioh;
  164         struct timeout          sc_to;
  166 #ifdef CRYPTO
bus_dma_tag_t           sc_dmat;
  168         struct glxsb_dma_map    sc_dma;
int32_t                 sc_cid;
  170         int                     sc_nsessions;
  171         struct glxsb_session    *sc_sessions;
  172 #endif /* CRYPTO */
  173 };
  175 int     glxsb_match(struct device *, void *, void *);
  176 void    glxsb_attach(struct device *, struct device *, void *);
  177 void    glxsb_rnd(void *);
  179 struct cfattach glxsb_ca = {
  180         sizeof(struct glxsb_softc), glxsb_match, glxsb_attach
  181 };
  183 struct cfdriver glxsb_cd = {
NULL, "glxsb", DV_DULL
  185 };
  188 #ifdef CRYPTO
  190 #define GLXSB_SESSION(sid)              ((sid) & 0x0fffffff)
  191 #define GLXSB_SID(crd,ses)              (((crd) << 28) | ((ses) & 0x0fffffff))
  193 static struct glxsb_softc *glxsb_sc;
  194 extern int i386_has_xcrypt;
  196 int glxsb_crypto_setup(struct glxsb_softc *);
  197 int glxsb_crypto_newsession(uint32_t *, struct cryptoini *);
  198 int glxsb_crypto_process(struct cryptop *);
  199 int glxsb_crypto_freesession(uint64_t);
  200 static __inline void glxsb_aes(struct glxsb_softc *, uint32_t, uint32_t,
uint32_t, void *, int, void *);
  203 int glxsb_dma_alloc(struct glxsb_softc *, int, struct glxsb_dma_map *);
  204 void glxsb_dma_pre_op(struct glxsb_softc *, struct glxsb_dma_map *);
  205 void glxsb_dma_post_op(struct glxsb_softc *, struct glxsb_dma_map *);
  206 void glxsb_dma_free(struct glxsb_softc *, struct glxsb_dma_map *);
  208 #endif /* CRYPTO */
  211 int
glxsb_match(struct device *parent, void *match, void *aux)
  213 {
  214         struct pci_attach_args *pa = aux;
  216         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_GEODE_LX_CRYPTO)
  218                 return (1);
  220         return (0);
  221 }
  223 void
glxsb_attach(struct device *parent, struct device *self, void *aux)
  225 {
  226         struct glxsb_softc *sc = (void *) self;
  227         struct pci_attach_args *pa = aux;
bus_addr_t membase;
bus_size_t memsize;
uint64_t msr;
  231 #ifdef CRYPTO
uint32_t intr;
  233 #endif
msr = rdmsr(SB_GLD_MSR_CAP);
  236         if ((msr & 0xFFFF00) != 0x130400) {
printf(": unknown ID 0x%x\n", (int) ((msr & 0xFFFF00) >> 16));
  238                 return;
  239         }
  241         /* printf(": revision %d", (int) (msr & 0xFF)); */
  243         /* Map in the security block configuration/control registers */
  244         if (pci_mapreg_map(pa, PCI_MAPREG_START,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_iot,
  246             &sc->sc_ioh, &membase, &memsize, SB_MEM_SIZE)) {
printf(": can't find mem space\n");
  248                 return;
  249         }
  251         /*
  252          * Configure the Security Block.
  253          *
  254          * We want to enable the noise generator (T_NE), and enable the
  255          * linear feedback shift register and whitener post-processing
  256          * (T_SEL = 3).  Also ensure that test mode (deterministic values)
  257          * is disabled.
  258          */
msr = rdmsr(SB_GLD_MSR_CTRL);
msr &= ~(SB_GMC_T_TM | SB_GMC_T_SEL_MASK);
msr |= SB_GMC_T_NE | SB_GMC_T_SEL3;
  262 #if 0
msr |= SB_GMC_SBI | SB_GMC_SBY;         /* for AES, if necessary */
  264 #endif
wrmsr(SB_GLD_MSR_CTRL, msr);
  267         /* Install a periodic collector for the "true" (AMD's word) RNG */
timeout_set(&sc->sc_to, glxsb_rnd, sc);
glxsb_rnd(sc);
printf(": RNG");
  272 #ifdef CRYPTO
  273         /* We don't have an interrupt handler, so disable completion INTs */
intr = SB_AI_DISABLE_AES_A | SB_AI_DISABLE_AES_B |
SB_AI_DISABLE_EEPROM | SB_AI_AES_A_COMPLETE |
SB_AI_AES_B_COMPLETE | SB_AI_EEPROM_COMPLETE;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_AES_INT, intr);
sc->sc_dmat = pa->pa_dmat;
  281         if (glxsb_crypto_setup(sc))
printf(" AES");
  283 #endif
printf("\n");
  286 }
  288 void
glxsb_rnd(void *v)
  290 {
  291         struct glxsb_softc *sc = v;
uint32_t status, value;
  293         extern int hz;
status = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SB_RANDOM_NUM_STATUS);
  296         if (status & SB_RNS_TRNG_VALID) {
value = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SB_RANDOM_NUM);
add_true_randomness(value);
  299         }
timeout_add(&sc->sc_to, (hz > 100) ? (hz / 100) : 1);
  302 }
  304 #ifdef CRYPTO
  305 int
glxsb_crypto_setup(struct glxsb_softc *sc)
  307 {
  308         int algs[CRYPTO_ALGORITHM_MAX + 1];
  310         /* Allocate a contiguous DMA-able buffer to work in */
  311         if (glxsb_dma_alloc(sc, GLXSB_MAX_AES_LEN * 2, &sc->sc_dma) != 0)
  312                 return 0;
bzero(algs, sizeof(algs));
algs[CRYPTO_AES_CBC] = CRYPTO_ALG_FLAG_SUPPORTED;
algs[CRYPTO_MD5_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED;
algs[CRYPTO_SHA1_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED;
algs[CRYPTO_RIPEMD160_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED;
algs[CRYPTO_SHA2_256_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED;
algs[CRYPTO_SHA2_384_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED;
algs[CRYPTO_SHA2_512_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED;
sc->sc_cid = crypto_get_driverid(0);
  324         if (sc->sc_cid < 0)
  325                 return 0;
crypto_register(sc->sc_cid, algs, glxsb_crypto_newsession,
glxsb_crypto_freesession, glxsb_crypto_process);
sc->sc_nsessions = 0;
glxsb_sc = sc;
  334         return 1;
  335 }
  337 int
glxsb_crypto_newsession(uint32_t *sidp, struct cryptoini *cri)
  339 {
  340         struct glxsb_softc *sc = glxsb_sc;
  341         struct glxsb_session *ses = NULL;
  342         struct auth_hash        *axf;
  343         struct cryptoini        *c;
  344         struct swcr_data        *swd;
  345         int sesn, i;
  347         if (sc == NULL || sidp == NULL || cri == NULL)
  348                 return (EINVAL);
  350         for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
  351                 if (sc->sc_sessions[sesn].ses_used == 0) {
ses = &sc->sc_sessions[sesn];
  353                         break;
  354                 }
  355         }
  357         if (ses == NULL) {
sesn = sc->sc_nsessions;
ses = malloc((sesn + 1) * sizeof(*ses), M_DEVBUF, M_NOWAIT);
  360                 if (ses == NULL)
  361                         return (ENOMEM);
  362                 if (sesn != 0) {
bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses));
bzero(sc->sc_sessions, sesn * sizeof(*ses));
free(sc->sc_sessions, M_DEVBUF);
  366                 }
sc->sc_sessions = ses;
ses = &sc->sc_sessions[sesn];
sc->sc_nsessions++;
  370         }
bzero(ses, sizeof(*ses));
ses->ses_used = 1;
  375         for (c = cri; c != NULL; c = c->cri_next) {
  376                 switch (c->cri_alg) {
  377                 case CRYPTO_AES_CBC:
  378                         if (c->cri_klen != 128) {
glxsb_crypto_freesession(sesn);
  380                                 return (EINVAL);
  381                         }
get_random_bytes(ses->ses_iv, sizeof(ses->ses_iv));
ses->ses_klen = c->cri_klen;
  386                         /* Copy the key (Geode LX wants the primary key only) */
bcopy(c->cri_key, ses->ses_key, sizeof(ses->ses_key));
  388                         break;
  390                 case CRYPTO_MD5_HMAC:
axf = &auth_hash_hmac_md5_96;
  392                         goto authcommon;
  393                 case CRYPTO_SHA1_HMAC:
axf = &auth_hash_hmac_sha1_96;
  395                         goto authcommon;
  396                 case CRYPTO_RIPEMD160_HMAC:
axf = &auth_hash_hmac_ripemd_160_96;
  398                         goto authcommon;
  399                 case CRYPTO_SHA2_256_HMAC:
axf = &auth_hash_hmac_sha2_256_96;
  401                         goto authcommon;
  402                 case CRYPTO_SHA2_384_HMAC:
axf = &auth_hash_hmac_sha2_384_96;
  404                         goto authcommon;
  405                 case CRYPTO_SHA2_512_HMAC:
axf = &auth_hash_hmac_sha2_512_96;
authcommon:
MALLOC(swd, struct swcr_data *,
  409                             sizeof(struct swcr_data), M_CRYPTO_DATA,
M_NOWAIT);
  411                         if (swd == NULL) {
glxsb_crypto_freesession(sesn);
  413                                 return (ENOMEM);
  414                         }
bzero(swd, sizeof(struct swcr_data));
ses->ses_swd = swd;
swd->sw_ictx = malloc(axf->ctxsize, M_CRYPTO_DATA,
M_NOWAIT);
  420                         if (swd->sw_ictx == NULL) {
glxsb_crypto_freesession(sesn);
  422                                 return (ENOMEM);
  423                         }
swd->sw_octx = malloc(axf->ctxsize, M_CRYPTO_DATA,
M_NOWAIT);
  427                         if (swd->sw_octx == NULL) {
glxsb_crypto_freesession(sesn);
  429                                 return (ENOMEM);
  430                         }
  432                         for (i = 0; i < c->cri_klen / 8; i++)
c->cri_key[i] ^= HMAC_IPAD_VAL;
axf->Init(swd->sw_ictx);
axf->Update(swd->sw_ictx, c->cri_key, c->cri_klen / 8);
axf->Update(swd->sw_ictx, hmac_ipad_buffer,
HMAC_BLOCK_LEN - (c->cri_klen / 8));
  440                         for (i = 0; i < c->cri_klen / 8; i++)
c->cri_key[i] ^= (HMAC_IPAD_VAL ^
HMAC_OPAD_VAL);
axf->Init(swd->sw_octx);
axf->Update(swd->sw_octx, c->cri_key, c->cri_klen / 8);
axf->Update(swd->sw_octx, hmac_opad_buffer,
HMAC_BLOCK_LEN - (c->cri_klen / 8));
  449                         for (i = 0; i < c->cri_klen / 8; i++)
c->cri_key[i] ^= HMAC_OPAD_VAL;
swd->sw_axf = axf;
swd->sw_alg = c->cri_alg;
  455                         break;
  456                 default:
glxsb_crypto_freesession(sesn);
  458                         return (EINVAL);
  459                 }
  460         }
  462         *sidp = GLXSB_SID(0, sesn);
  463         return (0);
  464 }
  466 int
glxsb_crypto_freesession(uint64_t tid)
  468 {
  469         struct glxsb_softc *sc = glxsb_sc;
  470         struct swcr_data *swd;
  471         struct auth_hash *axf;
  472         int sesn;
uint32_t sid = ((uint32_t)tid) & 0xffffffff;
  475         if (sc == NULL)
  476                 return (EINVAL);
sesn = GLXSB_SESSION(sid);
  478         if (sesn >= sc->sc_nsessions)
  479                 return (EINVAL);
  480         if (sc->sc_sessions[sesn].ses_swd) {
swd = sc->sc_sessions[sesn].ses_swd;
axf = swd->sw_axf;
  484                 if (swd->sw_ictx) {
bzero(swd->sw_ictx, axf->ctxsize);
free(swd->sw_ictx, M_CRYPTO_DATA);
  487                 }
  488                 if (swd->sw_octx) {
bzero(swd->sw_octx, axf->ctxsize);
free(swd->sw_octx, M_CRYPTO_DATA);
  491                 }
FREE(swd, M_CRYPTO_DATA);
  493         }
bzero(&sc->sc_sessions[sesn], sizeof(sc->sc_sessions[sesn]));
  495         return (0);
  496 }
  498 /*
  499  * Must be called at splnet() or higher
  500  */
  501 static __inline void
glxsb_aes(struct glxsb_softc *sc, uint32_t control, uint32_t psrc,
uint32_t pdst, void *key, int len, void *iv)
  504 {
uint32_t status;
  506         int i;
  508         if (len & 0xF) {
printf("%s: len must be a multiple of 16 (not %d)\n",
sc->sc_dev.dv_xname, len);
  511                 return;
  512         }
  514         /* Set the source */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_SOURCE_A, psrc);
  517         /* Set the destination address */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_DEST_A, pdst);
  520         /* Set the data length */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_LENGTH_A, len);
  523         /* Set the IV */
  524         if (iv != NULL) {
bus_space_write_region_4(sc->sc_iot, sc->sc_ioh,
SB_CBC_IV, iv, 4);
control |= SB_CTL_CBC;
  528         }
  530         /* Set the key */
bus_space_write_region_4(sc->sc_iot, sc->sc_ioh, SB_WKEY, key, 4);
  533         /* Ask the security block to do it */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, SB_CTL_A,
control | SB_CTL_WK | SB_CTL_DC | SB_CTL_SC | SB_CTL_ST);
  537         /*
  538          * Now wait until it is done.
  539          *
  540          * We do a busy wait.  Obviously the number of iterations of
  541          * the loop required to perform the AES operation depends upon
  542          * the number of bytes to process.
  543          *
  544          * On a 500 MHz Geode LX we see
  545          *
  546          *      length (bytes)  typical max iterations
  547          *          16             12
  548          *          64             22
  549          *         256             59
  550          *        1024            212
  551          *        8192          1,537
  552          *
  553          * Since we have a maximum size of operation defined in
  554          * GLXSB_MAX_AES_LEN, we use this constant to decide how long
  555          * to wait.  Allow an order of magnitude longer than it should
  556          * really take, just in case.
  557          */
  558         for (i = 0; i < GLXSB_MAX_AES_LEN * 10; i++) {
status = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SB_CTL_A);
  561                 if ((status & SB_CTL_ST) == 0)          /* Done */
  562                         return;
  563         }
printf("%s: operation failed to complete\n", sc->sc_dev.dv_xname);
  566 }
  568 static int
glxsb_crypto_swauth(struct cryptop *crp, struct cryptodesc *crd,
  570     struct swcr_data *sw, caddr_t buf)
  571 {
  572         int     type;
  574         if (crp->crp_flags & CRYPTO_F_IMBUF)
type = CRYPTO_BUF_MBUF;
  576         else
type = CRYPTO_BUF_IOV;
  579         return (swcr_authcompute(crp, crd, sw, buf, type));
  580 }
  582 static int
glxsb_crypto_encdec(struct cryptop *crp, struct cryptodesc *crd,
  584     struct glxsb_session *ses, struct glxsb_softc *sc, caddr_t buf)
  585 {
  586         char *op_src, *op_dst;
uint32_t op_psrc, op_pdst;
uint8_t op_iv[SB_AES_BLOCK_SIZE], *piv;
  589         int err = 0;
  590         int len, tlen, xlen;
  591         int offset;
uint32_t control;
  594         if (crd == NULL || (crd->crd_len % SB_AES_BLOCK_SIZE) != 0) {
err = EINVAL;
  596                 goto out;
  597         }
  599         /* How much of our buffer will we need to use? */
xlen = crd->crd_len > GLXSB_MAX_AES_LEN ?
GLXSB_MAX_AES_LEN : crd->crd_len;
  603         /*
  604          * XXX Check if we can have input == output on Geode LX.
  605          * XXX In the meantime, use two separate (adjacent) buffers.
  606          */
op_src = sc->sc_dma.dma_vaddr;
op_dst = sc->sc_dma.dma_vaddr + xlen;
op_psrc = sc->sc_dma.dma_paddr;
op_pdst = sc->sc_dma.dma_paddr + xlen;
  613         if (crd->crd_flags & CRD_F_ENCRYPT) {
control = SB_CTL_ENC;
  615                 if (crd->crd_flags & CRD_F_IV_EXPLICIT)
bcopy(crd->crd_iv, op_iv, sizeof(op_iv));
  617                 else
bcopy(ses->ses_iv, op_iv, sizeof(op_iv));
  620                 if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) {
  621                         if (crp->crp_flags & CRYPTO_F_IMBUF)
m_copyback((struct mbuf *)crp->crp_buf,
crd->crd_inject, sizeof(op_iv), op_iv);
  624                         else if (crp->crp_flags & CRYPTO_F_IOV)
cuio_copyback((struct uio *)crp->crp_buf,
crd->crd_inject, sizeof(op_iv), op_iv);
  627                         else
bcopy(op_iv,
crp->crp_buf + crd->crd_inject, sizeof(op_iv));
  630                 }
  631         } else {
control = SB_CTL_DEC;
  633                 if (crd->crd_flags & CRD_F_IV_EXPLICIT)
bcopy(crd->crd_iv, op_iv, sizeof(op_iv));
  635                 else {
  636                         if (crp->crp_flags & CRYPTO_F_IMBUF)
m_copydata((struct mbuf *)crp->crp_buf,
crd->crd_inject, sizeof(op_iv), op_iv);
  639                         else if (crp->crp_flags & CRYPTO_F_IOV)
cuio_copydata((struct uio *)crp->crp_buf,
crd->crd_inject, sizeof(op_iv), op_iv);
  642                         else
bcopy(crp->crp_buf + crd->crd_inject,
op_iv, sizeof(op_iv));
  645                 }
  646         }
offset = 0;
tlen = crd->crd_len;
piv = op_iv;
  652         /* Process the data in GLXSB_MAX_AES_LEN chunks */
  653         while (tlen > 0) {
len = (tlen > GLXSB_MAX_AES_LEN) ? GLXSB_MAX_AES_LEN : tlen;
  656                 if (crp->crp_flags & CRYPTO_F_IMBUF)
m_copydata((struct mbuf *)crp->crp_buf,
crd->crd_skip + offset, len, op_src);
  659                 else if (crp->crp_flags & CRYPTO_F_IOV)
cuio_copydata((struct uio *)crp->crp_buf,
crd->crd_skip + offset, len, op_src);
  662                 else
bcopy(crp->crp_buf + crd->crd_skip + offset, op_src,
len);
glxsb_dma_pre_op(sc, &sc->sc_dma);
glxsb_aes(sc, control, op_psrc, op_pdst, ses->ses_key,
len, op_iv);
glxsb_dma_post_op(sc, &sc->sc_dma);
  673                 if (crp->crp_flags & CRYPTO_F_IMBUF)
m_copyback((struct mbuf *)crp->crp_buf,
crd->crd_skip + offset, len, op_dst);
  676                 else if (crp->crp_flags & CRYPTO_F_IOV)
cuio_copyback((struct uio *)crp->crp_buf,
crd->crd_skip + offset, len, op_dst);
  679                 else
bcopy(op_dst, crp->crp_buf + crd->crd_skip + offset,
len);
offset += len;
tlen -= len;
  686                 if (tlen <= 0) {        /* Ideally, just == 0 */
  687                         /* Finished - put the IV in session IV */
piv = ses->ses_iv;
  689                 }
  691                 /*
  692                  * Copy out last block for use as next iteration/session IV.
  693                  *
  694                  * piv is set to op_iv[] before the loop starts, but is
  695                  * set to ses->ses_iv if we're going to exit the loop this
  696                  * time.
  697                  */
  698                 if (crd->crd_flags & CRD_F_ENCRYPT) {
bcopy(op_dst + len - sizeof(op_iv), piv, sizeof(op_iv));
  700                 } else {
  701                         /* Decryption, only need this if another iteration */
  702                         if (tlen > 0) {
bcopy(op_src + len - sizeof(op_iv), piv,
  704                                     sizeof(op_iv));
  705                         }
  706                 }
  707         }
  709         /* All AES processing has now been done. */
bzero(sc->sc_dma.dma_vaddr, xlen * 2);
out:
  713         return (err);
  714 }
  716 int
glxsb_crypto_process(struct cryptop *crp)
  718 {
  719         struct glxsb_softc *sc = glxsb_sc;
  720         struct glxsb_session *ses;
  721         struct cryptodesc *crd;
  722         int sesn,err = 0;
  723         int s;
s = splnet();
  727         if (crp == NULL || crp->crp_callback == NULL) {
err = EINVAL;
  729                 goto out;
  730         }
crd = crp->crp_desc;
  732         if (crd == NULL) {
err = EINVAL;
  734                 goto out;
  735         }
sesn = GLXSB_SESSION(crp->crp_sid);
  738         if (sesn >= sc->sc_nsessions) {
err = EINVAL;
  740                 goto out;
  741         }
ses = &sc->sc_sessions[sesn];
  744         for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
  745                 switch (crd->crd_alg) {
  746                 case CRYPTO_AES_CBC:
  747                         if ((err = glxsb_crypto_encdec(crp, crd, ses, sc,
crp->crp_buf)) != 0)
  749                                 goto out;
  750                         break;
  752                 case CRYPTO_MD5_HMAC:
  753                 case CRYPTO_SHA1_HMAC:
  754                 case CRYPTO_RIPEMD160_HMAC:
  755                 case CRYPTO_SHA2_256_HMAC:
  756                 case CRYPTO_SHA2_384_HMAC:
  757                 case CRYPTO_SHA2_512_HMAC:
  758                         if ((err = glxsb_crypto_swauth(crp, crd, ses->ses_swd,
crp->crp_buf)) != 0)
  760                                 goto out;
  761                         break;
  763                 default:
err = EINVAL;
  765                         goto out;
  766                 }
  767         }
out:
crp->crp_etype = err;
crypto_done(crp);
splx(s);
  773         return (err);
  774 }
  776 int
glxsb_dma_alloc(struct glxsb_softc *sc, int size, struct glxsb_dma_map *dma)
  778 {
  779         int rc;
dma->dma_nsegs = 1;
dma->dma_size = size;
rc = bus_dmamap_create(sc->sc_dmat, size, dma->dma_nsegs, size,
  785             0, BUS_DMA_NOWAIT, &dma->dma_map);
  786         if (rc != 0) {
printf("%s: couldn't create DMA map for %d bytes (%d)\n",
sc->sc_dev.dv_xname, size, rc);
  790                 goto fail0;
  791         }
rc = bus_dmamem_alloc(sc->sc_dmat, size, SB_AES_ALIGN, 0,
  794             &dma->dma_seg, dma->dma_nsegs, &dma->dma_nsegs, BUS_DMA_NOWAIT);
  795         if (rc != 0) {
printf("%s: couldn't allocate DMA memory of %d bytes (%d)\n",
sc->sc_dev.dv_xname, size, rc);
  799                 goto fail1;
  800         }
rc = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, 1, size,
  803             &dma->dma_vaddr, BUS_DMA_NOWAIT);
  804         if (rc != 0) {
printf("%s: couldn't map DMA memory for %d bytes (%d)\n",
sc->sc_dev.dv_xname, size, rc);
  808                 goto fail2;
  809         }
rc = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr,
size, NULL, BUS_DMA_NOWAIT);
  813         if (rc != 0) {
printf("%s: couldn't load DMA memory for %d bytes (%d)\n",
sc->sc_dev.dv_xname, size, rc);
  817                 goto fail3;
  818         }
dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr;
  822         return 0;
fail3:
bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size);
fail2:
bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nsegs);
fail1:
bus_dmamap_destroy(sc->sc_dmat, dma->dma_map);
fail0:
  831         return rc;
  832 }
  834 void
glxsb_dma_pre_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma)
  836 {
bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 0, dma->dma_size,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  839 }
  841 void
glxsb_dma_post_op(struct glxsb_softc *sc, struct glxsb_dma_map *dma)
  843 {
bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 0, dma->dma_size,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
  846 }
  848 void
glxsb_dma_free(struct glxsb_softc *sc, struct glxsb_dma_map *dma)
  850 {
bus_dmamap_unload(sc->sc_dmat, dma->dma_map);
bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size);
bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nsegs);
bus_dmamap_destroy(sc->sc_dmat, dma->dma_map);
  855 }
  857 #endif /* CRYPTO */