This source file includes following definitions.
- ehci_soft_qtd_t
- ehci_soft_qh_t
- ehci_softc_t
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40 typedef struct ehci_soft_qtd {
41 ehci_qtd_t qtd;
42 struct ehci_soft_qtd *nextqtd;
43 ehci_physaddr_t physaddr;
44 usbd_xfer_handle xfer;
45 LIST_ENTRY(ehci_soft_qtd) hnext;
46 u_int16_t len;
47 } ehci_soft_qtd_t;
48 #define EHCI_SQTD_SIZE ((sizeof (struct ehci_soft_qtd) + EHCI_QTD_ALIGN - 1) / EHCI_QTD_ALIGN * EHCI_QTD_ALIGN)
49 #define EHCI_SQTD_CHUNK (EHCI_PAGE_SIZE / EHCI_SQTD_SIZE)
50
51 typedef struct ehci_soft_qh {
52 ehci_qh_t qh;
53 struct ehci_soft_qh *next;
54 struct ehci_soft_qh *prev;
55 struct ehci_soft_qtd *sqtd;
56 ehci_physaddr_t physaddr;
57 int islot;
58 } ehci_soft_qh_t;
59 #define EHCI_SQH_SIZE ((sizeof (struct ehci_soft_qh) + EHCI_QH_ALIGN - 1) / EHCI_QH_ALIGN * EHCI_QH_ALIGN)
60 #define EHCI_SQH_CHUNK (EHCI_PAGE_SIZE / EHCI_SQH_SIZE)
61
62 struct ehci_xfer {
63 struct usbd_xfer xfer;
64 struct usb_task abort_task;
65 LIST_ENTRY(ehci_xfer) inext;
66 ehci_soft_qtd_t *sqtdstart;
67 ehci_soft_qtd_t *sqtdend;
68 u_int32_t ehci_xfer_flags;
69 #ifdef DIAGNOSTIC
70 int isdone;
71 #endif
72 };
73 #define EHCI_XFER_ABORTING 0x0001
74 #define EHCI_XFER_ABORTWAIT 0x0002
75
76 #define EXFER(xfer) ((struct ehci_xfer *)(xfer))
77
78
79 struct ehci_soft_islot {
80 ehci_soft_qh_t *sqh;
81 };
82
83 #define EHCI_FRAMELIST_MAXCOUNT 1024
84 #define EHCI_IPOLLRATES 8
85 #define EHCI_INTRQHS ((1 << EHCI_IPOLLRATES) - 1)
86 #define EHCI_IQHIDX(lev, pos) \
87 ((((pos) & ((1 << (lev)) - 1)) | (1 << (lev))) - 1)
88 #define EHCI_ILEV_IVAL(lev) (1 << (lev))
89
90
91 #define EHCI_HASH_SIZE 128
92 #define EHCI_COMPANION_MAX 8
93
94 typedef struct ehci_softc {
95 struct usbd_bus sc_bus;
96 bus_space_tag_t iot;
97 bus_space_handle_t ioh;
98 bus_size_t sc_size;
99 u_int sc_offs;
100 int sc_flags;
101 #define EHCIF_DROPPED_INTR_WORKAROUND 0x01
102
103 char sc_vendor[16];
104 int sc_id_vendor;
105
106 u_int32_t sc_cmd;
107 void *sc_powerhook;
108 void *sc_shutdownhook;
109
110 usb_dma_t sc_fldma;
111 ehci_link_t *sc_flist;
112 u_int sc_flsize;
113 u_int sc_rand;
114
115 struct ehci_soft_islot sc_islots[EHCI_INTRQHS];
116
117 LIST_HEAD(, ehci_xfer) sc_intrhead;
118
119 ehci_soft_qh_t *sc_freeqhs;
120 ehci_soft_qtd_t *sc_freeqtds;
121
122 int sc_noport;
123 u_int8_t sc_addr;
124 u_int8_t sc_conf;
125 usbd_xfer_handle sc_intrxfer;
126 char sc_isreset;
127 char sc_softwake;
128
129 u_int32_t sc_eintrs;
130 ehci_soft_qh_t *sc_async_head;
131
132 SIMPLEQ_HEAD(, usbd_xfer) sc_free_xfers;
133
134 struct rwlock sc_doorbell_lock;
135
136 struct timeout sc_tmo_pcd;
137 struct timeout sc_tmo_intrlist;
138
139 struct device *sc_child;
140
141 char sc_dying;
142 } ehci_softc_t;
143
144 #define EREAD1(sc, a) bus_space_read_1((sc)->iot, (sc)->ioh, (a))
145 #define EREAD2(sc, a) bus_space_read_2((sc)->iot, (sc)->ioh, (a))
146 #define EREAD4(sc, a) bus_space_read_4((sc)->iot, (sc)->ioh, (a))
147 #define EWRITE1(sc, a, x) bus_space_write_1((sc)->iot, (sc)->ioh, (a), (x))
148 #define EWRITE2(sc, a, x) bus_space_write_2((sc)->iot, (sc)->ioh, (a), (x))
149 #define EWRITE4(sc, a, x) bus_space_write_4((sc)->iot, (sc)->ioh, (a), (x))
150 #define EOREAD1(sc, a) bus_space_read_1((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a))
151 #define EOREAD2(sc, a) bus_space_read_2((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a))
152 #define EOREAD4(sc, a) bus_space_read_4((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a))
153 #define EOWRITE1(sc, a, x) bus_space_write_1((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x))
154 #define EOWRITE2(sc, a, x) bus_space_write_2((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x))
155 #define EOWRITE4(sc, a, x) bus_space_write_4((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x))
156
157 usbd_status ehci_init(ehci_softc_t *);
158 int ehci_intr(void *);
159 int ehci_detach(ehci_softc_t *, int);
160 int ehci_activate(struct device *, enum devact);
161 void ehci_shutdown(void *);