root/dev/pci/gdt_pci.c

DEFINITIONS

1. gdt_pci_probe
2. gdt_pci_attach
3. gdt_pci_enable_intr
4. gdt_pci_copy_cmd
5. gdt_pci_get_status
6. gdt_pci_intr
7. gdt_pci_release_event
8. gdt_pci_set_sema0
9. gdt_pci_test_busy
10. gdt_pcinew_copy_cmd
11. gdt_pcinew_get_status
12. gdt_pcinew_intr
13. gdt_pcinew_release_event
14. gdt_pcinew_set_sema0
15. gdt_pcinew_test_busy
16. gdt_mpr_copy_cmd
17. gdt_mpr_get_status
18. gdt_mpr_intr
19. gdt_mpr_release_event
20. gdt_mpr_set_sema0
21. gdt_mpr_test_busy

    1 /*      $OpenBSD: gdt_pci.c,v 1.20 2006/02/24 00:04:27 brad Exp $       */
    3 /*
    4  * Copyright (c) 1999, 2000 Niklas Hallqvist.  All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   25  */
   27 /*
   28  * This driver would not have written if it was not for the hardware donations
   29  * from both ICP-Vortex and Öko.neT.  I want to thank them for their support.
   30  */
   32 #include <sys/param.h>
   33 #include <sys/systm.h>
   34 #include <sys/device.h>
   35 #include <sys/kernel.h>
   36 #include <sys/malloc.h>
   37 #include <sys/queue.h>
   39 #include <machine/bus.h>
   40 #include <machine/endian.h>
   41 #include <machine/intr.h>
   43 #include <scsi/scsi_all.h>
   44 #include <scsi/scsiconf.h>
   46 #include <dev/pci/pcidevs.h>
   47 #include <dev/pci/pcireg.h>
   48 #include <dev/pci/pcivar.h>
   50 #include <dev/ic/gdtreg.h>
   51 #include <dev/ic/gdtvar.h>
   53 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */
   54 #define GDT_PCI_PRODUCT_FC      0x200
   56 #define GDT_DEVICE_ID_MIN       0x100
   57 #define GDT_DEVICE_ID_MAX       0x2ff
   58 #define GDT_DEVICE_ID_NEWRX     0x300
   59 #define GDT_DEVICE_ID_NEWRX2    0x301
   61 /* Mapping registers for various areas */
   62 #define GDT_PCI_DPMEM           0x10
   63 #define GDT_PCINEW_IOMEM        0x10
   64 #define GDT_PCINEW_IO           0x14
   65 #define GDT_PCINEW_DPMEM        0x18
   67 /* PCI SRAM structure */
   68 #define GDT_MAGIC       0x00    /* u_int32_t, controller ID from BIOS */
   69 #define GDT_NEED_DEINIT 0x04    /* u_int16_t, switch between BIOS/driver */
   70 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */
   71 #define GDT_OS_USED     0x10    /* u_int8_t [16], OS code per service */
   72 #define GDT_FW_MAGIC    0x3c    /* u_int8_t, controller ID from firmware */
   73 #define GDT_SRAM_SZ     0x40
   75 /* DPRAM PCI controllers */
   76 #define GDT_DPR_IF      0x00    /* interface area */
   77 #define GDT_6SR         (0xff0 - GDT_SRAM_SZ)
   78 #define GDT_SEMA1       0xff1   /* volatile u_int8_t, command semaphore */
   79 #define GDT_IRQEN       0xff5   /* u_int8_t, board interrupts enable */
   80 #define GDT_EVENT       0xff8   /* u_int8_t, release event */
   81 #define GDT_IRQDEL      0xffc   /* u_int8_t, acknowledge board interrupt */
   82 #define GDT_DPRAM_SZ    0x1000
   84 /* PLX register structure (new PCI controllers) */
   85 #define GDT_CFG_REG     0x00    /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */
   86 #define GDT_SEMA0_REG   0x40    /* volatile u_int8_t, command semaphore */
   87 #define GDT_SEMA1_REG   0x41    /* volatile u_int8_t, status semaphore */
   88 #define GDT_PLX_STATUS  0x44    /* volatile u_int16_t, command status */
   89 #define GDT_PLX_SERVICE 0x46    /* u_int16_t, service */
   90 #define GDT_PLX_INFO    0x48    /* u_int32_t [2], additional info */
   91 #define GDT_LDOOR_REG   0x60    /* u_int8_t, PCI to local doorbell */
   92 #define GDT_EDOOR_REG   0x64    /* volatile u_int8_t, local to PCI doorbell */
   93 #define GDT_CONTROL0    0x68    /* u_int8_t, control0 register (unused) */
   94 #define GDT_CONTROL1    0x69    /* u_int8_t, board interrupts enable */
   95 #define GDT_PLX_SZ      0x80
   97 /* DPRAM new PCI controllers */
   98 #define GDT_IC          0x00    /* interface */
   99 #define GDT_PCINEW_6SR  (0x4000 - GDT_SRAM_SZ)
  100                                 /* SRAM structure */
  101 #define GDT_PCINEW_SZ   0x4000
  103 /* i960 register structure (PCI MPR controllers) */
  104 #define GDT_MPR_SEMA0   0x10    /* volatile u_int8_t, command semaphore */
  105 #define GDT_MPR_SEMA1   0x12    /* volatile u_int8_t, status semaphore */
  106 #define GDT_MPR_STATUS  0x14    /* volatile u_int16_t, command status */
  107 #define GDT_MPR_SERVICE 0x16    /* u_int16_t, service */
  108 #define GDT_MPR_INFO    0x18    /* u_int32_t [2], additional info */
  109 #define GDT_MPR_LDOOR   0x20    /* u_int8_t, PCI to local doorbell */
  110 #define GDT_MPR_EDOOR   0x2c    /* volatile u_int8_t, locl to PCI doorbell */
  111 #define GDT_EDOOR_EN    0x34    /* u_int8_t, board interrupts enable */
  112 #define GDT_I960_SZ     0x1000
  114 /* DPRAM PCI MPR controllers */
  115 #define GDT_I960R       0x00    /* 4KB i960 registers */
  116 #define GDT_MPR_IC      GDT_I960_SZ
  117                                 /* interface area */
  118 #define GDT_MPR_6SR     (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ)
  119                                 /* SRAM structure */
  120 #define GDT_MPR_SZ      0x4000
  122 int     gdt_pci_probe(struct device *, void *, void *);
  123 void    gdt_pci_attach(struct device *, struct device *, void *);
  124 void    gdt_pci_enable_intr(struct gdt_softc *);
  126 void    gdt_pci_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
u_int8_t gdt_pci_get_status(struct gdt_softc *);
  128 void    gdt_pci_intr(struct gdt_softc *, struct gdt_intr_ctx *);
  129 void    gdt_pci_release_event(struct gdt_softc *, struct gdt_ccb *);
  130 void    gdt_pci_set_sema0(struct gdt_softc *);
  131 int     gdt_pci_test_busy(struct gdt_softc *);
  133 void    gdt_pcinew_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
u_int8_t gdt_pcinew_get_status(struct gdt_softc *);
  135 void    gdt_pcinew_intr(struct gdt_softc *, struct gdt_intr_ctx *);
  136 void    gdt_pcinew_release_event(struct gdt_softc *, struct gdt_ccb *);
  137 void    gdt_pcinew_set_sema0(struct gdt_softc *);
  138 int     gdt_pcinew_test_busy(struct gdt_softc *);
  140 void    gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
u_int8_t gdt_mpr_get_status(struct gdt_softc *);
  142 void    gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *);
  143 void    gdt_mpr_release_event(struct gdt_softc *, struct gdt_ccb *);
  144 void    gdt_mpr_set_sema0(struct gdt_softc *);
  145 int     gdt_mpr_test_busy(struct gdt_softc *);
  147 struct cfattach gdt_pci_ca = {
  148         sizeof (struct gdt_softc), gdt_pci_probe, gdt_pci_attach
  149 };
  151 int
gdt_pci_probe(parent, match, aux)
  153         struct device *parent;
  154         void *match, *aux;
  155 {
  156         struct pci_attach_args *pa = aux;
  158         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX &&
  159             ((PCI_PRODUCT(pa->pa_id) >= GDT_DEVICE_ID_MIN &&
PCI_PRODUCT(pa->pa_id) <= GDT_DEVICE_ID_MAX) ||
PCI_PRODUCT(pa->pa_id) == GDT_DEVICE_ID_NEWRX ||
PCI_PRODUCT(pa->pa_id) == GDT_DEVICE_ID_NEWRX2))
  163                 return (1);
  164         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL &&
  165             (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GDT_RAID1 ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GDT_RAID2))
  167                 return (1);
  168         return (0);
  169 }
  171 void
gdt_pci_attach(parent, self, aux)
  173         struct device *parent, *self;
  174         void *aux;
  175 {
  176         struct pci_attach_args *pa = aux;
  177         struct gdt_softc *gdt = (void *)self;
bus_space_tag_t dpmemt, iomemt, iot;
bus_space_handle_t dpmemh, iomemh, ioh;
bus_addr_t dpmembase, iomembase, iobase;
bus_size_t dpmemsize, iomemsize, iosize;
u_int16_t prod;
u_int32_t status = 0;
  184 #define DPMEM_MAPPED            1
  185 #define IOMEM_MAPPED            2
  186 #define IO_MAPPED               4
  187 #define INTR_ESTABLISHED        8
  188         int retries;
u_int8_t protocol;
pci_intr_handle_t ih;
  191         const char *intrstr;
printf(": ");
gdt->sc_class = 0;
  196         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX) {
prod = PCI_PRODUCT(pa->pa_id);
  198                 switch (prod) {
  199                 case PCI_PRODUCT_VORTEX_GDT_60x0:
  200                 case PCI_PRODUCT_VORTEX_GDT_6000B:
gdt->sc_class = GDT_PCI;
  202                         break;
  204                 case PCI_PRODUCT_VORTEX_GDT_6x10:
  205                 case PCI_PRODUCT_VORTEX_GDT_6x20:
  206                 case PCI_PRODUCT_VORTEX_GDT_6530:
  207                 case PCI_PRODUCT_VORTEX_GDT_6550:
  208                 case PCI_PRODUCT_VORTEX_GDT_6x17:
  209                 case PCI_PRODUCT_VORTEX_GDT_6x27:
  210                 case PCI_PRODUCT_VORTEX_GDT_6537:
  211                 case PCI_PRODUCT_VORTEX_GDT_6557:
  212                 case PCI_PRODUCT_VORTEX_GDT_6x15:
  213                 case PCI_PRODUCT_VORTEX_GDT_6x25:
  214                 case PCI_PRODUCT_VORTEX_GDT_6535:
  215                 case PCI_PRODUCT_VORTEX_GDT_6555:
gdt->sc_class = GDT_PCINEW;
  217                         break;
  219                 case PCI_PRODUCT_VORTEX_GDT_6x17RP:
  220                 case PCI_PRODUCT_VORTEX_GDT_6x27RP:
  221                 case PCI_PRODUCT_VORTEX_GDT_6537RP:
  222                 case PCI_PRODUCT_VORTEX_GDT_6557RP:
  223                 case PCI_PRODUCT_VORTEX_GDT_6x11RP:
  224                 case PCI_PRODUCT_VORTEX_GDT_6x21RP:
  225                 case PCI_PRODUCT_VORTEX_GDT_6x17RD:
  226                 case PCI_PRODUCT_VORTEX_GDT_6x27RD:
  227                 case PCI_PRODUCT_VORTEX_GDT_6537RD:
  228                 case PCI_PRODUCT_VORTEX_GDT_6557RD:
  229                 case PCI_PRODUCT_VORTEX_GDT_6x11RD:
  230                 case PCI_PRODUCT_VORTEX_GDT_6x21RD:
  231                 case PCI_PRODUCT_VORTEX_GDT_6x18RD:
  232                 case PCI_PRODUCT_VORTEX_GDT_6x28RD:
  233                 case PCI_PRODUCT_VORTEX_GDT_6x38RD:
  234                 case PCI_PRODUCT_VORTEX_GDT_6x58RD:
  235                 case PCI_PRODUCT_VORTEX_GDT_6518RS:
  236                 case PCI_PRODUCT_VORTEX_GDT_7x18RN:
  237                 case PCI_PRODUCT_VORTEX_GDT_7x28RN:
  238                 case PCI_PRODUCT_VORTEX_GDT_7x38RN:
  239                 case PCI_PRODUCT_VORTEX_GDT_7x58RN:
  240                 case PCI_PRODUCT_VORTEX_GDT_6x19RD:
  241                 case PCI_PRODUCT_VORTEX_GDT_6x29RD:
  242                 case PCI_PRODUCT_VORTEX_GDT_7x19RN:
  243                 case PCI_PRODUCT_VORTEX_GDT_7x29RN:
  244                 case PCI_PRODUCT_VORTEX_GDT_7x43RN:
gdt->sc_class = GDT_MPR;
  246                 }
  248                 /* If we don't recognize it, determine class heuristically.  */
  249                 if (gdt->sc_class == 0)
gdt->sc_class = prod < 0x100 ? GDT_PCINEW : GDT_MPR;
  252                 if (prod >= GDT_PCI_PRODUCT_FC)
gdt->sc_class |= GDT_FC;
  255         } else if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
gdt->sc_class = GDT_MPR;
  257         }
  259         if (pci_mapreg_map(pa,
GDT_CLASS(gdt) == GDT_PCINEW ? GDT_PCINEW_DPMEM : GDT_PCI_DPMEM,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &dpmemt,
  262             &dpmemh, &dpmembase, &dpmemsize, 0)) {
  263                 if (pci_mapreg_map(pa,
GDT_CLASS(gdt) == GDT_PCINEW ? GDT_PCINEW_DPMEM :
GDT_PCI_DPMEM,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M, 0,
  267                     &dpmemt,&dpmemh, &dpmembase, &dpmemsize, 0)) {
printf("cannot map DPMEM\n");
  269                         goto bail_out;
  270                 }
  271         }
status |= DPMEM_MAPPED;
gdt->sc_dpmemt = dpmemt;
gdt->sc_dpmemh = dpmemh;
gdt->sc_dpmembase = dpmembase;
gdt->sc_dmat = pa->pa_dmat;
  278         /*
  279          * The GDT_PCINEW series also has two other regions to map.
  280          */
  281         if (GDT_CLASS(gdt) == GDT_PCINEW) {
  282                 if (pci_mapreg_map(pa, GDT_PCINEW_IOMEM, PCI_MAPREG_TYPE_MEM,
  283                     0, &iomemt, &iomemh, &iomembase, &iomemsize, 0)) {
printf("cannot map memory mapped I/O ports\n");
  285                         goto bail_out;
  286                 }
status |= IOMEM_MAPPED;
  289                 if (pci_mapreg_map(pa, GDT_PCINEW_IO, PCI_MAPREG_TYPE_IO, 0,
  290                     &iot, &ioh, &iobase, &iosize, 0)) {
printf("cannot map I/O ports\n");
  292                         goto bail_out;
  293                 }
status |= IO_MAPPED;
gdt->sc_iot = iot;
gdt->sc_ioh = ioh;
gdt->sc_iobase = iobase;
  298         }
  300         switch (GDT_CLASS(gdt)) {
  301         case GDT_PCI:
bus_space_set_region_4(dpmemt, dpmemh, 0, 0,
GDT_DPR_IF_SZ >> 2);
  304                 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) {
printf("cannot write to DPMEM\n");
  306                         goto bail_out;
  307                 }
  309 #if 0
  310                 /* disable board interrupts, deinit services */
gdth_writeb(0xff, &dp6_ptr->io.irqdel);
gdth_writeb(0x00, &dp6_ptr->io.irqen);
gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
gdth_writeb(0, &dp6_ptr->io.event);
retries = INIT_RETRIES;
gdth_delay(20);
  321                 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  322                   if (--retries == 0) {
printk("initialization error (DEINIT failed)\n");
gdth_munmap(ha->brd);
  325                     return 0;
  326                   }
gdth_delay(1);
  328                 }
prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  332                 if (prot_ver != PROTOCOL_VERSION) {
printk("illegal protocol version\n");
gdth_munmap(ha->brd);
  335                   return 0;
  336                 }
ha->type = GDT_PCI;
ha->ic_all_size = sizeof(dp6_ptr->u);
  341                 /* special command to controller BIOS */
gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
gdth_writel(0x01, &dp6_ptr->u.ic.S_Info[2]);
gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
gdth_writeb(0, &dp6_ptr->io.event);
retries = INIT_RETRIES;
gdth_delay(20);
  350                 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  351                   if (--retries == 0) {
printk("initialization error\n");
gdth_munmap(ha->brd);
  354                     return 0;
  355                   }
gdth_delay(1);
  357                 }
gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  360 #endif
gdt->sc_ic_all_size = GDT_DPRAM_SZ;
gdt->sc_copy_cmd = gdt_pci_copy_cmd;
gdt->sc_get_status = gdt_pci_get_status;
gdt->sc_intr = gdt_pci_intr;
gdt->sc_release_event = gdt_pci_release_event;
gdt->sc_set_sema0 = gdt_pci_set_sema0;
gdt->sc_test_busy = gdt_pci_test_busy;
  371                 break;
  373         case GDT_PCINEW:
bus_space_set_region_4(dpmemt, dpmemh, 0, 0,
GDT_DPR_IF_SZ >> 2);
  376                 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) {
printf("cannot write to DPMEM\n");
  378                         goto bail_out;
  379                 }
  381 #if 0
  382                 /* disable board interrupts, deinit services */
outb(0x00,PTR2USHORT(&ha->plx->control1));
outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
retries = INIT_RETRIES;
gdth_delay(20);
  396                 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  397                   if (--retries == 0) {
printk("initialization error (DEINIT failed)\n");
gdth_munmap(ha->brd);
  400                     return 0;
  401                   }
gdth_delay(1);
  403                 }
prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
gdth_writeb(0, &dp6c_ptr->u.ic.Status);
  406                 if (prot_ver != PROTOCOL_VERSION) {
printk("illegal protocol version\n");
gdth_munmap(ha->brd);
  409                   return 0;
  410                 }
ha->type = GDT_PCINEW;
ha->ic_all_size = sizeof(dp6c_ptr->u);
  415                 /* special command to controller BIOS */
gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
gdth_writel(0x01, &dp6c_ptr->u.ic.S_Info[2]);
gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
retries = INIT_RETRIES;
gdth_delay(20);
  426                 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  427                   if (--retries == 0) {
printk("initialization error\n");
gdth_munmap(ha->brd);
  430                     return 0;
  431                   }
gdth_delay(1);
  433                 }
gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
  435 #endif
gdt->sc_ic_all_size = GDT_PCINEW_SZ;
gdt->sc_copy_cmd = gdt_pcinew_copy_cmd;
gdt->sc_get_status = gdt_pcinew_get_status;
gdt->sc_intr = gdt_pcinew_intr;
gdt->sc_release_event = gdt_pcinew_release_event;
gdt->sc_set_sema0 = gdt_pcinew_set_sema0;
gdt->sc_test_busy = gdt_pcinew_test_busy;
  446                 break;
  448         case GDT_MPR:
bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC, GDT_MPR_MAGIC);
  450                 if (bus_space_read_4(dpmemt, dpmemh, GDT_MPR_IC) !=
GDT_MPR_MAGIC) {
printf("cannot access DPMEM at 0x%x (shadowed?)\n",
dpmembase);
  454                         goto bail_out;
  455                 }
  457                 /*
  458                  * XXX Here the Linux driver has a weird remapping logic I
  459                  * don't understand.  My controller does not need it, and I
  460                  * cannot see what purpose it serves, therefore I did not
  461                  * do anything similar.
  462                  */
bus_space_set_region_4(dpmemt, dpmemh, GDT_I960_SZ, 0,
GDT_DPR_IF_SZ >> 2);
  467                 /* Disable everything */
bus_space_write_1(dpmemt, dpmemh, GDT_EDOOR_EN,
bus_space_read_1(dpmemt, dpmemh, GDT_EDOOR_EN) | 4);
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_EDOOR, 0xff);
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS,
  472                     0);
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_CMD_INDEX,
  474                     0);
bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_INFO,
dpmembase);
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
  479                     0xff);
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_LDOOR, 1);
DELAY(20);
retries = GDT_RETRIES;
  484                 while (bus_space_read_1(dpmemt, dpmemh,
GDT_MPR_IC + GDT_S_STATUS) != 0xff) {
  486                         if (--retries == 0) {
printf("DEINIT failed (status 0x%x)\n",
bus_space_read_1(dpmemt, dpmemh,
GDT_MPR_IC + GDT_S_STATUS));
  490                                 goto bail_out;
  491                         }
DELAY(1);
  493                 }
protocol = (u_int8_t)bus_space_read_4(dpmemt, dpmemh,
GDT_MPR_IC + GDT_S_INFO);
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS,
  498                     0);
  499                 if (protocol != GDT_PROTOCOL_VERSION) {
printf("unsupported protocol %d\n", protocol);
  501                         goto bail_out;
  502                 }
  504                 /* special commnd to controller BIOS */
bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_INFO, 0);
bus_space_write_4(dpmemt, dpmemh,
GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), 0);
bus_space_write_4(dpmemt, dpmemh,
GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t), 1);
bus_space_write_4(dpmemt, dpmemh,
GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t), 0);
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
  513                     0xfe);
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_LDOOR, 1);
DELAY(20);
retries = GDT_RETRIES;
  518                 while (bus_space_read_1(dpmemt, dpmemh,
GDT_MPR_IC + GDT_S_STATUS) != 0xfe) {
  520                         if (--retries == 0) {
printf("initialization error\n");
  522                                 goto bail_out;
  523                         }
DELAY(1);
  525                 }
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS,
  528                     0);
gdt->sc_ic_all_size = GDT_MPR_SZ;
gdt->sc_copy_cmd = gdt_mpr_copy_cmd;
gdt->sc_get_status = gdt_mpr_get_status;
gdt->sc_intr = gdt_mpr_intr;
gdt->sc_release_event = gdt_mpr_release_event;
gdt->sc_set_sema0 = gdt_mpr_set_sema0;
gdt->sc_test_busy = gdt_mpr_test_busy;
  538         }
  540         if (pci_intr_map(pa, &ih)) {
printf("couldn't map interrupt\n");
  542                 goto bail_out;
  543         }
intrstr = pci_intr_string(pa->pa_pc, ih);
gdt->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, gdt_intr, gdt,
gdt->sc_dev.dv_xname);
  547         if (gdt->sc_ih == NULL) {
printf("couldn't establish interrupt");
  549                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
  552                 goto bail_out;
  553         }
status |= INTR_ESTABLISHED;
  555         if (intrstr != NULL)
printf("%s ", intrstr);
  558         if (gdt_attach(gdt))
  559                 goto bail_out;
gdt_pci_enable_intr(gdt);
  563         return;
bail_out:
  566         if (status & DPMEM_MAPPED)
bus_space_unmap(dpmemt, dpmemh, dpmemsize);
  568         if (status & IOMEM_MAPPED)
bus_space_unmap(iomemt, iomemh, iomembase);
  570         if (status & IO_MAPPED)
bus_space_unmap(iot, ioh, iosize);
  572         if (status & INTR_ESTABLISHED)
pci_intr_disestablish(pa->pa_pc, gdt->sc_ih);
  574         return;
  575 }
  577 /* Enable interrupts */
  578 void
gdt_pci_enable_intr(gdt)
  580         struct gdt_softc *gdt;
  581 {
GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt));
  584         switch(GDT_CLASS(gdt)) {
  585         case GDT_PCI:
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_IRQDEL,
  587                     1);
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_CMD_INDEX, 0);
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_IRQEN,
  591                     1);
  592                 break;
  594         case GDT_PCINEW:
bus_space_write_1(gdt->sc_iot, gdt->sc_ioh, GDT_EDOOR_REG,
  596                     0xff);
bus_space_write_1(gdt->sc_iot, gdt->sc_ioh, GDT_CONTROL1, 3);
  598                 break;
  600         case GDT_MPR:
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_MPR_EDOOR, 0xff);
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_EDOOR_EN) & ~4);
  606                 break;
  607         }
  608 }
  610 /*
  611  * "old" PCI controller-specific functions
  612  */
  614 void
gdt_pci_copy_cmd(gdt, ccb)
  616         struct gdt_softc *gdt;
  617         struct gdt_ccb *ccb;
  618 {
  619         /* XXX Not yet implemented */
  620 }
u_int8_t
gdt_pci_get_status(gdt)
  624         struct gdt_softc *gdt;
  625 {
  626         /* XXX Not yet implemented */
  627         return (0);
  628 }
  630 void
gdt_pci_intr(gdt, ctx)
  632         struct gdt_softc *gdt;
  633         struct gdt_intr_ctx *ctx;
  634 {
  635         /* XXX Not yet implemented */
  636 }
  638 void
gdt_pci_release_event(gdt, ccb)
  640         struct gdt_softc *gdt;
  641         struct gdt_ccb *ccb;
  642 {
  643         /* XXX Not yet implemented */
  644 }
  646 void
gdt_pci_set_sema0(gdt)
  648         struct gdt_softc *gdt;
  649 {
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_SEMA0, 1);
  651 }
  653 int
gdt_pci_test_busy(gdt)
  655         struct gdt_softc *gdt;
  656 {
  657         /* XXX Not yet implemented */
  658         return (0);
  659 }
  661 /*
  662  * "new" PCI controller-specific functions
  663  */
  665 void
gdt_pcinew_copy_cmd(gdt, ccb)
  667         struct gdt_softc *gdt;
  668         struct gdt_ccb *ccb;
  669 {
  670         /* XXX Not yet implemented */
  671 }
u_int8_t
gdt_pcinew_get_status(gdt)
  675         struct gdt_softc *gdt;
  676 {
  677         /* XXX Not yet implemented */
  678         return (0);
  679 }
  681 void
gdt_pcinew_intr(gdt, ctx)
  683         struct gdt_softc *gdt;
  684         struct gdt_intr_ctx *ctx;
  685 {
  686         /* XXX Not yet implemented */
  687 }
  689 void
gdt_pcinew_release_event(gdt, ccb)
  691         struct gdt_softc *gdt;
  692         struct gdt_ccb *ccb;
  693 {
  694         /* XXX Not yet implemented */
  695 }
  697 void
gdt_pcinew_set_sema0(gdt)
  699         struct gdt_softc *gdt;
  700 {
bus_space_write_1(gdt->sc_iot, gdt->sc_ioh, GDT_SEMA0_REG, 1);
  702 }
  704 int
gdt_pcinew_test_busy(gdt)
  706         struct gdt_softc *gdt;
  707 {
  708         /* XXX Not yet implemented */
  709         return (0);
  710 }
  712 /*
  713  * MPR PCI controller-specific functions
  714  */
  716 void
gdt_mpr_copy_cmd(gdt, ccb)
  718         struct gdt_softc *gdt;
  719         struct gdt_ccb *ccb;
  720 {
u_int16_t cp_count = roundup(gdt->sc_cmd_len, sizeof (u_int32_t));
u_int16_t dp_offset = gdt->sc_cmd_off;
u_int16_t cmd_no = gdt->sc_cmd_cnt++;
GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt));
gdt->sc_cmd_off += cp_count;
bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET,
GDT_DPMEM_COMMAND_OFFSET + dp_offset);
bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID,
ccb->gc_service);
bus_space_write_raw_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_MPR_IC + GDT_DPR_CMD + dp_offset, gdt->sc_cmd, cp_count);
  737 }
u_int8_t
gdt_mpr_get_status(gdt)
  741         struct gdt_softc *gdt;
  742 {
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt));
  745         return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR);
  746 }
  748 void
gdt_mpr_intr(gdt, ctx)
  750         struct gdt_softc *gdt;
  751         struct gdt_intr_ctx *ctx;
  752 {
GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt));
  755         if (ctx->istatus & 0x80) {              /* error flag */
ctx->istatus &= ~0x80;
ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt,
gdt->sc_dpmemh, GDT_MPR_STATUS);
  759                 if (ctx->istatus == GDT_ASYNCINDEX) {
ctx->service = bus_space_read_2(gdt->sc_dpmemt,
gdt->sc_dpmemh, GDT_MPR_SERVICE);
ctx->info2 = bus_space_read_4(gdt->sc_dpmemt,
gdt->sc_dpmemh, GDT_MPR_INFO + sizeof (u_int32_t));
  764                 }
  765         } else                                  /* no error */
ctx->cmd_status = GDT_S_OK;
ctx->info =
bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO);
  771         if (gdt_polling)                        /* init. -> more info */
ctx->info2 = bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_MPR_INFO + sizeof (u_int32_t));
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0);
  776 }
  778 void
gdt_mpr_release_event(gdt, ccb)
  780         struct gdt_softc *gdt;
  781         struct gdt_ccb *ccb;
  782 {
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt));
  785         if (gdt_dec16(gdt->sc_cmd + GDT_CMD_OPCODE) == GDT_INIT)
ccb->gc_service |= 0x80;
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
  788 }
  790 void
gdt_mpr_set_sema0(gdt)
  792         struct gdt_softc *gdt;
  793 {
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt));
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1);
  797 }
  799 int
gdt_mpr_test_busy(gdt)
  801         struct gdt_softc *gdt;
  802 {
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt));
  805         return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_MPR_SEMA0) & 1);
  807 }