sc_iobase 378 arch/i386/isa/pccom.c sc->sc_iobase = iobase;
sc_iobase 58 arch/i386/isa/pccomvar.h int sc_iobase;
sc_iobase 277 dev/cardbus/com_cardbus.c sc->sc_iobase = csc->cc_addr;
sc_iobase 119 dev/eisa/if_fea.c PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_FUNCTION_CTRL, 0x23);
sc_iobase 120 dev/eisa/if_fea.c PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_IO_CMP_1_1,
sc_iobase 121 dev/eisa/if_fea.c (sc->sc_iobase >> 8) & 0xF0);
sc_iobase 122 dev/eisa/if_fea.c PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_IO_CMP_0_1,
sc_iobase 123 dev/eisa/if_fea.c (sc->sc_iobase >> 8) & 0xF0);
sc_iobase 124 dev/eisa/if_fea.c PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_SLOT_CTRL, 0x01);
sc_iobase 125 dev/eisa/if_fea.c data = PDQ_OS_IORD_8(tag, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF);
sc_iobase 127 dev/eisa/if_fea.c PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF, data & ~1);
sc_iobase 129 dev/eisa/if_fea.c PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF, data | 1);
sc_iobase 131 dev/eisa/if_fea.c data = PDQ_OS_IORD_8(tag, sc->sc_iobase, PDQ_EISA_IO_CONFIG_STAT_0);
sc_iobase 132 dev/eisa/if_fea.c PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_IO_CONFIG_STAT_0,
sc_iobase 173 dev/eisa/if_fea.c EISA_SLOT_SIZE, 0, &sc->sc_iobase)) {
sc_iobase 178 dev/eisa/if_fea.c pdq_eisa_subprobe(sc->sc_iotag, sc->sc_iobase, &maddr, &msize, &irq);
sc_iobase 182 dev/eisa/if_fea.c sc->sc_csrhandle = sc->sc_iobase;
sc_iobase 191 dev/eisa/if_fea.c bus_space_unmap(sc->sc_iotag, sc->sc_iobase, EISA_SLOT_SIZE);
sc_iobase 153 dev/ic/com_subr.c if (sc->sc_iobase == comconsaddr) {
sc_iobase 283 dev/ic/com_subr.c if (sc->sc_iobase == comsiraddr) {
sc_iobase 350 dev/ic/com_subr.c if (iot == com_kgdb_iot && sc->sc_iobase == com_kgdb_addr &&
sc_iobase 91 dev/ic/comvar.h bus_addr_t sc_iobase;
sc_iobase 296 dev/ic/gdtvar.h bus_addr_t sc_iobase;
sc_iobase 191 dev/ic/i82596var.h void *sc_iobase; /* (MD) KVA of base of 24 bit addr space */
sc_iobase 203 dev/ic/pdqvar.h bus_space_handle_t sc_iobase; /* i/o space handle */
sc_iobase 211 dev/ic/pdqvar.h pdq_bus_ioport_t sc_iobase;
sc_iobase 213 dev/ic/pdqvar.h #define sc_membase sc_iobase
sc_iobase 102 dev/isa/ad1848var.h int sc_iobase;
sc_iobase 89 dev/isa/addcom_isa.c bus_addr_t sc_iobase;
sc_iobase 203 dev/isa/addcom_isa.c sc->sc_iobase = ia->ia_iobase;
sc_iobase 225 dev/isa/addcom_isa.c iobase = sc->sc_iobase
sc_iobase 243 dev/isa/addcom_isa.c ca.ca_iobase = sc->sc_iobase
sc_iobase 123 dev/isa/aha.c int sc_iobase;
sc_iobase 390 dev/isa/aha.c sc->sc_iobase = ia->ia_iobase;
sc_iobase 520 dev/isa/aha.c int iobase = sc->sc_iobase;
sc_iobase 780 dev/isa/aha.c int iobase = sc->sc_iobase;
sc_iobase 1015 dev/isa/aha.c sc->sc_iobase = iobase;
sc_iobase 1041 dev/isa/aha.c int iobase = sc->sc_iobase;
sc_iobase 1163 dev/isa/aha.c int iobase = sc->sc_iobase;
sc_iobase 1415 dev/isa/aha.c int iobase = sc->sc_iobase;
sc_iobase 111 dev/isa/aria.c u_short sc_iobase; /* I/O port base address */
sc_iobase 291 dev/isa/aria.c sc->sc_iobase = iobase;
sc_iobase 487 dev/isa/aria.c register u_short iobase = sc->sc_iobase;
sc_iobase 531 dev/isa/aria.c sc->sc_irq, sc->sc_iobase, sc->sc_interrupts);
sc_iobase 770 dev/isa/aria.c register u_short iobase = sc->sc_iobase;
sc_iobase 877 dev/isa/aria.c register u_int iobase = sc->sc_iobase;
sc_iobase 913 dev/isa/aria.c register u_short iobase = sc->sc_iobase;
sc_iobase 1030 dev/isa/aria.c aria_sendcmd(sc->sc_iobase, ARIADSPC_STOP_REC, 0, -1, -1);
sc_iobase 1046 dev/isa/aria.c aria_sendcmd(sc->sc_iobase, ARIADSPC_STOP_PLAY, 1, -1, -1);
sc_iobase 1065 dev/isa/aria.c aria_sendcmd(sc->sc_iobase, ARIADSPC_START_REC, ARIAR_RECORD_CHAN, -1, -1);
sc_iobase 1070 dev/isa/aria.c aria_sendcmd(sc->sc_iobase, ARIADSPC_START_PLAY, 1, -1, -1);
sc_iobase 1106 dev/isa/aria.c aria_sendcmd(sc->sc_iobase, ARIADSPC_START_REC, 0, -1, -1);
sc_iobase 1137 dev/isa/aria.c aria_sendcmd(sc->sc_iobase, ARIADSPC_START_PLAY, 1, -1, -1);
sc_iobase 1154 dev/isa/aria.c register u_short iobase = sc->sc_iobase;
sc_iobase 56 dev/isa/ast.c int sc_iobase;
sc_iobase 152 dev/isa/ast.c sc->sc_iobase = ia->ia_iobase;
sc_iobase 155 dev/isa/ast.c if (bus_space_map(sc->sc_iot, sc->sc_iobase + i * COM_NPORTS,
sc_iobase 170 dev/isa/ast.c ca.ca_iobase = sc->sc_iobase + i * COM_NPORTS;
sc_iobase 56 dev/isa/boca.c int sc_iobase;
sc_iobase 153 dev/isa/boca.c sc->sc_iobase = ia->ia_iobase;
sc_iobase 156 dev/isa/boca.c if (bus_space_map(iot, sc->sc_iobase + i * COM_NPORTS,
sc_iobase 167 dev/isa/boca.c ca.ca_iobase = sc->sc_iobase + i * COM_NPORTS;
sc_iobase 119 dev/isa/com_commulti.c sc->sc_iobase = ca->ca_iobase;
sc_iobase 153 dev/isa/com_isa.c sc->sc_iobase = iobase;
sc_iobase 135 dev/isa/com_isapnp.c sc->sc_iobase = iobase;
sc_iobase 282 dev/isa/ess.c (int)sc->sc_open, sc->sc_iobase, sc->out_port,
sc_iobase 356 dev/isa/ess.c int iobase = sc->sc_iobase;
sc_iobase 806 dev/isa/ess.c if (!ESS_BASE_VALID(sc->sc_iobase)) {
sc_iobase 807 dev/isa/ess.c printf("ess: configured iobase 0x%x invalid\n", sc->sc_iobase);
sc_iobase 85 dev/isa/ess_isapnp.c sc->sc_iobase = ia->ipa_io[0].base;
sc_iobase 130 dev/isa/essvar.h int sc_iobase; /* I/O port base address */
sc_iobase 2187 dev/isa/gus.c int port = sc->sc_iobase;
sc_iobase 2203 dev/isa/gus.c sc->sc_codec.sc_iobase = port+GUS_MAX_CODEC_BASE;
sc_iobase 2205 dev/isa/gus.c if (ad1848_mapprobe(&sc->sc_codec, sc->sc_codec.sc_iobase) == 0) {
sc_iobase 212 dev/isa/gus_isa.c sc->sc_iobase = ia->ia_iobase;
sc_iobase 215 dev/isa/gus_isa.c if (bus_space_map(sc->sc_iot, sc->sc_iobase, GUS_NPORT1, 0, &sc->sc_ioh1))
sc_iobase 217 dev/isa/gus_isa.c if (bus_space_map(sc->sc_iot, sc->sc_iobase+GUS_IOH2_OFFSET, GUS_NPORT2, 0,
sc_iobase 223 dev/isa/gus_isa.c if (bus_space_map(sc->sc_iot, sc->sc_iobase+GUS_IOH3_OFFSET, GUS_NPORT3, 0,
sc_iobase 227 dev/isa/gus_isa.c if (bus_space_map(sc->sc_iot, sc->sc_iobase+GUS_IOH4_OFFSET, GUS_NPORT4, 0,
sc_iobase 159 dev/isa/gus_isapnp.c sc->sc_iobase = ipa->ia_iobase;
sc_iobase 146 dev/isa/gusvar.h int sc_iobase; /* I/O base address */
sc_iobase 103 dev/isa/hsq.c int sc_iobase;
sc_iobase 200 dev/isa/hsq.c sc->sc_iobase = ia->ia_iobase;
sc_iobase 203 dev/isa/hsq.c if (bus_space_map(sc->sc_iot, sc->sc_iobase + i * COM_NPORTS,
sc_iobase 214 dev/isa/hsq.c ca.ca_iobase = sc->sc_iobase + i * COM_NPORTS;
sc_iobase 71 dev/isa/if_el.c int sc_iobase; /* base I/O addr */
sc_iobase 122 dev/isa/if_el.c sc->sc_iobase = iobase;
sc_iobase 229 dev/isa/if_el.c outb(sc->sc_iobase+EL_AC, 0);
sc_iobase 240 dev/isa/if_el.c int iobase = sc->sc_iobase;
sc_iobase 259 dev/isa/if_el.c int iobase = sc->sc_iobase;
sc_iobase 298 dev/isa/if_el.c int iobase = sc->sc_iobase;
sc_iobase 407 dev/isa/if_el.c int iobase = sc->sc_iobase;
sc_iobase 437 dev/isa/if_el.c int iobase = sc->sc_iobase;
sc_iobase 540 dev/isa/if_el.c int iobase = sc->sc_iobase;
sc_iobase 220 dev/isa/if_ie.c int sc_iobase;
sc_iobase 329 dev/isa/if_ie.c #define PORT sc->sc_iobase
sc_iobase 394 dev/isa/if_ie.c sc->sc_iobase = ia->ia_iobase;
sc_iobase 465 dev/isa/if_ie.c sc->sc_iobase = ia->ia_iobase;
sc_iobase 607 dev/isa/if_ie.c sc->sc_iobase = ia->ia_iobase;
sc_iobase 352 dev/isa/pas.c sc->sc_sbdsp.sc_iobase = ia->ia_iobase;
sc_iobase 412 dev/isa/pas.c sc->sc_sbdsp.sc_iobase = iobase;
sc_iobase 114 dev/isa/pss.c int sc_iobase; /* I/O port base address */
sc_iobase 135 dev/isa/pss.c int sc_iobase; /* MIDI I/O port base address */
sc_iobase 143 dev/isa/pss.c int sc_iobase; /* CD I/O port base address */
sc_iobase 301 dev/isa/pss.c int pss_base = sc->sc_iobase;
sc_iobase 444 dev/isa/pss.c int config = sc->sc_iobase + PSS_CONFIG;
sc_iobase 520 dev/isa/pss.c int config = sc->sc_iobase + PSS_CONFIG;
sc_iobase 585 dev/isa/pss.c int pss_base = sc->sc_iobase;
sc_iobase 615 dev/isa/pss.c int pss_base = sc->sc_iobase;
sc_iobase 689 dev/isa/pss.c (u_char)inb(sc->sc_iobase-WSS_CODEC+WSS_STATUS));
sc_iobase 698 dev/isa/pss.c (u_short)inw(sc->sc_iobase+PSS_STATUS),
sc_iobase 699 dev/isa/pss.c (u_short)inw(sc->sc_iobase+PSS_ID_VERS));
sc_iobase 702 dev/isa/pss.c (u_short)inw(sc->sc_iobase+PSS_CONFIG),
sc_iobase 703 dev/isa/pss.c (u_short)inw(sc->sc_iobase+PSS_WSS_CONFIG));
sc_iobase 745 dev/isa/pss.c sc->sc_iobase = iobase;
sc_iobase 748 dev/isa/pss.c pss_setaddr(WSS_BASE_ADDRESS, sc->sc_iobase+PSS_WSS_CONFIG); /* XXX! */
sc_iobase 752 dev/isa/pss.c outw(sc->sc_iobase+PSS_CONFIG, 0);
sc_iobase 753 dev/isa/pss.c outw(sc->sc_iobase+PSS_WSS_CONFIG, 0);
sc_iobase 754 dev/isa/pss.c outw(sc->sc_iobase+SB_CONFIG, 0);
sc_iobase 755 dev/isa/pss.c outw(sc->sc_iobase+MIDI_CONFIG, 0);
sc_iobase 756 dev/isa/pss.c outw(sc->sc_iobase+CD_CONFIG, 0);
sc_iobase 789 dev/isa/pss.c pss_setint(ia->ia_irq, sc->sc_iobase+PSS_CONFIG);
sc_iobase 790 dev/isa/pss.c pss_setdma(sc->sc_drq, sc->sc_iobase+PSS_CONFIG);
sc_iobase 796 dev/isa/pss.c outw(sc->sc_iobase+PSS_STATUS, inw(sc->sc_iobase+PSS_STATUS) | GAME_BIT);
sc_iobase 798 dev/isa/pss.c outw(sc->sc_iobase+PSS_STATUS, inw(sc->sc_iobase+PSS_STATUS) & GAME_BIT_MASK);
sc_iobase 824 dev/isa/pss.c sc->sc_iobase = cf->cf_iobase + WSS_CODEC;
sc_iobase 827 dev/isa/pss.c pss_setaddr(cf->cf_iobase, pc->sc_iobase+PSS_WSS_CONFIG);
sc_iobase 831 dev/isa/pss.c DPRINTF(("sp: no ad1848 ? iobase=%x\n", sc->sc_iobase));
sc_iobase 895 dev/isa/pss.c outb(sc->sc_iobase+WSS_CONFIG, (bits | 0x40));
sc_iobase 896 dev/isa/pss.c if ((inb(sc->sc_iobase+WSS_STATUS) & 0x40) == 0) /* XXX What do these bits mean ? */
sc_iobase 897 dev/isa/pss.c DPRINTF(("sp: IRQ %x\n", inb(sc->sc_iobase+WSS_STATUS)));
sc_iobase 899 dev/isa/pss.c outb(sc->sc_iobase+WSS_CONFIG, (bits | wss_dma_bits[sc->sc_drq]));
sc_iobase 918 dev/isa/pss.c sc->sc_iobase = cf->cf_iobase;
sc_iobase 945 dev/isa/pss.c outw(pc->sc_iobase+MIDI_CONFIG,0);
sc_iobase 946 dev/isa/pss.c DPRINTF(("pss: mpu port 0x%x irq %d\n", sc->sc_iobase, sc->sc_irq));
sc_iobase 947 dev/isa/pss.c pss_setaddr(sc->sc_iobase, pc->sc_iobase+MIDI_CONFIG);
sc_iobase 948 dev/isa/pss.c pss_setint(sc->sc_irq, pc->sc_iobase+MIDI_CONFIG);
sc_iobase 963 dev/isa/pss.c sc->sc_iobase = cf->cf_iobase;
sc_iobase 965 dev/isa/pss.c pss_setaddr(sc->sc_iobase, pc->sc_iobase+CD_CONFIG);
sc_iobase 968 dev/isa/pss.c val = inw(pc->sc_iobase+CD_CONFIG);
sc_iobase 969 dev/isa/pss.c outw(pc->sc_iobase+CD_CONFIG, 0);
sc_iobase 972 dev/isa/pss.c outw(pc->sc_iobase+CD_CONFIG, val);
sc_iobase 999 dev/isa/pss.c pss_setint(sc->sc_irq, pc->sc_iobase+CD_CONFIG);
sc_iobase 1020 dev/isa/pss.c sc->sc_iobase = iobase;
sc_iobase 1027 dev/isa/pss.c vers = (inw(sc->sc_iobase+PSS_ID_VERS)&0xff) - 1;
sc_iobase 1052 dev/isa/pss.c sc->sc_iobase = iobase;
sc_iobase 1076 dev/isa/pss.c sc->sc_iobase = iobase;
sc_iobase 1083 dev/isa/pss.c sc->sc_iobase, MIDI_NPORT, cf->cf_irq);
sc_iobase 1100 dev/isa/pss.c sc->sc_iobase = iobase;
sc_iobase 1104 dev/isa/pss.c sc->sc_iobase, 2, cf->cf_irq);
sc_iobase 1259 dev/isa/pss.c sr = inw(sc->sc_iobase+PSS_STATUS);
sc_iobase 1264 dev/isa/pss.c outw(sc->sc_iobase+PSS_IRQ_ACK, 0);
sc_iobase 1283 dev/isa/pss.c sr = inb(sc->sc_iobase+MIDI_STATUS_REG);
sc_iobase 56 dev/isa/rtfps.c int sc_iobase;
sc_iobase 161 dev/isa/rtfps.c sc->sc_iobase = ia->ia_iobase;
sc_iobase 168 dev/isa/rtfps.c if (bus_space_map(iot, sc->sc_iobase + i * COM_NPORTS,
sc_iobase 183 dev/isa/rtfps.c ca.ca_iobase = sc->sc_iobase + i * COM_NPORTS;
sc_iobase 109 dev/isa/sb_isa.c sc->sc_iobase = ia->ia_iobase;
sc_iobase 100 dev/isa/sb_isapnp.c sc->sc_iobase = ia->ipa_io[0].base;
sc_iobase 205 dev/isa/sbdsp.c sc->sc_iobase, sc->sc_irq);
sc_iobase 288 dev/isa/sbdsp.c bus_space_write_1(iot, ioh, 0, sc->sc_iobase & 0x70);
sc_iobase 107 dev/isa/sbdspvar.h int sc_iobase; /* I/O port base address */
sc_iobase 297 dev/pci/gdt_pci.c gdt->sc_iobase = iobase;
sc_iobase 323 dev/pcmcia/com_pcmcia.c sc->sc_iobase = -1;
sc_iobase 119 dev/puc/com_puc.c sc->sc_iobase = pa->a;
sc_iobase 211 dev/sbus/asio.c sc->sc_iobase = 0; /* XXX WTF is iobase for? It used to be the lower 32 bits of ioh's vaddr... */