1 /* $OpenBSD: stp4020reg.h,v 1.6 2007/08/06 15:13:47 tom Exp $ */
2 /* $NetBSD: stp4020reg.h,v 1.1 1998/11/22 22:14:35 pk Exp $ */
3
4 /*-
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Paul Kranenburg.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40
41 #ifndef _STP4020_REG_H
42 #define _STP4020_REG_H
43
44 /*
45 * STP4020: SBus/PCMCIA bridge supporting one Type-3 PCMCIA card, or up to
46 * two Type-1 and Type-2 PCMCIA cards..
47 * Programming information source:
48 * - http://www.sun.com/microelectronics/datasheets/stp4020/
49 * - SunOS 5.5 header file
50 */
51
52 /*
53 * General chip attributes.
54 */
55 #define STP4020_NSOCK 2 /* number of PCCARD sockets per STP4020 */
56 #define STP4020_NWIN 3 /* number of windows per socket */
57
58 /*
59 * Socket control registers.
60 *
61 * Each PCMCIA socket has two interface control registers and two interface
62 * status registers associated with it.
63 */
64
65 /*
66 * Socket Interface Control register 0
67 */
68 #define STP4020_ICR0_rsvd1 0xc000 /* reserved bits */
69 #define STP4020_ICR0_PROMEN 0x2000 /* FCode PROM enable */
70 /* Status change interrupts can be routed to one of two SBus interrupt levels:*/
71 #define STP4020_ICR0_SCILVL 0x1000 /* card status change interrupt level */
72 #define STP4020_ICR0_SCILVL_SB0 0x0000 /* interrupt on *SB_INT[0] */
73 #define STP4020_ICR0_SCILVL_SB1 0x1000 /* interrupt on *SB_INT[1] */
74 /* Interrupt enable bits: */
75 #define STP4020_ICR0_CDIE 0x0800 /* card detect interrupt enable */
76 #define STP4020_ICR0_BVD2IE 0x0400 /* battery voltage detect 2 int en. */
77 #define STP4020_ICR0_BVD1IE 0x0200 /* battery voltage detect 1 int en. */
78 #define STP4020_ICR0_RDYIE 0x0100 /* ready/busy interrupt enable */
79 #define STP4020_ICR0_WPIE 0x0080 /* write protect interrupt enable */
80 #define STP4020_ICR0_CTOIE 0x0040 /* PC card timeout interrupt enable */
81 #define STP4020_ICR0_rsvd2 0x0020 /* */
82 #define STP4020_ICR0_IOIE 0x0010 /* I/O (*IRQ) interrupt enable */
83 /* PC card I/O interrupts can also be routed to one of two SBus intr levels: */
84 #define STP4020_ICR0_IOILVL 0x0008 /* I/O (*IRQ) interrupt level (SBus) */
85 #define STP4020_ICR0_IOILVL_SB0 0x0000 /* interrupt on *SB_INT[0] */
86 #define STP4020_ICR0_IOILVL_SB1 0x0008 /* interrupt on *SB_INT[1] */
87
88 #define STP4020_ICR0_SPKREN 0x0004 /* *SPKR_OUT enable */
89 #define STP4020_ICR0_RESET 0x0002 /* PC card reset */
90 #define STP4020_ICR0_IFTYPE 0x0001 /* PC card interface type */
91 #define STP4020_ICR0_IFTYPE_MEM 0x0000 /* MEMORY only */
92 #define STP4020_ICR0_IFTYPE_IO 0x0001 /* MEMORY and I/O */
93 #define STP4020_ICR0_BITS "\010\1IFTYPE\2RESET\3SPKREN\4IOILVL\5IOIE" \
94 "\7CTOIE\10WPIE\11RDYIE\12BVD1IE\13BVD2IE\14CDIE\15SCILV\16PROMEN"
95
96 /* Shorthand for all status change interrupts enables */
97 #define STP4020_ICR0_ALL_STATUS_IE ( \
98 STP4020_ICR0_CDIE | \
99 STP4020_ICR0_BVD2IE | \
100 STP4020_ICR0_BVD1IE | \
101 STP4020_ICR0_RDYIE | \
102 STP4020_ICR0_WPIE | \
103 STP4020_ICR0_CTOIE \
104 )
105
106 /*
107 * Socket Interface Control register 1
108 */
109 #define STP4020_ICR1_LPBKEN 0x8000 /* PC card data loopback enable */
110 #define STP4020_ICR1_CD1DB 0x4000 /* card detect 1 diagnostic bit */
111 #define STP4020_ICR1_BVD2DB 0x2000 /* battery voltage detect 2 diag bit */
112 #define STP4020_ICR1_BVD1DB 0x1000 /* battery voltage detect 1 diag bit */
113 #define STP4020_ICR1_RDYDB 0x0800 /* ready/busy diagnostic bit */
114 #define STP4020_ICR1_WPDB 0x0400 /* write protect diagnostic bit */
115 #define STP4020_ICR1_WAITDB 0x0200 /* *WAIT diagnostic bit */
116 #define STP4020_ICR1_DIAGEN 0x0100 /* diagnostic enable bit */
117 #define STP4020_ICR1_rsvd1 0x0080 /* reserved */
118 #define STP4020_ICR1_APWREN 0x0040 /* PC card auto power switch enable */
119
120 /*
121 * The Vpp controls are two-bit fields which specify which voltage
122 * should be switched onto Vpp for this socket.
123 *
124 * Both of the "no connect" states are equal.
125 */
126 #define STP4020_ICR1_VPP2EN 0x0030 /* Vpp2 power enable */
127 #define STP4020_ICR1_VPP2_OFF 0x0000 /* no connect */
128 #define STP4020_ICR1_VPP2_VCC 0x0010 /* Vcc switched onto Vpp2 */
129 #define STP4020_ICR1_VPP2_VPP 0x0020 /* Vpp switched onto Vpp2 */
130 #define STP4020_ICR1_VPP2_ZIP 0x0030 /* no connect */
131
132 #define STP4020_ICR1_VPP1EN 0x000c /* Vpp1 power enable */
133 #define STP4020_ICR1_VPP1_OFF 0x0000 /* no connect */
134 #define STP4020_ICR1_VPP1_VCC 0x0004 /* Vcc switched onto Vpp1 */
135 #define STP4020_ICR1_VPP1_VPP 0x0008 /* Vpp switched onto Vpp1 */
136 #define STP4020_ICR1_VPP1_ZIP 0x000c /* no connect */
137
138 #define STP4020_ICR1_MSTPWR 0x0002 /* PC card master power enable */
139 #define STP4020_ICR1_PCIFOE 0x0001 /* PC card interface output enable */
140
141 #define STP4020_ICR1_BITS "\010\1PCIFOE\2MSTPWR\7APWREN\11DIAGEN" \
142 "\12WAITDB\13WPDB\14RDYDB\15BVD1D\16BVD2D\17CD1DB\18LPBKEN"
143
144 /*
145 * Socket Interface Status register 0
146 *
147 * Some signals in this register change meaning depending on whether
148 * the socket is configured as MEMORY-ONLY or MEMORY & I/O:
149 * mo: valid only if the socket is in memory-only mode
150 * io: valid only if the socket is in memory and I/O mode.
151 *
152 * Pending interrupts are cleared by writing the corresponding status
153 * bit set in the upper half of this register.
154 */
155 #define STP4020_ISR0_ZERO 0x8000 /* always reads back as zero (mo) */
156 #define STP4020_ISR0_IOINT 0x8000 /* PC card I/O intr (*IRQ) posted (io)*/
157 #define STP4020_ISR0_SCINT 0x4000 /* status change interrupt posted */
158 #define STP4020_ISR0_CDCHG 0x2000 /* card detect status change */
159 #define STP4020_ISR0_BVD2CHG 0x1000 /* battery voltage detect 2 status change */
160 #define STP4020_ISR0_BVD1CHG 0x0800 /* battery voltage detect 1 status change */
161 #define STP4020_ISR0_RDYCHG 0x0400 /* ready/busy status change */
162 #define STP4020_ISR0_WPCHG 0x0200 /* write protect status change */
163 #define STP4020_ISR0_PCTO 0x0100 /* PC card access timeout */
164 #define STP4020_ISR0_ALL_STATUS_IRQ 0x7f00
165
166 #define STP4020_ISR0_LIVE 0x00ff /* live status bit mask */
167 #define STP4020_ISR0_CD2ST 0x0080 /* card detect 2 live status */
168 #define STP4020_ISR0_CD1ST 0x0040 /* card detect 1 live status */
169 #define STP4020_ISR0_BVD2ST 0x0020 /* battery voltage detect 2 live status (mo) */
170 #define STP4020_ISR0_SPKR 0x0020 /* SPKR signal live status (io)*/
171 #define STP4020_ISR0_BVD1ST 0x0010 /* battery voltage detect 1 live status (mo) */
172 #define STP4020_ISR0_STSCHG 0x0010 /* I/O *STSCHG signal live status (io)*/
173 #define STP4020_ISR0_RDYST 0x0008 /* ready/busy live status (mo) */
174 #define STP4020_ISR0_IOREQ 0x0008 /* I/O *REQ signal live status (io) */
175 #define STP4020_ISR0_WPST 0x0004 /* write protect live status (mo) */
176 #define STP4020_ISR0_IOIS16 0x0004 /* IOIS16 signal live status (io) */
177 #define STP4020_ISR0_WAITST 0x0002 /* wait signal live status */
178 #define STP4020_ISR0_PWRON 0x0001 /* PC card power status */
179
180 #define STP4020_ISR0_IOBITS "\010\1PWRON\2WAITST\3IOIS16\4IOREQ" \
181 "\5STSCHG\6SPKR\7CD1ST\10CD2ST\11PCTO\12WPCHG\13RDYCHG\14BVD1CHG" \
182 "\15BVD2CHG\16CDCHG\17SCINT\20IOINT"
183 #define STP4020_ISR0_MOBITS "\010\1PWRON\2WAITST\3WPST\4RDYST" \
184 "\5BVD1ST\6BVD2ST\7CD1ST\10CD2ST\11PCTO\12WPCHG\13RDYCHG\14BVD1CHG" \
185 "\15BVD2CHG\16CDCHG\17SCINT"
186
187 /*
188 * Socket Interface Status register 1
189 */
190 #define STP4020_ISR1_rsvd 0xffc0 /* reserved */
191 #define STP4020_ISR1_PCTYPE_M 0x0030 /* PC card type(s) supported bit mask */
192 #define STP4020_ISR1_PCTYPE_S 4 /* PC card type(s) supported bit shift */
193 #define STP4020_ISR1_REV_M 0x000f /* ASIC revision level bit mask */
194 #define STP4020_ISR1_REV_S 0 /* ASIC revision level bit shift */
195
196
197 /*
198 * Socket window control/status register definitions.
199 *
200 * According to SunOS 5.5:
201 * "Each PCMCIA socket has three windows associated with it; each of
202 * these windows can be programmed to map in either the AM, CM or IO
203 * space on the PC card. Each window can also be programmed with a
204 * starting or base address relative to the PC card's address zero.
205 * Each window is a fixed 1Mb in size.
206 *
207 * Each window has two window control registers associated with it to
208 * control the window's PCMCIA bus timing parameters, PC card address
209 * space that the window maps, and the base address in the
210 * selected PC card's address space."
211 */
212 #define STP4020_WINDOW_SIZE (1024*1024) /* 1MB */
213 #define STP4020_WINDOW_SHIFT 20 /* for 1MB */
214
215 /*
216 * PC card Window Control register 0
217 */
218 #define STP4020_WCR0_rsvd 0x8000 /* reserved */
219 #define STP4020_WCR0_CMDLNG_M 0x7c00 /* command strobe length bit mask */
220 #define STP4020_WCR0_CMDLNG_S 10 /* command strobe length bit shift */
221 #define STP4020_WCR0_CMDDLY_M 0x0300 /* command strobe delay bit mask */
222 #define STP4020_WCR0_CMDDLY_S 8 /* command strobe delay bit shift */
223 #define STP4020_MEM_SPEED_MIN 100
224 #define STP4020_MEM_SPEED_MAX 1370
225 /*
226 * The ASPSEL (Address Space Select) bits control which of the three PC card
227 * address spaces this window maps in.
228 */
229 #define STP4020_WCR0_ASPSEL_M 0x00c0 /* address space select bit mask */
230 #define STP4020_WCR0_ASPSEL_AM 0x0000 /* attribute memory */
231 #define STP4020_WCR0_ASPSEL_CM 0x0040 /* common memory */
232 #define STP4020_WCR0_ASPSEL_IO 0x0080 /* I/O */
233 /*
234 * The base address controls which 1MB range in the 64MB card address space
235 * this window maps to.
236 */
237 #define STP4020_WCR0_BASE_M 0x0003f /* base address bit mask */
238 #define STP4020_WCR0_BASE_S 0 /* base address bit shift */
239
240 #define STP4020_ADDR2PAGE(x) ((x) >> 20)
241
242 /*
243 * PC card Window Control register 1
244 */
245 #define STP4020_WCR1_rsvd 0xffe0 /* reserved */
246 #define STP4020_WCR1_RECDLY_M 0x0018 /* recovery delay bit mask */
247 #define STP4020_WCR1_RECDLY_S 3 /* recovery delay bit shift */
248 #define STP4020_WCR1_WAITDLY_M 0x0006 /* *WAIT signal delay bit mask */
249 #define STP4020_WCR1_WAITDLY_S 1 /* *WAIT signal delay bit shift */
250 #define STP4020_WCR1_WAITREQ_M 0x0001 /* *WAIT signal is required bit mask */
251 #define STP4020_WCR1_WAITREQ_S 0 /* *WAIT signal is required bit shift */
252
253 #if for_reference_only
254 /*
255 * STP4020 CSR structures
256 *
257 * There is one stp4020_regs_t structure per instance, and it refers to
258 * the complete Stp4020 register set.
259 *
260 * For each socket, there is one stp4020_socket_csr_t structure, which
261 * refers to all the registers for that socket. That structure is
262 * made up of the window register structures as well as the registers
263 * that control overall socket operation.
264 *
265 * For each window, there is one stp4020_window_ctl_t structure, which
266 * refers to all the registers for that window.
267 */
268
269 /*
270 * per-window CSR structure
271 */
272 typedef struct stp4020_window_ctl_t {
273 volatile ushort_t ctl0; /* window control register 0 */
274 volatile ushort_t ctl1; /* window control register 1 */
275 } stp4020_window_ctl_t;
276
277 /*
278 * per-socket CSR structure
279 */
280 typedef struct stp4020_socket_csr_t {
281 volatile struct stp4020_window_ctl_t window[STP4020_NWIN];
282 volatile ushort_t ctl0; /* socket control register 0 */
283 volatile ushort_t ctl1; /* socket control register 1 */
284 volatile ushort_t stat0; /* socket status register 0 */
285 volatile ushort_t stat1; /* socket status register 1 */
286 volatile uchar_t filler[12]; /* filler space */
287 } stp4020_socket_csr_t;
288
289 /*
290 * per-instance CSR structure
291 */
292 typedef struct stp4020_regs_t {
293 struct stp4020_socket_csr_t socket[STP4020_NSOCK]; /* socket CSRs */
294 } stp4020_regs_t;
295 #endif /* reference */
296
297 /* Size of control and status register banks */
298 #define STP4020_SOCKREGS_SIZE 32
299 #define STP4020_WINREGS_SIZE 4
300
301 /* Relative socket control & status register offsets */
302 #define STP4020_ICR0_IDX 12
303 #define STP4020_ICR1_IDX 14
304 #define STP4020_ISR0_IDX 16
305 #define STP4020_ISR1_IDX 18
306
307 /* Relative Window control register offsets */
308 #define STP4020_WCR0_IDX 0
309 #define STP4020_WCR1_IDX 2
310
311 /* Socket control and status register offsets */
312 #define STP4020_ICR0_REG(s) ((32 * (s)) + STP4020_ICR0_IDX)
313 #define STP4020_ICR1_REG(s) ((32 * (s)) + STP4020_ICR1_IDX)
314 #define STP4020_ISR0_REG(s) ((32 * (s)) + STP4020_ISR0_IDX)
315 #define STP4020_ISR1_REG(s) ((32 * (s)) + STP4020_ISR1_IDX)
316
317 /* Window control and status registers; one set per socket */
318 #define STP4020_WCR0_REG(s,w) ((32 * (s)) + (4 * (w)) + STP4020_WCR0_IDX)
319 #define STP4020_WCR1_REG(s,w) ((32 * (s)) + (4 * (w)) + STP4020_WCR1_IDX)
320
321 #endif /* _STP4020_REG_H */