ctl0             3118 dev/ic/rtw.c   	uint32_t proto_ctl0, ctl0, ctl1;
ctl0             3181 dev/ic/rtw.c   		ctl0 = proto_ctl0 |
ctl0             3187 dev/ic/rtw.c   			ctl0 |= RTW_TXCTL0_RATE_1MBPS;
ctl0             3190 dev/ic/rtw.c   			ctl0 |= RTW_TXCTL0_RATE_2MBPS;
ctl0             3193 dev/ic/rtw.c   			ctl0 |= RTW_TXCTL0_RATE_5MBPS;
ctl0             3196 dev/ic/rtw.c   			ctl0 |= RTW_TXCTL0_RATE_11MBPS;
ctl0             3202 dev/ic/rtw.c   			ctl0 |= RTW_TXCTL0_RTSEN;
ctl0             3206 dev/ic/rtw.c   			ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN);
ctl0             3209 dev/ic/rtw.c   				ctl0 |= RTW_TXCTL0_BEACON;
ctl0             3277 dev/ic/rtw.c   			td->td_ctl0 = htole32(ctl0);
ctl0              107 dev/pci/jmb.c  	u_int32_t			ctl0, ctl5;
ctl0              110 dev/pci/jmb.c  	ctl0 = pci_conf_read(pa->pa_pc, pa->pa_tag, JM_PCI_CTL0);
ctl0              114 dev/pci/jmb.c  	if (pa->pa_function == (ISSET(ctl0, JM_PCI_CTL0_AHCI_F1) ? 1 : 0)) {
ctl0              115 dev/pci/jmb.c  		ctl0 &= ~(JM_PCI_CTL0_AHCI_EN | JM_PCI_CTL0_SATA0_IDE |
ctl0              127 dev/pci/jmb.c  			ctl0 |= JM_PCI_CTL0_AHCI_EN | JM_PCI_CTL0_SATA0_AHCI |
ctl0              135 dev/pci/jmb.c  	if (pa->pa_function == (ISSET(ctl0, JM_PCI_CTL0_PCIIDE_F1) ? 1 : 0)) {
ctl0              136 dev/pci/jmb.c  		ctl0 &= ~(JM_PCI_CTL0_PCIIDE_CS | JM_PCI_CTL0_IDEDMA_CFG);
ctl0              148 dev/pci/jmb.c  			ctl0 |= JM_PCI_CTL0_PCIIDE_CS | JM_PCI_CTL0_IDEDMA_CFG;
ctl0              154 dev/pci/jmb.c  	pci_conf_write(pa->pa_pc, pa->pa_tag, JM_PCI_CTL0, ctl0);
ctl0              273 dev/sbus/stp4020reg.h     volatile	ushort_t	ctl0;		/* window control register 0 */
ctl0              282 dev/sbus/stp4020reg.h     volatile	ushort_t	ctl0;		/* socket control register 0 */