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54 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12)
55 #define AXE_CMD_DIR(x) (((x) & 0x0F00) >> 8)
56 #define AXE_CMD_CMD(x) ((x) & 0x00FF)
57
58 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002
59 #define AXE_182_CMD_READ_RXTX_SRAM 0x8002
60 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103
61 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104
62 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103
63 #define AXE_CMD_MII_OPMODE_SW 0x0106
64 #define AXE_CMD_MII_READ_REG 0x2007
65 #define AXE_CMD_MII_WRITE_REG 0x2108
66 #define AXE_CMD_MII_READ_OPMODE 0x1009
67 #define AXE_CMD_MII_OPMODE_HW 0x010A
68 #define AXE_CMD_SROM_READ 0x200B
69 #define AXE_CMD_SROM_WRITE 0x010C
70 #define AXE_CMD_SROM_WR_ENABLE 0x010D
71 #define AXE_CMD_SROM_WR_DISABLE 0x010E
72 #define AXE_CMD_RXCTL_READ 0x200F
73 #define AXE_CMD_RXCTL_WRITE 0x0110
74 #define AXE_CMD_READ_IPG012 0x3011
75 #define AXE_172_CMD_WRITE_IPG0 0x0112
76 #define AXE_172_CMD_WRITE_IPG1 0x0113
77 #define AXE_172_CMD_WRITE_IPG2 0x0114
78 #define AXE_178_CMD_WRITE_IPG012 0x0112
79 #define AXE_CMD_READ_MCAST 0x8015
80 #define AXE_CMD_WRITE_MCAST 0x8116
81 #define AXE_172_CMD_READ_NODEID 0x6017
82 #define AXE_172_CMD_WRITE_NODEID 0x6118
83 #define AXE_178_CMD_READ_NODEID 0x6013
84 #define AXE_178_CMD_WRITE_NODEID 0x6114
85 #define AXE_CMD_READ_PHYID 0x2019
86 #define AXE_172_CMD_READ_MEDIA 0x101A
87 #define AXE_178_CMD_READ_MEDIA 0x201A
88 #define AXE_CMD_WRITE_MEDIA 0x011B
89 #define AXE_CMD_READ_MONITOR_MODE 0x101C
90 #define AXE_CMD_WRITE_MONITOR_MODE 0x011D
91 #define AXE_CMD_READ_GPIO 0x101E
92 #define AXE_CMD_WRITE_GPIO 0x011F
93 #define AXE_CMD_SW_RESET_REG 0x0120
94 #define AXE_CMD_SW_PHY_STATUS 0x0021
95 #define AXE_CMD_SW_PHY_SELECT 0x0122
96
97 #define AXE_SW_RESET_CLEAR 0x00
98 #define AXE_SW_RESET_RR 0x01
99 #define AXE_SW_RESET_RT 0x02
100 #define AXE_SW_RESET_PRTE 0x04
101 #define AXE_SW_RESET_PRL 0x08
102 #define AXE_SW_RESET_BZ 0x10
103 #define AXE_SW_RESET_IPRL 0x20
104 #define AXE_SW_RESET_IPPD 0x40
105
106
107 #define AXE_178_RESET_MAGIC 0x40
108
109 #define AXE_178_MEDIA_GMII 0x0001
110 #define AXE_MEDIA_FULL_DUPLEX 0x0002
111 #define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004
112
113 #define AXE_178_MEDIA_MAGIC 0x0004
114 #define AXE_178_MEDIA_ENCK 0x0008
115 #define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010
116 #define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010
117 #define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020
118 #define AXE_178_MEDIA_JUMBO_EN 0x0040
119 #define AXE_178_MEDIA_LTPF_ONLY 0x0080
120 #define AXE_178_MEDIA_RX_EN 0x0100
121 #define AXE_178_MEDIA_100TX 0x0200
122 #define AXE_178_MEDIA_SBP 0x0800
123 #define AXE_178_MEDIA_SUPERMAC 0x1000
124
125 #define AXE_RXCMD_PROMISC 0x0001
126 #define AXE_RXCMD_ALLMULTI 0x0002
127 #define AXE_172_RXCMD_UNICAST 0x0004
128 #define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004
129 #define AXE_RXCMD_BROADCAST 0x0008
130 #define AXE_RXCMD_MULTICAST 0x0010
131 #define AXE_RXCMD_ENABLE 0x0080
132 #define AXE_178_RXCMD_MFB 0x0300
133
134 #define AXE_NOPHY 0xE0
135 #define AXE_INTPHY 0x10
136
137 #define AXE_TIMEOUT 1000
138 #define AXE_172_BUFSZ 1536
139 #define AXE_178_MIN_BUFSZ 2048
140 #define AXE_178_MAX_BUFSZ 16384
141
142 #define AXE_RX_LIST_CNT 1
143 #define AXE_TX_LIST_CNT 1
144
145 #define AXE_CTL_READ 0x01
146 #define AXE_CTL_WRITE 0x02
147
148 #define AXE_CONFIG_NO 1
149 #define AXE_IFACE_IDX 0
150
151
152
153
154
155 #define AXE_ENDPT_RX 0x0
156 #define AXE_ENDPT_TX 0x1
157 #define AXE_ENDPT_INTR 0x2
158 #define AXE_ENDPT_MAX 0x3
159
160 struct axe_type {
161 struct usb_devno axe_dev;
162 u_int16_t axe_flags;
163 #define AX178 0x0001
164 #define AX772 0x0002
165 };
166
167 struct axe_softc;
168
169 struct axe_chain {
170 struct axe_softc *axe_sc;
171 usbd_xfer_handle axe_xfer;
172 char *axe_buf;
173 struct mbuf *axe_mbuf;
174 int axe_accum;
175 int axe_idx;
176 };
177
178 struct axe_cdata {
179 struct axe_chain axe_tx_chain[AXE_TX_LIST_CNT];
180 struct axe_chain axe_rx_chain[AXE_RX_LIST_CNT];
181 int axe_tx_prod;
182 int axe_tx_cons;
183 int axe_tx_cnt;
184 int axe_rx_prod;
185 };
186
187 struct axe_sframe_hdr {
188 u_int16_t len;
189 u_int16_t ilen;
190 } __packed;
191
192 struct axe_softc {
193 struct device axe_dev;
194 #define GET_MII(sc) (&(sc)->axe_mii)
195 struct arpcom arpcom;
196 #define GET_IFP(sc) (&(sc)->arpcom.ac_if)
197 struct mii_data axe_mii;
198 usbd_device_handle axe_udev;
199 usbd_interface_handle axe_iface;
200
201 u_int16_t axe_vendor;
202 u_int16_t axe_product;
203
204 u_int16_t axe_flags;
205
206 int axe_ed[AXE_ENDPT_MAX];
207 usbd_pipe_handle axe_ep[AXE_ENDPT_MAX];
208 int axe_unit;
209 int axe_if_flags;
210 struct axe_cdata axe_cdata;
211 struct timeout axe_stat_ch;
212
213 int axe_refcnt;
214 char axe_dying;
215 char axe_attached;
216
217 struct usb_task axe_tick_task;
218 struct usb_task axe_stop_task;
219
220 struct rwlock axe_mii_lock;
221
222 int axe_link;
223 unsigned char axe_ipgs[3];
224 unsigned char axe_phyaddrs[2];
225 struct timeval axe_rx_notice;
226 u_int axe_bufsz;
227 };