1 /* $OpenBSD: sbreg.h,v 1.6 2002/07/02 19:38:55 nate Exp $ */
2 /* $NetBSD: sbreg.h,v 1.24 1997/08/24 23:24:51 augustss Exp $ */
3
4 /*
5 * Copyright (c) 1991-1993 Regents of the University of California.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the Computer Systems
19 * Engineering Group at Lawrence Berkeley Laboratory.
20 * 4. Neither the name of the University nor of the Laboratory may be used
21 * to endorse or promote products derived from this software without
22 * specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * From: Header: sbreg.h,v 1.3 93/07/18 14:07:28 mccanne Exp (LBL)
37 */
38
39 /*
40 * SoundBlaster register definitions.
41 * See "The Developer Kit for Sound Blaster Series, User's Guide" for more
42 * complete information (avialable from Creative Labs, Inc.). We refer
43 * to this documentation as "SBK".
44 *
45 * We handle two types of cards: the basic SB version 2.0+, and
46 * the SB PRO. There are several distinct pieces of the hardware:
47 *
48 * joystick port (independent of I/O base address)
49 * FM synth (stereo on PRO)
50 * mixer (PRO only)
51 * DSP (sic)
52 * CD-ROM (PRO only)
53 *
54 * The MIDI capabilities are handled by the DSP unit.
55 */
56
57 /*
58 * Address map. The SoundBlaster can be configured (via jumpers) for
59 * either base I/O address 0x220 or 0x240. The encodings below give
60 * the offsets to specific SB ports. SBP stands for SB port offset.
61 */
62 #define SBP_LFM_STATUS 0 /* R left FM status port */
63 #define SBP_LFM_ADDR 0 /* W left FM address register */
64 #define SBP_LFM_DATA 1 /* RW left FM data port */
65 #define SBP_RFM_STATUS 2 /* R right FM status port */
66 #define SBP_RFM_ADDR 2 /* W right FM address register */
67 #define SBP_RFM_DATA 3 /* RW right FM data port */
68
69 #define SBP_FM_STATUS 8 /* R FM status port */
70 #define SBP_FM_ADDR 8 /* W FM address register */
71 #define SBP_FM_DATA 9 /* RW FM data port */
72 #define SBP_MIXER_ADDR 4 /* W mixer address register */
73 #define SBP_MIXER_DATA 5 /* RW mixer data port */
74
75 #define SBP_MIX_RESET 0x00 /* mixer reset port, value */
76 #define SBP_1335_MASTER_VOL 0x02
77 #define SBP_1335_MIDI_VOL 0x06
78 #define SBP_1335_CD_VOL 0x08
79 #define SBP_1335_VOICE_VOL 0x0A
80
81 #define SBP_VOICE_VOL 0x04
82 #define SBP_MIC_VOL 0x0A /* warning: only one channel of volume... */
83 #define SBP_MASTER_VOL 0x22
84 #define SBP_MIDI_VOL 0x26
85 #define SBP_CD_VOL 0x28
86 #define SBP_LINE_VOL 0x2E
87
88 #define SBP_RECORD_SOURCE 0x0C
89 #define SBP_STEREO 0x0E
90 #define SBP_PLAYMODE_STEREO 0x2
91 #define SBP_PLAYMODE_MONO 0x0
92 #define SBP_PLAYMODE_MASK 0x2
93 #define SBP_OUTFILTER 0x0E
94 #define SBP_INFILTER 0x0C
95
96 #define SBP_RECORD_FROM(src, filteron, high) ((src) | (filteron) | (high))
97 #define SBP_FILTER_ON 0x0
98 #define SBP_FILTER_OFF 0x20
99 #define SBP_IFILTER_MASK 0x28
100 #define SBP_OFILTER_MASK 0x20
101 #define SBP_IFILTER_LOW 0
102 #define SBP_IFILTER_HIGH 0x08
103 #define SBP_FROM_MIC 0x00
104 #define SBP_FROM_CD 0x02
105 #define SBP_FROM_LINE 0x06
106
107 #define SBP_SET_IRQ 0x80 /* Soft-configured irq (SB16-) */
108 #define SBP_SET_DRQ 0x81 /* Soft-configured drq (SB16-) */
109 #define SBP_IRQ_STATUS 0x82 /* Pending IRQ status (SB16-) */
110 #define SBP_IRQ_MPU401 0x04
111 #define SBP_IRQ_DMA16 0x02
112 #define SBP_IRQ_DMA8 0x01
113
114 #define SB16P_MASTER_L 0x30
115 #define SB16P_VOICE_L 0x32
116 #define SB16P_MIDI_L 0x34
117 #define SB16P_CD_L 0x36
118 #define SB16P_LINE_L 0x38
119 #define SB16P_MIC_L 0x3a
120 #define SB16P_PCSPEAKER 0x3b
121 #define SB16P_OSWITCH 0x3c
122 #define SB16P_ISWITCH_L 0x3d
123 #define SB16P_ISWITCH_R 0x3e
124 #define SB16P_SW_MIC 0x01
125 #define SB16P_SW_CD_R 0x02
126 #define SB16P_SW_CD_L 0x04
127 #define SB16P_SW_CD (SB16P_SW_CD_L|SB16P_SW_CD_R)
128 #define SB16P_SW_LINE_R 0x08
129 #define SB16P_SW_LINE_L 0x10
130 #define SB16P_SW_LINE (SB16P_SW_LINE_L|SB16P_SW_LINE_R)
131 #define SB16P_SW_MIDI_R 0x20
132 #define SB16P_SW_MIDI_L 0x40
133 #define SB16P_SW_MIDI (SB16P_SW_MIDI_L|SB16P_SW_MIDI_R)
134 #define SB16P_INPUT_GAIN_L 0x3f
135 #define SB16P_OUTPUT_GAIN_L 0x41
136 #define SB16P_TREBLE_L 0x44
137 #define SB16P_BASS_L 0x46
138 #define SB16P_L_TO_R(l) ((l)+1)
139
140 #define SB16P_AGC 0x43
141
142 #define SBP_RECORD_SOURCE_L 0x3d
143 #define SBP_RECORD_SOURCE_R 0x3e
144 #define SBP_MIDI_SRC_R 0x20
145 #define SBP_LINE_SRC_R 0x08
146 #define SBP_CD_SRC_R 0x02
147 #define SBP_MIC_SRC 0x01
148 #define SB_SRC_R_TO_L(x) ((x) << 1)
149
150 #define SB_STEREO_GAIN(left, right) ((left) | ((right) >> 4))
151 #define SB_MIC_GAIN(v) ((v) >> 5)
152
153 #define SB_ADJUST_MIC_GAIN(sc, x) sbdsp_adjust((x), ISSB16CLASS(sc) ? 0xf8 : 0xc0)
154 #define SB_ADJUST_GAIN(sc, x) sbdsp_adjust((x), ISSB16CLASS(sc) ? 0xf8 : 0xe0)
155 #define SB_ADJUST_2_GAIN(sc, x) sbdsp_adjust((x), 0xc0)
156
157 #define SB_1335_GAIN(x) ((x) >> 4)
158 #define SB_1335_MASTER_GAIN(x) ((x) >> 5)
159
160 #define SBP_DSP_RESET 6 /* W reset port */
161 #define SB_MAGIC 0xaa /* card outputs on successful reset */
162 #define SBP_DSP_READ 10 /* R read port */
163 #define SBP_DSP_WRITE 12 /* W write port */
164 #define SBP_DSP_WSTAT 12 /* R write status */
165 #define SBP_DSP_RSTAT 14 /* R read status */
166 #define SB_DSP_BUSY 0x80
167 #define SB_DSP_READY 0x80
168 #define SBP_DSP_IRQACK8 14 /* R acknowledge DSP IRQ, 8-bit */
169 #define SBP_DSP_IRQACK16 15 /* R acknowledge DSP IRQ, 16-bit */
170 #define SBP_CDROM_DATA 16 /* RW send cmds/recv data */
171 #define SBP_CDROM_STATUS 17 /* R status port */
172 #define SBP_CDROM_RESET 18 /* W reset register */
173 #define SBP_CDROM_ENABLE 19 /* W enable register */
174
175 #define SBP_NPORT 24
176 #define SB_NPORT 16
177
178 /*
179 * DSP commands. This unit handles MIDI and audio capabilities.
180 * The DSP can be reset, data/commands can be read or written to it,
181 * and it can generate interrupts. Interrupts are generated for MIDI
182 * input or DMA completion. They seem to have neglected the fact
183 * that it would be nice to have a MIDI transmission complete interrupt.
184 * Worse, the DMA engine is half-duplex. This means you need to do
185 * (timed) programmed I/O to be able to record and play simulataneously.
186 */
187 #define SB_DSP_DACWRITE 0x10 /* programmed I/O write to DAC */
188 #define SB_DSP_WDMA 0x14 /* begin 8-bit linear DMA output */
189 #define SB_DSP_WDMA_2 0x16 /* begin 2-bit ADPCM DMA output */
190 #define SB_DSP_WDMA_LOOP 0x1C /* begin 8-bit linear DMA output loop */
191 #define SB_DSP_ADCREAD 0x20 /* programmed I/O read from ADC */
192 #define SB_DSP_RDMA 0x24 /* begin 8-bit linear DMA input */
193 #define SB_DSP_RDMA_LOOP 0x2C /* begin 8-bit linear DMA input loop */
194 #define SB_MIDI_POLL 0x30 /* initiate a polling read for MIDI */
195 #define SB_MIDI_READ 0x31 /* read a MIDI byte on recv intr */
196 #define SB_MIDI_UART_POLL 0x34 /* enter UART mode w/ read polling */
197 #define SB_MIDI_UART_INTR 0x35 /* enter UART mode w/ read intrs */
198 #define SB_MIDI_WRITE 0x38 /* write a MIDI byte (non-UART mode) */
199 #define SB_DSP_TIMECONST 0x40 /* set ADAC time constant */
200 #define SB_DSP16_OUTPUTRATE 0x41 /* set ADAC output rate */
201 #define SB_DSP16_INPUTRATE 0x42 /* set ADAC input rate */
202 #define SB_DSP_BLOCKSIZE 0x48 /* set blk size for high speed xfer */
203 #define SB_DSP_WDMA_4 0x74 /* begin 4-bit ADPCM DMA output */
204 #define SB_DSP_WDMA_2_6 0x76 /* begin 2.6-bit ADPCM DMA output */
205 #define SB_DSP_SILENCE 0x80 /* send a block of silence */
206 #define SB_DSP_HS_OUTPUT 0x90 /* set high speed mode for wdma */
207 #define SB_DSP_HS_INPUT 0x98 /* set high speed mode for rdma */
208 #define SB_DSP_RECORD_MONO 0xA0 /* set mono recording */
209 #define SB_DSP_RECORD_STEREO 0xA8 /* set stereo recording */
210 #define SB_DSP16_WDMA_16 0xB6 /* begin 16-bit linear output */
211 #define SB_DSP16_RDMA_16 0xBE /* begin 16-bit linear input */
212 #define SB_DSP16_WDMA_8 0xC6 /* begin 8-bit linear output */
213 #define SB_DSP16_RDMA_8 0xCE /* begin 8-bit linear input */
214 #define SB_DSP_HALT 0xd0 /* temporarily suspend DMA */
215 #define SB_DSP_SPKR_ON 0xd1 /* turn speaker on */
216 #define SB_DSP_SPKR_OFF 0xd3 /* turn speaker off */
217 #define SB_DSP_CONT 0xd4 /* continue suspended DMA */
218 #define SB_DSP_RD_SPKR 0xd8 /* get speaker status */
219 #define SB_SPKR_OFF 0x00
220 #define SB_SPKR_ON 0xff
221 #define SB_DSP_VERSION 0xe1 /* get version number */
222
223 #define SB_BMODE_UNSIGNED 0x00
224 #define SB_BMODE_SIGNED 0x10
225 #define SB_BMODE_STEREO 0x20
226
227 /* Some of these come from linux driver (It serves as convenient unencumbered
228 documentation) */
229 #define JAZZ16_READ_VER 0xFA /* 0x12 means ProSonic/Jazz16? */
230 #define JAZZ16_VER_JAZZ 0x12
231 #define JAZZ16_SET_DMAINTR 0xFB
232
233 #define JAZZ16_CONFIG_PORT 0x201
234 #define JAZZ16_WAKEUP 0xAF
235 #define JAZZ16_SETBASE 0x50
236
237 #define JAZZ16_RECORD_STEREO 0xAC /* 16-bit record */
238 #define JAZZ16_RECORD_MONO 0xA4 /* 16-bit record */
239
240 /*
241 * These come from Jazz16 chipset documentation, which doesn't include
242 * full register details, alas. Their source code CD-ROM probably includes
243 * details, but it has an NDA attached.
244 */
245 #define JAZZ16_DIR_PB 0x10
246 #define JAZZ16_SINGLE_PB 0x14
247 #define JAZZ16_SINGLE_ALAW_PB 0x17
248 #define JAZZ16_CONT_PB 0x1C
249 #define JAZZ16_CONT_ALAW_PB 0x1F
250 #define JAZZ16_DIR_PCM_REC 0x20
251 #define JAZZ16_SINGLE_REC 0x24
252 #define JAZZ16_SINGLE_ALAW_REC 0x27
253 #define JAZZ16_CONT_REC 0x2C
254 #define JAZZ16_CONT_ALAW_REC 0x2F
255 #define JAZZ16_SINGLE_ADPCM_PB 0x74
256 #define JAZZ16_SINGLE_MULAW_PB 0x77
257 #define JAZZ16_CONT_ADPCM_PB 0x7C
258 #define JAZZ16_SINGLE_ADPCM_REC 0x84
259 #define JAZZ16_SINGLE_MULAW_REC 0x87
260 #define JAZZ16_CONT_ADPCM_REC 0x8C
261 #define JAZZ16_CONT_MULAW_REC 0x8F
262 #define JAZZ16_CONT_PB_XX 0x90
263 #define JAZZ16_SINGLE_PB_XX 0x91
264 #define JAZZ16_SINGLE_REC_XX 0x98
265 #define JAZZ16_CONT_REC_XX 0x99
266
267
268 /*
269 * The ADPCM encodings are differential, meaning each sample represents
270 * a difference to add to a running sum. The initial value is called the
271 * reference, or reference byte. Any of the ADPCM DMA transfers can specify
272 * that the given transfer begins with a reference byte by or'ing
273 * in the bit below.
274 */
275 #define SB_DSP_REFERENCE 1
276
277 /*
278 * Macros to detect valid hardware configuration data.
279 */
280 #define SBP_IRQ_VALID(irq) ((irq) == 5 || (irq) == 7 || (irq) == 9 || (irq) == 10)
281 #define SB_IRQ_VALID(irq) ((irq) == 3 || (irq) == 5 || (irq) == 7 || (irq) == 9)
282
283 #define SB16_DRQ_VALID(chan) ((chan) == 0 || (chan) == 1 || (chan) == 3 || \
284 (chan) == 5 || (chan) == 6 || (chan) == 7)
285 #define SBP_DRQ_VALID(chan) ((chan) == 0 || (chan) == 1 || (chan) == 3)
286 #define SB_DRQ_VALID(chan) ((chan) == 1)
287
288 #define SB_BASE_VALID(base) ((base) == 0x220 || (base) == 0x240)
289
290 #define SB_INPUT_RATE 0
291 #define SB_OUTPUT_RATE 1
292