1 /* $OpenBSD: elink3reg.h,v 1.15 2005/02/17 18:07:36 jfb Exp $ */
2 /* $NetBSD: elink3reg.h,v 1.13 1997/04/27 09:42:34 veego Exp $ */
3
4 /*
5 * Copyright (c) 1995 Herb Peyerl <hpeyerl@beer.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Herb Peyerl.
19 * 4. The name of Herb Peyerl may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * These define the EEPROM data structure. They are used in the probe
37 * function to verify the existence of the adapter after having sent
38 * the ID_Sequence.
39 *
40 * There are others but only the ones we use are defined here.
41 */
42 #define EEPROM_NODE_ADDR_0 0x0 /* Word */
43 #define EEPROM_NODE_ADDR_1 0x1 /* Word */
44 #define EEPROM_NODE_ADDR_2 0x2 /* Word */
45 #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */
46 #define EEPROM_MFG_ID 0x7 /* 0x6d50 */
47 #define EEPROM_ADDR_CFG 0x8 /* Base addr */
48 #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
49 #define EEPROM_OEM_ADDR0 0xa
50 #define EEPROM_PNP 0x13 /* PNP mode and such? */
51
52 /*
53 * These are the registers for the 3Com 3c509 and their bit patterns when
54 * applicable. They have been taken out of the "EtherLink III Parallel
55 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual
56 * from 3com.
57 */
58 #define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a command reg. */
59 #define EP_STATUS 0x0e /* Read. BASE+0x0e is always status reg. */
60 #define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window reg. */
61
62 /*
63 * Window 0 registers. Setup.
64 */
65 /* Write */
66 #define EP_W0_EEPROM_DATA 0x0c
67 #define EP_W0_EEPROM_COMMAND 0x0a
68 #define EP_W0_RESOURCE_CFG 0x08
69 #define EP_W0_ADDRESS_CFG 0x06
70 #define EP_W0_CONFIG_CTRL 0x04
71 /* Read */
72 #define EP_W0_PRODUCT_ID 0x02
73 #define EP_W0_MFG_ID 0x00
74
75 /*
76 * Window 1 registers. Operating Set.
77 */
78 /* Write */
79 #define EP_W1_TX_PIO_WR_2 0x02
80 #define EP_W1_TX_PIO_WR_1 0x00
81 /* Read */
82 #define EP_W1_FREE_TX 0x0c
83 #define EP_W1_TX_STATUS 0x0b /* byte */
84 #define EP_W1_TIMER 0x0a /* byte */
85 #define EP_W1_RX_STATUS 0x08
86 #define EP_W1_RX_PIO_RD_2 0x02
87 #define EP_W1_RX_PIO_RD_1 0x00
88
89 /* Special registers used by the RoadRunner. These are used to program
90 * a FIFO buffer to reduce the PCMCIA->PCI bridge latency during PIO.
91 */
92 #define EP_W1_RUNNER_RDCTL 0x16
93 #define EP_W1_RUNNER_WRCTL 0x1c
94
95 /*
96 * Window 2 registers. Station Address Setup/Read
97 */
98 /* Read/Write */
99 #define EP_W2_RECVMASK_0 0x06
100 #define EP_W2_ADDR_5 0x05
101 #define EP_W2_ADDR_4 0x04
102 #define EP_W2_ADDR_3 0x03
103 #define EP_W2_ADDR_2 0x02
104 #define EP_W2_ADDR_1 0x01
105 #define EP_W2_ADDR_0 0x00
106
107 /*
108 * Window 3 registers. FIFO Management.
109 */
110 /* Read */
111 #define EP_W3_FREE_TX 0x0c
112 #define EP_W3_FREE_RX 0x0a
113 /* Read/Write, at least on busmastering cards. */
114 #define EP_W3_INTERNAL_CONFIG 0x00 /* 32 bits */
115 #define EP_W3_OTHER_INT 0x04 /* 8 bits */
116 #define EP_W3_PIO_RESERVED 0x05 /* 8 bits */
117 #define EP_W3_MAC_CONTROL 0x06 /* 16 bits */
118 #define EP_W3_RESET_OPTIONS 0x08 /* 16 bits */
119
120 /*
121 * Window 4 registers. Diagnostics.
122 */
123 /* Read/Write */
124 #define EP_W4_MEDIA_TYPE 0x0a
125 #define EP_W4_CTRLR_STATUS 0x08
126 #define EP_W4_NET_DIAG 0x06
127 #define EP_W4_FIFO_DIAG 0x04
128 #define EP_W4_HOST_DIAG 0x02
129 #define EP_W4_TX_DIAG 0x00
130
131 /*
132 * Window 4 offset 8 is the PHY Management register on the
133 * 3c90x.
134 */
135 #define EP_W4_BOOM_PHYSMGMT 0x08
136 #define PHYSMGMT_CLK 0x0001
137 #define PHYSMGMT_DATA 0x0002
138 #define PHYSMGMT_DIR 0x0004
139
140 /*
141 * Window 5 Registers. Results and Internal status.
142 */
143 /* Read */
144 #define EP_W5_READ_0_MASK 0x0c
145 #define EP_W5_INTR_MASK 0x0a
146 #define EP_W5_RX_FILTER 0x08
147 #define EP_W5_RX_EARLY_THRESH 0x06
148 #define EP_W5_TX_AVAIL_THRESH 0x02
149 #define EP_W5_TX_START_THRESH 0x00
150
151 /*
152 * Window 6 registers. Statistics.
153 */
154 /* Read/Write */
155 #define TX_TOTAL_OK 0x0c
156 #define RX_TOTAL_OK 0x0a
157 #define TX_DEFERRALS 0x08
158 #define RX_FRAMES_OK 0x07
159 #define TX_FRAMES_OK 0x06
160 #define RX_OVERRUNS 0x05
161 #define TX_COLLISIONS 0x04
162 #define TX_AFTER_1_COLLISION 0x03
163 #define TX_AFTER_X_COLLISIONS 0x02
164 #define TX_NO_SQE 0x01
165 #define TX_CD_LOST 0x00
166
167 /*
168 * Window 7 registers.
169 * Address and length for a single bus-master DMA transfer.
170 */
171 #define EP_W7_MASTER_ADDDRES 0x00
172 #define EP_W7_RX_ERROR 0x04
173 #define EP_W7_MASTER_LEN 0x06
174 #define EP_W7_RX_STATUS 0x08
175 #define EP_W7_TIMER 0x0a
176 #define EP_W7_TX_STATUS 0x0b
177 #define EP_W7_MASTER_STATUS 0x0c
178
179 /*
180 * Window 7 registers.
181 * Address and length for a single bus-master DMA transfer.
182 */
183 #define EP_W7_MASTER_ADDDRES 0x00
184 #define EP_W7_RX_ERROR 0x04
185 #define EP_W7_MASTER_LEN 0x06
186 #define EP_W7_RX_STATUS 0x08
187 #define EP_W7_TIMER 0x0a
188 #define EP_W7_TX_STATUS 0x0b
189 #define EP_W7_MASTER_STATUS 0x0c
190
191 /*
192 * Register definitions.
193 */
194
195 /*
196 * Command register. All windows.
197 *
198 * 16 bit register.
199 * 15-11: 5-bit code for command to be executed.
200 * 10-0: 11-bit arg if any. For commands with no args;
201 * this can be set to anything.
202 */
203 #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms after issuing */
204 #define WINDOW_SELECT (u_short) (0x1<<11)
205 #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to determine
206 whether this is needed. If so;
207 wait 800 uSec before using trans-
208 ceiver. */
209 #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on power-up */
210 #define RX_ENABLE (u_short) (0x4<<11)
211 #define RX_RESET (u_short) (0x5<<11)
212 #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11)
213 #define TX_ENABLE (u_short) (0x9<<11)
214 #define TX_DISABLE (u_short) (0xa<<11)
215 #define TX_RESET (u_short) (0xb<<11)
216 #define REQ_INTR (u_short) (0xc<<11)
217
218 /*
219 * The following C_* acknowledge the various interrupts.
220 * Some of them don't do anything. See the manual.
221 */
222 #define ACK_INTR (u_short) (0x6800)
223 # define C_INTR_LATCH (u_short) (ACK_INTR|0x01)
224 # define C_CARD_FAILURE (u_short) (ACK_INTR|0x02)
225 # define C_TX_COMPLETE (u_short) (ACK_INTR|0x04)
226 # define C_TX_AVAIL (u_short) (ACK_INTR|0x08)
227 # define C_RX_COMPLETE (u_short) (ACK_INTR|0x10)
228 # define C_RX_EARLY (u_short) (ACK_INTR|0x20)
229 # define C_INT_RQD (u_short) (ACK_INTR|0x40)
230 # define C_UPD_STATS (u_short) (ACK_INTR|0x80)
231
232 #define SET_INTR_MASK (u_short) (0x0e<<11)
233
234 /* busmastering-cards only? */
235 #define STATUS_ENABLE (u_short) (0x0f<<11)
236
237 #define SET_RD_0_MASK (u_short) (0x0f<<11)
238
239 #define SET_RX_FILTER (u_short) (0x10<<11)
240 # define FIL_INDIVIDUAL (u_short) (0x01)
241 # define FIL_MULTICAST (u_short) (0x02)
242 # define FIL_BRDCST (u_short) (0x04)
243 # define FIL_PROMISC (u_short) (0x08)
244
245 #define SET_RX_EARLY_THRESH (u_short) (0x11<<11)
246 #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11)
247 #define SET_TX_START_THRESH (u_short) (0x13<<11)
248 #define START_DMA (u_short) (0x14<<11) /* busmaster-only */
249 # define START_DMA_TX (START_DMA | 0x0)) /* busmaster-only */
250 # define START_DMA_RX (START_DMA | 0x1) /* busmaster-only */
251 #define STATS_ENABLE (u_short) (0x15<<11)
252 #define STATS_DISABLE (u_short) (0x16<<11)
253 #define STOP_TRANSCEIVER (u_short) (0x17<<11)
254
255 /* Only on adapters that support power management: */
256 #define POWERUP (u_short) (0x1b<<11)
257 #define POWERDOWN (u_short) (0x1c<<11)
258 #define POWERAUTO (u_short) (0x1d<<11)
259
260 /*
261 * Command parameter that disables threshold interrupts
262 * PIO (3c509) cards use 2044. The fifo word-oriented and 2044--2047 work.
263 * "busmastering" cards need 8188.
264 * The implicit two-bit upshift done by busmastering cards means
265 * a value of 2047 disables threshold interrupts on both.
266 */
267 #define EP_THRESH_DISABLE 2047
268
269 /*
270 * Status register. All windows.
271 *
272 * 15-13: Window number(0-7).
273 * 12: Command_in_progress.
274 * 11: reserved / DMA in progress on busmaster cards.
275 * 10: reserved.
276 * 9: reserved.
277 * 8: reserved / DMA done on busmaster cards.
278 * 7: Update Statistics.
279 * 6: Interrupt Requested.
280 * 5: RX Early.
281 * 4: RX Complete.
282 * 3: TX Available.
283 * 2: TX Complete.
284 * 1: Adapter Failure.
285 * 0: Interrupt Latch.
286 */
287 #define S_INTR_LATCH (u_short) (0x0001)
288 #define S_CARD_FAILURE (u_short) (0x0002)
289 #define S_TX_COMPLETE (u_short) (0x0004)
290 #define S_TX_AVAIL (u_short) (0x0008)
291 #define S_RX_COMPLETE (u_short) (0x0010)
292 #define S_RX_EARLY (u_short) (0x0020)
293 #define S_INT_RQD (u_short) (0x0040)
294 #define S_UPD_STATS (u_short) (0x0080)
295 #define S_DMA_DONE (u_short) (0x0100) /* DMA cards only */
296 #define S_DOWN_COMPLETE (u_short) (0x0200) /* DMA cards only */
297 #define S_UP_COMPLETE (u_short) (0x0400) /* DMA cards only */
298 #define S_DMA_IN_PROGRESS (u_short) (0x0800) /* DMA cards only */
299 #define S_COMMAND_IN_PROGRESS (u_short) (0x1000)
300
301 /*
302 * FIFO Registers. RX Status.
303 *
304 * 15: Incomplete or FIFO empty.
305 * 14: 1: Error in RX Packet 0: Incomplete or no error.
306 * 14-11: Type of error. [14-11]
307 * 1000 = Overrun.
308 * 1011 = Run Packet Error.
309 * 1100 = Alignment Error.
310 * 1101 = CRC Error.
311 * 1001 = Oversize Packet Error (>1514 bytes)
312 * 0010 = Dribble Bits.
313 * (all other error codes, no errors.)
314 *
315 * 10-0: RX Bytes (0-1514)
316 */
317 #define ERR_INCOMPLETE (u_short) (0x8000)
318 #define ERR_RX (u_short) (0x4000)
319 #define ERR_MASK (u_short) (0x7800)
320 #define ERR_OVERRUN (u_short) (0x4000)
321 #define ERR_RUNT (u_short) (0x5800)
322 #define ERR_ALIGNMENT (u_short) (0x6000)
323 #define ERR_CRC (u_short) (0x6800)
324 #define ERR_OVERSIZE (u_short) (0x4800)
325 #define ERR_DRIBBLE (u_short) (0x1000)
326
327 /*
328 * TX Status
329 *
330 * Reports the transmit status of a completed transmission. Writing this
331 * register pops the transmit completion stack.
332 *
333 * Window 1/Port 0x0b.
334 *
335 * 7: Complete
336 * 6: Interrupt on successful transmission requested.
337 * 5: Jabber Error (TP Only, TX Reset required. )
338 * 4: Underrun (TX Reset required. )
339 * 3: Maximum Collisions.
340 * 2: TX Status Overflow.
341 * 1-0: Undefined.
342 *
343 */
344 #define TXS_COMPLETE 0x80
345 #define TXS_INTR_REQ 0x40
346 #define TXS_JABBER 0x20
347 #define TXS_UNDERRUN 0x10
348 #define TXS_MAX_COLLISION 0x08
349 #define TXS_STATUS_OVERFLOW 0x04
350
351 /*
352 * RX status
353 * Window 1/Port 0x08.
354 */
355 #define RX_BYTES_MASK (u_short) (0x07ff)
356
357 /*
358 * Internal Config and MAC control (Window 3)
359 * Window 3 / Port 0: 32-bit internal config register:
360 * bits 0-2: fifo buffer ram size
361 * 3: ram width (word/byte) (ro)
362 * 4-5: ram speed
363 * 6-7: rom size
364 * 8-15: reserved
365 *
366 * 16-17: ram split (5:3, 3:1, or 1:1).
367 * 18-19: reserved
368 * 20-22: selected media type
369 * 21: unused
370 * 24: (nonvolatile) driver should autoselect media
371 * 25-31: reserved
372 *
373 * The low-order 16 bits should generally not be changed by software.
374 * Offsets defined for two 16-bit words, to help out 16-bit busses.
375 */
376 #define CONFIG_RAMSIZE (u_short) 0x0007
377 #define CONFIG_RAMSIZE_SHIFT (u_short) 0
378
379 #define CONFIG_RAMWIDTH (u_short) 0x0008
380 #define CONFIG_RAMWIDTH_SHIFT (u_short) 3
381
382 #define CONFIG_RAMSPEED (u_short) 0x0030
383 #define CONFIG_RAMSPEED_SHIFT (u_short) 4
384 #define CONFIG_ROMSIZE (u_short) 0x00c0
385 #define CONFIG_ROMSIZE_SHIFT (u_short) 6
386
387 /* Window 3/port 2 */
388 #define CONFIG_RAMSPLIT (u_short) 0x0003
389 #define CONFIG_RAMSPLIT_SHIFT (u_short) 0
390 #define CONFIG_MEDIAMASK (u_short) 0x0070
391 #define CONFIG_MEDIAMASK_SHIFT (u_short) 4
392
393 /*
394 * MAC_CONTROL (Window 3)
395 */
396 #define MAC_CONTROL_FDX 0x20 /* full-duplex mode */
397
398 /* Active media in EP_W3_RESET_OPTIONS mediamask bits */
399
400 #define EPMEDIA_10BASE_T (u_short) 0x00
401 #define EPMEDIA_AUI (u_short) 0x01
402 #define EPMEDIA_RESV1 (u_short) 0x02
403 #define EPMEDIA_10BASE_2 (u_short) 0x03
404 #define EPMEDIA_100BASE_TX (u_short) 0x04
405 #define EPMEDIA_100BASE_FX (u_short) 0x05
406 #define EPMEDIA_MII (u_short) 0x06
407 #define EPMEDIA_100BASE_T4 (u_short) 0x07
408
409
410 #define CONFIG_AUTOSELECT (u_short) 0x0100
411 #define CONFIG_AUTOSELECT_SHIFT (u_short) 8
412
413 /*
414 * RESET_OPTIONS (Window 4, on Demon/Vortex/Boomerang only)
415 * also mapped to PCI configuration space on PCI adaptors.
416 *
417 * (same register as Vortex EP_W3_RESET_OPTIONS, mapped to pci-config space)
418 */
419 #define EP_PCI_100BASE_T4 (1<<0)
420 #define EP_PCI_100BASE_TX (1<<1)
421 #define EP_PCI_100BASE_FX (1<<2)
422 #define EP_PCI_10BASE_T (1<<3)
423 # define EP_PCI_UTP EP_PCI_10BASE_T
424 #define EP_PCI_BNC (1<<4)
425 #define EP_PCI_AUI (1<<5)
426 #define EP_PCI_100BASE_MII (1<<6)
427 #define EP_PCI_INTERNAL_VCO (1<<8)
428
429 #define EP_RUNNER_MII_RESET 0x4000
430 #define EP_RUNNER_ENABLE_MII 0x8000
431
432 /*
433 * FIFO Status (Window 4)
434 *
435 * Supports FIFO diagnostics
436 *
437 * Window 4/Port 0x04.1
438 *
439 * 15: 1=RX receiving (RO). Set when a packet is being received
440 * into the RX FIFO.
441 * 14: Reserved
442 * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt.
443 * Requires RX Reset or Global Reset command to recover.
444 * It is generated when you read past the end of a packet -
445 * reading past what has been received so far will give bad
446 * data.
447 * 12: 1=RX status overrun (RO). Set when there are already 8
448 * packets in the RX FIFO. While this bit is set, no additional
449 * packets are received. Requires no action on the part of
450 * the host. The condition is cleared once a packet has been
451 * read out of the RX FIFO.
452 * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there
453 * may not be an overrun packet yet). While this bit is set,
454 * no additional packets will be received (some additional
455 * bytes can still be pending between the wire and the RX
456 * FIFO). Requires no action on the part of the host. The
457 * condition is cleared once a few bytes have been read out
458 * from the RX FIFO.
459 * 10: 1=TX overrun (RO). Generates adapter failure interrupt.
460 * Requires TX Reset or Global Reset command to recover.
461 * Disables Transmitter.
462 * 9-8: Unassigned.
463 * 7-0: Built in self test bits for the RX and TX FIFO's.
464 */
465 #define FIFOS_RX_RECEIVING (u_short) 0x8000
466 #define FIFOS_RX_UNDERRUN (u_short) 0x2000
467 #define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000
468 #define FIFOS_RX_OVERRUN (u_short) 0x0800
469 #define FIFOS_TX_OVERRUN (u_short) 0x0400
470
471 /*
472 * ISA/eisa CONFIG_CNTRL media-present bits.
473 */
474 #define EP_W0_CC_AUI (1<<13)
475 #define EP_W0_CC_BNC (1<<12)
476 #define EP_W0_CC_UTP (1<<9)
477
478
479 /* EEPROM state flags/commands */
480 #define EEPROM_BUSY (1<<15)
481 #define EEPROM_TST_MODE (1<<14)
482 #define READ_EEPROM (1<<7)
483
484 /* For the RoadRunner chips... */
485 #define WRITE_EEPROM_RR 0x100
486 #define READ_EEPROM_RR 0x200
487 #define ERASE_EEPROM_RR 0x300
488
489 /* window 4, MEDIA_STATUS bits */
490 #define SQE_ENABLE 0x08 /* Enables SQE on AUI ports */
491 #define JABBER_GUARD_ENABLE 0x40
492 #define LINKBEAT_ENABLE 0x80
493 #define ENABLE_UTP (JABBER_GUARD_ENABLE|LINKBEAT_ENABLE)
494 #define DISABLE_UTP 0x0
495 #define LINKBEAT_DETECT 0x800
496 #define MEDIA_LED 0x0001 /* Link LED for 3C589E */
497
498 /*
499 * ep_connectors softc media-preset bitflags
500 */
501 #define EPC_AUI 0x01
502 #define EPC_BNC 0x02
503 #define EPC_RESERVED 0x04
504 #define EPC_UTP 0x08
505 #define EPC_100TX 0x10
506 #define EPC_100FX 0x20
507 #define EPC_MII 0x40
508 #define EPC_100T4 0x80
509
510 /*
511 * Misc defines for various things.
512 */
513 #define TAG_ADAPTER 0xd0
514 #define ACTIVATE_ADAPTER_TO_CONFIG 0xff
515 #define ENABLE_DRQ_IRQ 0x0001
516 #define MFG_ID 0x506d /* `TCM' */
517 #define PROD_ID_3C509 0x5090 /* 509[0-f] */
518 #define GO_WINDOW(x) bus_space_write_2(sc->sc_iot, \
519 sc->sc_ioh, EP_COMMAND, WINDOW_SELECT|x)
520
521 /* Used to probe for large-packet support. */
522 #define EP_LARGEWIN_PROBE EP_THRESH_DISABLE
523 #define EP_LARGEWIN_MASK 0xffc