1 /* $OpenBSD: cacreg.h,v 1.4 2003/11/16 20:30:06 avsm Exp $ */
2 /* $NetBSD: cacreg.h,v 1.5 2001/01/10 16:48:04 ad Exp $ */
3
4 /*-
5 * Copyright (c) 2000 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Andrew Doran.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*-
41 * Copyright (c) 1999 Jonathan Lemon
42 * All rights reserved.
43 *
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
46 * are met:
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
63 * SUCH DAMAGE.
64 */
65
66 #ifndef _IC_CACREG_H_
67 #define _IC_CACREG_H_
68
69 /* Board register offsets */
70 #define CAC_REG_CMD_FIFO 0x04
71 #define CAC_REG_DONE_FIFO 0x08
72 #define CAC_REG_INTR_MASK 0x0C
73 #define CAC_REG_STATUS 0x10
74 #define CAC_REG_INTR_PENDING 0x14
75
76 #define CAC_42REG_CMD_FIFO 0x40
77 #define CAC_42REG_DONE_FIFO 0x44
78 #define CAC_42REG_INTR_MASK 0x34
79 #define CAC_42REG_STATUS 0x30
80
81 #define CAC_42_EXTINT 0x08
82
83 #define CAC_EISAREG_INTR_MASK 0x01
84 #define CAC_EISAREG_LOCAL_MASK 0x04
85 #define CAC_EISAREG_LOCAL_DOORBELL 0x05
86 #define CAC_EISAREG_SYSTEM_MASK 0x06
87 #define CAC_EISAREG_SYSTEM_DOORBELL 0x07
88 #define CAC_EISAREG_LIST_ADDR 0x08
89 #define CAC_EISAREG_LIST_LEN 0x0c
90 #define CAC_EISAREG_TAG 0x0f
91 #define CAC_EISAREG_COMPLETE_ADDR 0x10
92 #define CAC_EISAREG_LIST_STATUS 0x16
93
94 /* EISA channel control */
95 #define CAC_EISA_CHANNEL_BUSY 0x01
96 #define CAC_EISA_CHANNEL_CLEAR 0x02
97
98 /* Interrupt mask values */
99 #define CAC_INTR_DISABLE 0x00
100 #define CAC_INTR_ENABLE 0x01
101
102 /* Interrupt status masks */
103 #define CAC_INTR_FIFO_NEMPTY 0x01
104
105 /* Command types */
106 #define CAC_CMD_GET_LOG_DRV_INFO 0x10
107 #define CAC_CMD_GET_CTRL_INFO 0x11
108 #define CAC_CMD_SENSE_DRV_STATUS 0x12
109 #define CAC_CMD_START_RECOVERY 0x13
110 #define CAC_CMD_GET_PHYS_DRV_INFO 0x15
111 #define CAC_CMD_BLINK_DRV_LEDS 0x16
112 #define CAC_CMD_SENSE_DRV_LEDS 0x17
113 #define CAC_CMD_GET_LOG_DRV_EXT 0x18
114 #define CAC_CMD_GET_CTRL_INFO 0x11
115 #define CAC_CMD_READ 0x20
116 #define CAC_CMD_WRITE 0x30
117 #define CAC_CMD_WRITE_MEDIA 0x31
118 #define CAC_CMD_GET_CONFIG 0x50
119 #define CAC_CMD_SET_CONFIG 0x51
120 #define CAC_CMD_START_FIRMWARE 0x99
121 #define CAC_CMD_FLUSH_CACHE 0xc2
122
123 /* Return status codes */
124 #define CAC_RET_SOFT_ERROR 0x02
125 #define CAC_RET_HARD_ERROR 0x04
126 #define CAC_RET_CMD_INVALID 0x10
127 #define CAC_RET_CMD_REJECTED 0x14
128
129 struct cac_drive_info {
130 u_int16_t secsize;
131 u_int32_t secperunit;
132 u_int16_t ncylinders;
133 u_int8_t nheads;
134 u_int8_t signature;
135 u_int8_t psectors;
136 u_int16_t wprecomp;
137 u_int8_t max_acc;
138 u_int8_t control;
139 u_int16_t pcylinders;
140 u_int8_t ptracks;
141 u_int16_t landing_zone;
142 u_int8_t nsectors;
143 u_int8_t checksum;
144 u_int8_t mirror;
145 } __packed;
146
147 struct cac_controller_info {
148 u_int8_t num_drvs;
149 u_int32_t signature;
150 u_int8_t firm_rev[4];
151 u_int8_t rom_rev[4];
152 u_int8_t hw_rev;
153 u_int32_t bb_rev;
154 u_int32_t drv_present_map;
155 u_int32_t ext_drv_map;
156 u_int32_t board_id;
157 u_int8_t cfg_error;
158 u_int32_t non_disk_bits;
159 u_int8_t bad_ram_addr;
160 u_int8_t cpu_rev;
161 u_int8_t pdpi_rev;
162 u_int8_t epic_rev;
163 u_int8_t wcxc_rev;
164 u_int8_t marketing_rev;
165 u_int8_t ctlr_flags;
166 u_int8_t host_flags;
167 u_int8_t expand_dis;
168 u_int8_t scsi_chips;
169 u_int32_t max_req_blocks;
170 u_int32_t ctlr_clock;
171 u_int8_t drvs_per_bus;
172 u_int16_t big_drv_present_map[8];
173 u_int16_t big_ext_drv_map[8];
174 u_int16_t big_non_disk_map[8];
175 u_int16_t task_flags;
176 u_int8_t icl_bus;
177 u_int8_t red_modes;
178 u_int8_t cur_red_mode;
179 u_int8_t red_ctlr_stat;
180 u_int8_t red_fail_reason;
181 u_int8_t reserved[403];
182 } __packed;
183
184 struct cac_hdr {
185 u_int8_t drive; /* logical drive */
186 u_int8_t priority; /* block priority */
187 u_int16_t size; /* size of request, in words */
188 } __packed;
189
190 struct cac_req {
191 u_int16_t next; /* offset of next request */
192 u_int8_t command; /* command */
193 u_int8_t error; /* return error code */
194 u_int32_t blkno; /* block number */
195 u_int16_t bcount; /* block count */
196 u_int8_t sgcount; /* number of scatter/gather entries */
197 u_int8_t reserved; /* reserved */
198 } __packed;
199
200 struct cac_sgb {
201 u_int32_t length; /* length of S/G segment */
202 u_int32_t addr; /* physical address of block */
203 } __packed;
204
205 #endif /* !_IC_CACREG_H_ */