root/dev/ic/ar5212reg.h

INCLUDED FROM

DEFINITIONS

1. AR5K_AR5212_DMASIZE_4B
2. AR5K_AR5212_DMASIZE_8B
3. AR5K_AR5212_DMASIZE_16B
4. AR5K_AR5212_DMASIZE_32B
5. AR5K_AR5212_DMASIZE_64B
6. AR5K_AR5212_DMASIZE_128B
7. AR5K_AR5212_DMASIZE_256B
8. AR5K_AR5212_DMASIZE_512B
9. ar5k_ar5212_dmasize_t

    1 /*      $OpenBSD: ar5212reg.h,v 1.11 2007/03/12 01:04:52 reyk Exp $     */
    3 /*
    4  * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
    5  *
    6  * Permission to use, copy, modify, and distribute this software for any
    7  * purpose with or without fee is hereby granted, provided that the above
    8  * copyright notice and this permission notice appear in all copies.
    9  *
   10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   17  */
   19 /*
   20  * Known registers of the Atheros AR5001 Wireless LAN chipsets
   21  * (AR5212/AR5311).
   22  */
   24 #ifndef _AR5K_AR5212_REG_H
   25 #define _AR5K_AR5212_REG_H
   27 /*
   28  * Command register
   29  */
   30 #define AR5K_AR5212_CR          0x0008
   31 #define AR5K_AR5212_CR_RXE      0x00000004
   32 #define AR5K_AR5212_CR_RXD      0x00000020
   33 #define AR5K_AR5212_CR_SWI      0x00000040
   35 /*
   36  * Receive queue descriptor pointer register
   37  */
   38 #define AR5K_AR5212_RXDP        0x000c
   40 /*
   41  * Configuration and status register
   42  */
   43 #define AR5K_AR5212_CFG                 0x0014
   44 #define AR5K_AR5212_CFG_SWTD            0x00000001
   45 #define AR5K_AR5212_CFG_SWTB            0x00000002
   46 #define AR5K_AR5212_CFG_SWRD            0x00000004
   47 #define AR5K_AR5212_CFG_SWRB            0x00000008
   48 #define AR5K_AR5212_CFG_SWRG            0x00000010
   49 #define AR5K_AR5212_CFG_ADHOC           0x00000020
   50 #define AR5K_AR5212_CFG_PHY_OK          0x00000100
   51 #define AR5K_AR5212_CFG_EEBS            0x00000200
   52 #define AR5K_AR5212_CFG_CLKGD           0x00000400
   53 #define AR5K_AR5212_CFG_PCI_THRES       0x00060000
   54 #define AR5K_AR5212_CFG_PCI_THRES_S     17
   56 /*
   57  * Interrupt enable register
   58  */
   59 #define AR5K_AR5212_IER         0x0024
   60 #define AR5K_AR5212_IER_DISABLE 0x00000000
   61 #define AR5K_AR5212_IER_ENABLE  0x00000001
   63 /*
   64  * Transmit configuration register
   65  */
   66 #define AR5K_AR5212_TXCFG               0x0030
   67 #define AR5K_AR5212_TXCFG_SDMAMR        0x00000007
   68 #define AR5K_AR5212_TXCFG_SDMAMR_S      0
   69 #define AR5K_AR5212_TXCFG_B_MODE        0x00000008
   70 #define AR5K_AR5212_TXCFG_TXFULL        0x000003f0
   71 #define AR5K_AR5212_TXCFG_TXFULL_S      4
   72 #define AR5K_AR5212_TXCFG_TXFULL_0B     0x00000000
   73 #define AR5K_AR5212_TXCFG_TXFULL_64B    0x00000010
   74 #define AR5K_AR5212_TXCFG_TXFULL_128B   0x00000020
   75 #define AR5K_AR5212_TXCFG_TXFULL_192B   0x00000030
   76 #define AR5K_AR5212_TXCFG_TXFULL_256B   0x00000040
   77 #define AR5K_AR5212_TXCFG_TXCONT_ENABLE 0x00000080
   78 #define AR5K_AR5212_TXCFG_DMASIZE       0x00000100
   79 #define AR5K_AR5212_TXCFG_JUMBO_TXE     0x00000400
   80 #define AR5K_AR5212_TXCFG_RTSRND        0x00001000
   81 #define AR5K_AR5212_TXCFG_FRMPAD_DIS    0x00002000
   82 #define AR5K_AR5212_TXCFG_RDY_DIS       0x00004000
   84 /*
   85  * Receive configuration register
   86  */
   87 #define AR5K_AR5212_RXCFG                       0x0034
   88 #define AR5K_AR5212_RXCFG_SDMAMW                0x00000007
   89 #define AR5K_AR5212_RXCFG_SDMAMW_S              0
   90 #define AR5K_AR5311_RXCFG_DEFAULT_ANTENNA       0x00000008
   91 #define AR5K_AR5212_RXCFG_ZLFDMA                0x00000010
   92 #define AR5K_AR5212_RXCFG_JUMBO_RXE             0x00000020
   93 #define AR5K_AR5212_RXCFG_JUMBO_WRAP            0x00000040
   95 /*
   96  * MIB control register
   97  */
   98 #define AR5K_AR5212_MIBC                0x0040
   99 #define AR5K_AR5212_MIBC_COW            0x00000001
  100 #define AR5K_AR5212_MIBC_FMC            0x00000002
  101 #define AR5K_AR5212_MIBC_CMC            0x00000004
  102 #define AR5K_AR5212_MIBC_MCS            0x00000008
  104 /*
  105  * Timeout prescale register
  106  */
  107 #define AR5K_AR5212_TOPS                0x0044
  108 #define AR5K_AR5212_TOPS_M              0x0000ffff
  110 /*
  111  * Receive timeout register (no frame received)
  112  */
  113 #define AR5K_AR5212_RXNOFRM             0x0048
  114 #define AR5K_AR5212_RXNOFRM_M           0x000003ff
  116 /*
  117  * Transmit timeout register (no frame sent)
  118  */
  119 #define AR5K_AR5212_TXNOFRM             0x004c
  120 #define AR5K_AR5212_TXNOFRM_M           0x000003ff
  121 #define AR5K_AR5212_TXNOFRM_QCU         0x000ffc00
  123 /*
  124  * Receive frame gap timeout register
  125  */
  126 #define AR5K_AR5212_RPGTO               0x0050
  127 #define AR5K_AR5212_RPGTO_M             0x000003ff
  129 /*
  130  * Receive frame count limit register
  131  */
  132 #define AR5K_AR5212_RFCNT               0x0054
  133 #define AR5K_AR5212_RFCNT_M             0x0000001f
  135 /*
  136  * Misc settings register
  137  */
  138 #define AR5K_AR5212_MISC                0x0058
  139 #define AR5K_AR5212_MISC_DMA_OBS_M      0x000001e0
  140 #define AR5K_AR5212_MISC_DMA_OBS_S      5
  141 #define AR5K_AR5212_MISC_MISC_OBS_M     0x00000e00
  142 #define AR5K_AR5212_MISC_MISC_OBS_S     9
  143 #define AR5K_AR5212_MISC_MAC_OBS_LSB_M  0x00007000
  144 #define AR5K_AR5212_MISC_MAC_OBS_LSB_S  12
  145 #define AR5K_AR5212_MISC_MAC_OBS_MSB_M  0x00038000
  146 #define AR5K_AR5212_MISC_MAC_OBS_MSB_S  15
  148 /*
  149  * Primary interrupt status register
  150  */
  151 #define AR5K_AR5212_PISR                0x0080
  152 #define AR5K_AR5212_PISR_RXOK           0x00000001
  153 #define AR5K_AR5212_PISR_RXDESC         0x00000002
  154 #define AR5K_AR5212_PISR_RXERR          0x00000004
  155 #define AR5K_AR5212_PISR_RXNOFRM        0x00000008
  156 #define AR5K_AR5212_PISR_RXEOL          0x00000010
  157 #define AR5K_AR5212_PISR_RXORN          0x00000020
  158 #define AR5K_AR5212_PISR_TXOK           0x00000040
  159 #define AR5K_AR5212_PISR_TXDESC         0x00000080
  160 #define AR5K_AR5212_PISR_TXERR          0x00000100
  161 #define AR5K_AR5212_PISR_TXNOFRM        0x00000200
  162 #define AR5K_AR5212_PISR_TXEOL          0x00000400
  163 #define AR5K_AR5212_PISR_TXURN          0x00000800
  164 #define AR5K_AR5212_PISR_MIB            0x00001000
  165 #define AR5K_AR5212_PISR_SWI            0x00002000
  166 #define AR5K_AR5212_PISR_RXPHY          0x00004000
  167 #define AR5K_AR5212_PISR_RXKCM          0x00008000
  168 #define AR5K_AR5212_PISR_SWBA           0x00010000
  169 #define AR5K_AR5212_PISR_BRSSI          0x00020000
  170 #define AR5K_AR5212_PISR_BMISS          0x00040000
  171 #define AR5K_AR5212_PISR_HIUERR         0x00080000
  172 #define AR5K_AR5212_PISR_BNR            0x00100000
  173 #define AR5K_AR5212_PISR_RXCHIRP        0x00200000
  174 #define AR5K_AR5212_PISR_TIM            0x00800000
  175 #define AR5K_AR5212_PISR_BCNMISC        0x00800000
  176 #define AR5K_AR5212_PISR_GPIO           0x01000000
  177 #define AR5K_AR5212_PISR_QCBRORN        0x02000000
  178 #define AR5K_AR5212_PISR_QCBRURN        0x04000000
  179 #define AR5K_AR5212_PISR_QTRIG          0x08000000
  181 /*
  182  * Secondary interrupt status registers (0 - 4)
  183  */
  184 #define AR5K_AR5212_SISR0               0x0084
  185 #define AR5K_AR5212_SISR0_QCU_TXOK      0x000003ff
  186 #define AR5K_AR5212_SISR0_QCU_TXDESC    0x03ff0000
  188 #define AR5K_AR5212_SISR1               0x0088
  189 #define AR5K_AR5212_SISR1_QCU_TXERR     0x000003ff
  190 #define AR5K_AR5212_SISR1_QCU_TXEOL     0x03ff0000
  192 #define AR5K_AR5212_SISR2               0x008c
  193 #define AR5K_AR5212_SISR2_QCU_TXURN     0x000003ff
  194 #define AR5K_AR5212_SISR2_MCABT         0x00100000
  195 #define AR5K_AR5212_SISR2_SSERR         0x00200000
  196 #define AR5K_AR5212_SISR2_DPERR         0x00400000
  197 #define AR5K_AR5212_SISR2_TIM           0x01000000
  198 #define AR5K_AR5212_SISR2_CAB_END       0x02000000
  199 #define AR5K_AR5212_SISR2_DTIM_SYNC     0x04000000
  200 #define AR5K_AR5212_SISR2_BCN_TIMEOUT   0x08000000
  201 #define AR5K_AR5212_SISR2_CAB_TIMEOUT   0x10000000
  202 #define AR5K_AR5212_SISR2_DTIM          0x20000000
  204 #define AR5K_AR5212_SISR3               0x0090
  205 #define AR5K_AR5212_SISR3_QCBRORN       0x000003ff
  206 #define AR5K_AR5212_SISR3_QCBRURN       0x03ff0000
  208 #define AR5K_AR5212_SISR4               0x0094
  209 #define AR5K_AR5212_SISR4_QTRIG         0x000003ff
  211 /*
  212  * Shadow read-and-clear interrupt status registers
  213  */
  214 #define AR5K_AR5212_RAC_PISR    0x00c0
  215 #define AR5K_AR5212_RAC_SISR0   0x00c4
  216 #define AR5K_AR5212_RAC_SISR1   0x00c8
  217 #define AR5K_AR5212_RAC_SISR2   0x00cc
  218 #define AR5K_AR5212_RAC_SISR3   0c00d0
  219 #define AR5K_AR5212_RAC_SISR4   0c00d4
  221 /*
  222  * Primary interrupt mask register
  223  */
  224 #define AR5K_AR5212_PIMR                0x00a0
  225 #define AR5K_AR5212_PIMR_RXOK           0x00000001
  226 #define AR5K_AR5212_PIMR_RXDESC         0x00000002
  227 #define AR5K_AR5212_PIMR_RXERR          0x00000004
  228 #define AR5K_AR5212_PIMR_RXNOFRM        0x00000008
  229 #define AR5K_AR5212_PIMR_RXEOL          0x00000010
  230 #define AR5K_AR5212_PIMR_RXORN          0x00000020
  231 #define AR5K_AR5212_PIMR_TXOK           0x00000040
  232 #define AR5K_AR5212_PIMR_TXDESC         0x00000080
  233 #define AR5K_AR5212_PIMR_TXERR          0x00000100
  234 #define AR5K_AR5212_PIMR_TXNOFRM        0x00000200
  235 #define AR5K_AR5212_PIMR_TXEOL          0x00000400
  236 #define AR5K_AR5212_PIMR_TXURN          0x00000800
  237 #define AR5K_AR5212_PIMR_MIB            0x00001000
  238 #define AR5K_AR5212_PIMR_SWI            0x00002000
  239 #define AR5K_AR5212_PIMR_RXPHY          0x00004000
  240 #define AR5K_AR5212_PIMR_RXKCM          0x00008000
  241 #define AR5K_AR5212_PIMR_SWBA           0x00010000
  242 #define AR5K_AR5212_PIMR_BRSSI          0x00020000
  243 #define AR5K_AR5212_PIMR_BMISS          0x00040000
  244 #define AR5K_AR5212_PIMR_HIUERR         0x00080000
  245 #define AR5K_AR5212_PIMR_BNR            0x00100000
  246 #define AR5K_AR5212_PIMR_RXCHIRP        0x00200000
  247 #define AR5K_AR5212_PIMR_TIM            0x00800000
  248 #define AR5K_AR5212_PIMR_BCNMISC        0x00800000
  249 #define AR5K_AR5212_PIMR_GPIO           0x01000000
  250 #define AR5K_AR5212_PIMR_QCBRORN        0x02000000
  251 #define AR5K_AR5212_PIMR_QCBRURN        0x04000000
  252 #define AR5K_AR5212_PIMR_QTRIG          0x08000000
  254 /*
  255  * Secondary interrupt mask registers (0 - 4)
  256  */
  257 #define AR5K_AR5212_SIMR0               0x00a4
  258 #define AR5K_AR5212_SIMR0_QCU_TXOK      0x000003ff
  259 #define AR5K_AR5212_SIMR0_QCU_TXOK_S    0
  260 #define AR5K_AR5212_SIMR0_QCU_TXDESC    0x03ff0000
  261 #define AR5K_AR5212_SIMR0_QCU_TXDESC_S  16
  263 #define AR5K_AR5212_SIMR1               0x00a8
  264 #define AR5K_AR5212_SIMR1_QCU_TXERR     0x000003ff
  265 #define AR5K_AR5212_SIMR1_QCU_TXERR_S   0
  266 #define AR5K_AR5212_SIMR1_QCU_TXEOL     0x03ff0000
  267 #define AR5K_AR5212_SIMR1_QCU_TXEOL_S   16
  269 #define AR5K_AR5212_SIMR2               0x00ac
  270 #define AR5K_AR5212_SIMR2_QCU_TXURN     0x000003ff
  271 #define AR5K_AR5212_SIMR2_QCU_TXURN_S   0
  272 #define AR5K_AR5212_SIMR2_MCABT         0x00100000
  273 #define AR5K_AR5212_SIMR2_SSERR         0x00200000
  274 #define AR5K_AR5212_SIMR2_DPERR         0x00400000
  275 #define AR5K_AR5212_SIMR2_TIM           0x01000000
  276 #define AR5K_AR5212_SIMR2_CAB_END       0x02000000
  277 #define AR5K_AR5212_SIMR2_DTIM_SYNC     0x04000000
  278 #define AR5K_AR5212_SIMR2_BCN_TIMEOUT   0x08000000
  279 #define AR5K_AR5212_SIMR2_CAB_TIMEOUT   0x10000000
  280 #define AR5K_AR5212_SIMR2_DTIM          0x20000000
  282 #define AR5K_AR5212_SIMR3               0x00b0
  283 #define AR5K_AR5212_SIMR3_QCBRORN       0x000003ff
  284 #define AR5K_AR5212_SIMR3_QCBRORN_S     0
  285 #define AR5K_AR5212_SIMR3_QCBRURN       0x03ff0000
  286 #define AR5K_AR5212_SIMR3_QCBRURN_S     16
  288 #define AR5K_AR5212_SIMR4               0x00b4
  289 #define AR5K_AR5212_SIMR4_QTRIG         0x000003ff
  290 #define AR5K_AR5212_SIMR4_QTRIG_S       0
  292 /*
  293  * Decompression mask registers
  294  */
  295 #define AR5K_AR5212_DCM_ADDR    0x0400
  296 #define AR5K_AR5212_DCM_DATA    0x0404
  298 /*
  299  * Decompression configuration registers
  300  */
  301 #define AR5K_AR5212_DCCFG       0x0420
  303 /*
  304  * Compression configuration registers
  305  */
  306 #define AR5K_AR5212_CCFG        0x0600
  307 #define AR5K_AR5212_CCFG_CUP    0x0604
  309 /*
  310  * Compression performance counter registers
  311  */
  312 #define AR5K_AR5212_CPC0        0x0610
  313 #define AR5K_AR5212_CPC1        0x0614
  314 #define AR5K_AR5212_CPC2        0x0618
  315 #define AR5K_AR5212_CPC3        0x061c
  316 #define AR5K_AR5212_CPCORN      0x0620
  318 /*
  319  * Queue control unit (QCU) registers (0 - 9)
  320  */
  321 #define AR5K_AR5212_QCU(_n, _a)         (((_n) << 2) + _a)
  323 /*
  324  * QCU Transmit descriptor pointer registers
  325  */
  326 #define AR5K_AR5212_QCU_TXDP(_n)        AR5K_AR5212_QCU(_n, 0x0800)
  328 /*
  329  * QCU Transmit enable register
  330  */
  331 #define AR5K_AR5212_QCU_TXE             0x0840
  333 /*
  334  * QCU Transmit disable register
  335  */
  336 #define AR5K_AR5212_QCU_TXD             0x0880
  338 /*
  339  * QCU CBR configuration registers
  340  */
  341 #define AR5K_AR5212_QCU_CBRCFG(_n)              AR5K_AR5212_QCU(_n, 0x08c0)
  342 #define AR5K_AR5212_QCU_CBRCFG_INTVAL           0x00ffffff
  343 #define AR5K_AR5212_QCU_CBRCFG_INTVAL_S         0
  344 #define AR5K_AR5212_QCU_CBRCFG_ORN_THRES        0xff000000
  345 #define AR5K_AR5212_QCU_CBRCFG_ORN_THRES_S      24
  347 /*
  348  * QCU Ready time configuration registers
  349  */
  350 #define AR5K_AR5212_QCU_RDYTIMECFG(_n)          AR5K_AR5212_QCU(_n, 0x0900)
  351 #define AR5K_AR5212_QCU_RDYTIMECFG_INTVAL       0x00ffffff
  352 #define AR5K_AR5212_QCU_RDYTIMECFG_INTVAL_S     0
  353 #define AR5K_AR5212_QCU_RDYTIMECFG_DURATION     0x00ffffff
  354 #define AR5K_AR5212_QCU_RDYTIMECFG_ENABLE       0x01000000
  356 /*
  357  * QCU one shot arm set registers
  358  */
  359 #define AR5K_AR5212_QCU_ONESHOTARMS(_n) AR5K_AR5212_QCU(_n, 0x0940)
  360 #define AR5K_AR5212_QCU_ONESHOTARMS_M   0x0000ffff
  362 /*
  363  * QCU one shot arm clear registers
  364  */
  365 #define AR5K_AR5212_QCU_ONESHOTARMC(_n) AR5K_AR5212_QCU(_n, 0x0980)
  366 #define AR5K_AR5212_QCU_ONESHOTARMC_M   0x0000ffff
  368 /*
  369  * QCU misc registers
  370  */
  371 #define AR5K_AR5212_QCU_MISC(_n)                AR5K_AR5212_QCU(_n, 0x09c0)
  372 #define AR5K_AR5212_QCU_MISC_FRSHED_M           0x0000000f
  373 #define AR5K_AR5212_QCU_MISC_FRSHED_ASAP        0
  374 #define AR5K_AR5212_QCU_MISC_FRSHED_CBR         1
  375 #define AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT      2
  376 #define AR5K_AR5212_QCU_MISC_FRSHED_TIM_GT      3
  377 #define AR5K_AR5212_QCU_MISC_FRSHED_BCN_SENT_GT 4
  378 #define AR5K_AR5212_QCU_MISC_ONESHOT_ENABLE     0x00000010
  379 #define AR5K_AR5212_QCU_MISC_CBREXP             0x00000020
  380 #define AR5K_AR5212_QCU_MISC_CBREXP_BCN         0x00000040
  381 #define AR5K_AR5212_QCU_MISC_BCN_ENABLE         0x00000080
  382 #define AR5K_AR5212_QCU_MISC_CBR_THRES_ENABLE   0x00000100
  383 #define AR5K_AR5212_QCU_MISC_TXE                0x00000200
  384 #define AR5K_AR5212_QCU_MISC_CBR                0x00000400
  385 #define AR5K_AR5212_QCU_MISC_DCU_EARLY          0x00000800
  387 /*
  388  * QCU status registers
  389  */
  390 #define AR5K_AR5212_QCU_STS(_n)         AR5K_AR5212_QCU(_n, 0x0a00)
  391 #define AR5K_AR5212_QCU_STS_FRMPENDCNT  0x00000003
  392 #define AR5K_AR5212_QCU_STS_CBREXPCNT   0x0000ff00
  394 /*
  395  * QCU ready time shutdown register
  396  */
  397 #define AR5K_AR5212_QCU_RDYTIMESHDN     0x0a40
  398 #define AR5K_AR5212_QCU_RDYTIMESHDN_M   0x000003ff
  400 /*
  401  * QCU compression buffer base registers
  402  */
  403 #define AR5K_AR5212_QCU_CBB_SELECT      0x0b00
  404 #define AR5K_AR5212_QCU_CBB_ADDR        0x0b04
  406 /*
  407  * QCU compression buffer configuration register
  408  */
  409 #define AR5K_AR5212_QCU_CBCFG   0x0b08
  411 /*
  412  * DCF control unit (DCU) registers (0 - 9)
  413  */
  414 #define AR5K_AR5212_DCU(_n, _a)         AR5K_AR5212_QCU(_n, _a)
  416 /*
  417  * DCU QCU mask registers
  418  */
  419 #define AR5K_AR5212_DCU_QCUMASK(_n)     AR5K_AR5212_DCU(_n, 0x1000)
  420 #define AR5K_AR5212_DCU_QCUMASK_M       0x000003ff
  422 /*
  423  * DCU local IFS settings register
  424  */
  425 #define AR5K_AR5212_DCU_LCL_IFS(_n)             AR5K_AR5212_DCU(_n, 0x1040)
  426 #define AR5K_AR5212_DCU_LCL_IFS_CW_MIN          0x000003ff
  427 #define AR5K_AR5212_DCU_LCL_IFS_CW_MIN_S        0
  428 #define AR5K_AR5212_DCU_LCL_IFS_CW_MAX          0x000ffc00
  429 #define AR5K_AR5212_DCU_LCL_IFS_CW_MAX_S        10
  430 #define AR5K_AR5212_DCU_LCL_IFS_AIFS            0x0ff00000
  431 #define AR5K_AR5212_DCU_LCL_IFS_AIFS_S          20
  433 /*
  434  * DCU retry limit registers
  435  */
  436 #define AR5K_AR5212_DCU_RETRY_LMT(_n)           AR5K_AR5212_DCU(_n, 0x1080)
  437 #define AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY      0x0000000f
  438 #define AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY_S    0
  439 #define AR5K_AR5212_DCU_RETRY_LMT_LG_RETRY      0x000000f0
  440 #define AR5K_AR5212_DCU_RETRY_LMT_LG_RETRY_S    4
  441 #define AR5K_AR5212_DCU_RETRY_LMT_SSH_RETRY     0x00003f00
  442 #define AR5K_AR5212_DCU_RETRY_LMT_SSH_RETRY_S   8
  443 #define AR5K_AR5212_DCU_RETRY_LMT_SLG_RETRY     0x000fc000
  444 #define AR5K_AR5212_DCU_RETRY_LMT_SLG_RETRY_S   14
  446 /*
  447  * DCU channel time registers
  448  */
  449 #define AR5K_AR5212_DCU_CHAN_TIME(_n)           AR5K_AR5212_DCU(_n, 0x10c0)
  450 #define AR5K_AR5212_DCU_CHAN_TIME_DUR           0x000fffff
  451 #define AR5K_AR5212_DCU_CHAN_TIME_DUR_S         0
  452 #define AR5K_AR5212_DCU_CHAN_TIME_ENABLE        0x00100000
  454 /*
  455  * DCU misc registers
  456  */
  457 #define AR5K_AR5212_DCU_MISC(_n)                AR5K_AR5212_DCU(_n, 0x1100)
  458 #define AR5K_AR5212_DCU_MISC_BACKOFF            0x000007ff
  459 #define AR5K_AR5212_DCU_MISC_BACKOFF_FRAG       0x00000200
  460 #define AR5K_AR5212_DCU_MISC_HCFPOLL_ENABLE     0x00000800
  461 #define AR5K_AR5212_DCU_MISC_BACKOFF_PERSIST    0x00001000
  462 #define AR5K_AR5212_DCU_MISC_FRMPRFTCH_ENABLE   0x00002000
  463 #define AR5K_AR5212_DCU_MISC_VIRTCOL            0x0000c000
  464 #define AR5K_AR5212_DCU_MISC_VIRTCOL_NORMAL     0
  465 #define AR5K_AR5212_DCU_MISC_VIRTCOL_MODIFIED   1
  466 #define AR5K_AR5212_DCU_MISC_VIRTCOL_IGNORE     2
  467 #define AR5K_AR5212_DCU_MISC_BCN_ENABLE         0x00010000
  468 #define AR5K_AR5212_DCU_MISC_ARBLOCK_CTL        0x00060000
  469 #define AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_S      17
  470 #define AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_NONE   0
  471 #define AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_INTFRM 1
  472 #define AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL 2
  473 #define AR5K_AR5212_DCU_MISC_ARBLOCK_IGNORE     0x00080000
  474 #define AR5K_AR5212_DCU_MISC_SEQ_NUM_INCR_DIS   0x00100000
  475 #define AR5K_AR5212_DCU_MISC_POST_FR_BKOFF_DIS  0x00200000
  476 #define AR5K_AR5212_DCU_MISC_VIRT_COLL_POLICY   0x00400000
  477 #define AR5K_AR5212_DCU_MISC_BLOWN_IFS_POLICY   0x00800000
  478 #define AR5K_AR5212_DCU_MISC_SEQNUM_CTL         0x01000000
  480 /*
  481  * DCU frame sequence number registers
  482  */
  483 #define AR5K_AR5212_DCU_SEQNUM(_n)      AR5K_AR5212_DCU(_n, 0x1140)
  484 #define AR5K_AR5212_DCU_SEQNUM_M        0x00000fff
  485 /*
  486  * DCU global IFS SIFS registers
  487  */
  488 #define AR5K_AR5212_DCU_GBL_IFS_SIFS    0x1030
  489 #define AR5K_AR5212_DCU_GBL_IFS_SIFS_M  0x0000ffff
  491 /*
  492  * DCU global IFS slot interval registers
  493  */
  494 #define AR5K_AR5212_DCU_GBL_IFS_SLOT    0x1070
  495 #define AR5K_AR5212_DCU_GBL_IFS_SLOT_M  0x0000ffff
  497 /*
  498  * DCU global IFS EIFS registers
  499  */
  500 #define AR5K_AR5212_DCU_GBL_IFS_EIFS    0x10b0
  501 #define AR5K_AR5212_DCU_GBL_IFS_EIFS_M  0x0000ffff
  503 /*
  504  * DCU global IFS misc registers
  505  */
  506 #define AR5K_AR5212_DCU_GBL_IFS_MISC                    0x10f0
  507 #define AR5K_AR5212_DCU_GBL_IFS_MISC_LFSR_SLICE         0x00000007
  508 #define AR5K_AR5212_DCU_GBL_IFS_MISC_TURBO_MODE         0x00000008
  509 #define AR5K_AR5212_DCU_GBL_IFS_MISC_SIFS_DUR_USEC      0x000003f0
  510 #define AR5K_AR5212_DCU_GBL_IFS_MISC_USEC_DUR           0x000ffc00
  511 #define AR5K_AR5212_DCU_GBL_IFS_MISC_DCU_ARB_DELAY      0x00300000
  513 /*
  514  * DCU frame prefetch control register
  515  */
  516 #define AR5K_AR5212_DCU_FP              0x1230
  518 /*
  519  * DCU transmit pause control/status register
  520  */
  521 #define AR5K_AR5212_DCU_TXP             0x1270
  522 #define AR5K_AR5212_DCU_TXP_M           0x000003ff
  523 #define AR5K_AR5212_DCU_TXP_STATUS      0x00010000
  525 /*
  526  * DCU transmit filter register
  527  */
  528 #define AR5K_AR5212_DCU_TX_FILTER       0x1038
  530 /*
  531  * DCU clear transmit filter register
  532  */
  533 #define AR5K_AR5212_DCU_TX_FILTER_CLR   0x143c
  535 /*
  536  * DCU set transmit filter register
  537  */
  538 #define AR5K_AR5212_DCU_TX_FILTER_SET   0x147c
  540 /*
  541  * DMA size definitions
  542  */
  543 typedef enum {
  544         AR5K_AR5212_DMASIZE_4B = 0,
  545         AR5K_AR5212_DMASIZE_8B = 1,
  546         AR5K_AR5212_DMASIZE_16B = 2,
  547         AR5K_AR5212_DMASIZE_32B = 3,
  548         AR5K_AR5212_DMASIZE_64B = 4,
  549         AR5K_AR5212_DMASIZE_128B = 5,
  550         AR5K_AR5212_DMASIZE_256B = 6,
AR5K_AR5212_DMASIZE_512B = 7
  552 } ar5k_ar5212_dmasize_t;
  554 /*
  555  * Reset control register
  556  */
  557 #define AR5K_AR5212_RC                  0x4000
  558 #define AR5K_AR5212_RC_PCU              0x00000001
  559 #define AR5K_AR5212_RC_BB               0x00000002
  560 #define AR5K_AR5212_RC_PCI              0x00000010
  561 #define AR5K_AR5212_RC_CHIP             (                               \
AR5K_AR5212_RC_PCU | AR5K_AR5212_RC_BB | AR5K_AR5212_RC_PCI     \
  563 )
  565 /*
  566  * Sleep control register
  567  */
  568 #define AR5K_AR5212_SCR                 0x4004
  569 #define AR5K_AR5212_SCR_SLDUR           0x0000ffff
  570 #define AR5K_AR5212_SCR_SLE             0x00030000
  571 #define AR5K_AR5212_SCR_SLE_S           16
  572 #define AR5K_AR5212_SCR_SLE_WAKE        0x00000000
  573 #define AR5K_AR5212_SCR_SLE_SLP         0x00010000
  574 #define AR5K_AR5212_SCR_SLE_ALLOW       0x00020000
  575 #define AR5K_AR5212_SCR_SLE_UNITS       0x00000008
  577 /*
  578  * Interrupt pending register
  579  */
  580 #define AR5K_AR5212_INTPEND     0x4008
  581 #define AR5K_AR5212_INTPEND_M   0x00000001
  583 /*
  584  * Sleep force register
  585  */
  586 #define AR5K_AR5212_SFR         0x400c
  587 #define AR5K_AR5212_SFR_M       0x00000001
  589 /*
  590  * PCI configuration register
  591  */
  592 #define AR5K_AR5212_PCICFG              0x4010
  593 #define AR5K_AR5212_PCICFG_CLKRUNEN     0x00000004
  594 #define AR5K_AR5212_PCICFG_EESIZE       0x00000018
  595 #define AR5K_AR5212_PCICFG_EESIZE_S     3
  596 #define AR5K_AR5212_PCICFG_EESIZE_4K    0
  597 #define AR5K_AR5212_PCICFG_EESIZE_8K    1
  598 #define AR5K_AR5212_PCICFG_EESIZE_16K   2
  599 #define AR5K_AR5212_PCICFG_EESIZE_FAIL  3
  600 #define AR5K_AR5212_PCICFG_LED          0x00000060
  601 #define AR5K_AR5212_PCICFG_LED_NONE     0x00000000
  602 #define AR5K_AR5212_PCICFG_LED_PEND     0x00000020
  603 #define AR5K_AR5212_PCICFG_LED_ASSOC    0x00000040
  604 #define AR5K_AR5212_PCICFG_BUS_SEL      0x00000380
  605 #define AR5K_AR5212_PCICFG_CBEFIX_DIS   0x00000400
  606 #define AR5K_AR5212_PCICFG_SL_INTEN     0x00000800
  607 #define AR5K_AR5212_PCICFG_SL_INPEN     0x00002800
  608 #define AR5K_AR5212_PCICFG_SPWR_DN      0x00010000
  609 #define AR5K_AR5212_PCICFG_LEDMODE      0x000e0000
  610 #define AR5K_AR5212_PCICFG_LEDMODE_PROP 0x00000000
  611 #define AR5K_AR5212_PCICFG_LEDMODE_PROM 0x00020000
  612 #define AR5K_AR5212_PCICFG_LEDMODE_PWR  0x00040000
  613 #define AR5K_AR5212_PCICFG_LEDMODE_RAND 0x00060000
  614 #define AR5K_AR5212_PCICFG_LEDBLINK     0x00700000
  615 #define AR5K_AR5212_PCICFG_LEDBLINK_S   20
  616 #define AR5K_AR5212_PCICFG_LEDSLOW      0x00800000
  617 #define AR5K_AR5212_PCICFG_LEDSTATE                                     \
  618         (AR5K_AR5212_PCICFG_LED | AR5K_AR5212_PCICFG_LEDMODE |          \
AR5K_AR5212_PCICFG_LEDBLINK | AR5K_AR5212_PCICFG_LEDSLOW)
  621 /*
  622  * "General Purpose Input/Output" (GPIO) control register
  623  */
  624 #define AR5K_AR5212_GPIOCR              0x4014
  625 #define AR5K_AR5212_GPIOCR_INT_ENA      0x00008000
  626 #define AR5K_AR5212_GPIOCR_INT_SELL     0x00000000
  627 #define AR5K_AR5212_GPIOCR_INT_SELH     0x00010000
  628 #define AR5K_AR5212_GPIOCR_NONE(n)      (0 << ((n) * 2))
  629 #define AR5K_AR5212_GPIOCR_OUT0(n)      (1 << ((n) * 2))
  630 #define AR5K_AR5212_GPIOCR_OUT1(n)      (2 << ((n) * 2))
  631 #define AR5K_AR5212_GPIOCR_ALL(n)       (3 << ((n) * 2))
  632 #define AR5K_AR5212_GPIOCR_INT_SEL(n)   ((n) << 12)
  634 #define AR5K_AR5212_NUM_GPIO    6
  636 /*
  637  * "General Purpose Input/Output" (GPIO) data output register
  638  */
  639 #define AR5K_AR5212_GPIODO      0x4018
  641 /*
  642  * "General Purpose Input/Output" (GPIO) data input register
  643  */
  644 #define AR5K_AR5212_GPIODI      0x401c
  645 #define AR5K_AR5212_GPIODI_M    0x0000002f
  647 /*
  648  * Silicon revision register
  649  */
  650 #define AR5K_AR5212_SREV                0x4020
  651 #define AR5K_AR5212_SREV_REV            0x0000000f
  652 #define AR5K_AR5212_SREV_REV_S          0
  653 #define AR5K_AR5212_SREV_VER            0x000000ff
  654 #define AR5K_AR5212_SREV_VER_S          4
  656 /*
  657  * EEPROM access registers
  658  */
  659 #define AR5K_AR5212_EEPROM_BASE         0x6000
  660 #define AR5K_AR5212_EEPROM_DATA         0x6004
  661 #define AR5K_AR5212_EEPROM_CMD          0x6008
  662 #define AR5K_AR5212_EEPROM_CMD_READ     0x00000001
  663 #define AR5K_AR5212_EEPROM_CMD_WRITE    0x00000002
  664 #define AR5K_AR5212_EEPROM_CMD_RESET    0x00000004
  665 #define AR5K_AR5212_EEPROM_STATUS       0x600c
  666 #define AR5K_AR5212_EEPROM_STAT_RDERR   0x00000001
  667 #define AR5K_AR5212_EEPROM_STAT_RDDONE  0x00000002
  668 #define AR5K_AR5212_EEPROM_STAT_WRERR   0x00000004
  669 #define AR5K_AR5212_EEPROM_STAT_WRDONE  0x00000008
  670 #define AR5K_AR5212_EEPROM_CFG          0x6010
  672 /*
  673  * PCU registers
  674  */
  676 #define AR5K_AR5212_PCU_MIN     0x8000
  677 #define AR5K_AR5212_PCU_MAX     0x8fff
  679 /*
  680  * First station id register (MAC address in lower 32 bits)
  681  */
  682 #define AR5K_AR5212_STA_ID0     0x8000
  684 /*
  685  * Second station id register (MAC address in upper 16 bits)
  686  */
  687 #define AR5K_AR5212_STA_ID1                     0x8004
  688 #define AR5K_AR5212_STA_ID1_AP                  0x00010000
  689 #define AR5K_AR5212_STA_ID1_ADHOC               0x00020000
  690 #define AR5K_AR5212_STA_ID1_PWR_SV              0x00040000
  691 #define AR5K_AR5212_STA_ID1_NO_KEYSRCH          0x00080000
  692 #define AR5K_AR5212_STA_ID1_PCF                 0x00100000
  693 #define AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA     0x00200000
  694 #define AR5K_AR5212_STA_ID1_DESC_ANTENNA        0x00400000
  695 #define AR5K_AR5212_STA_ID1_RTS_DEFAULT_ANTENNA 0x00800000
  696 #define AR5K_AR5212_STA_ID1_ACKCTS_6MB          0x01000000
  697 #define AR5K_AR5212_STA_ID1_BASE_RATE_11B       0x02000000
  699 /*
  700  * First BSSID register (MAC address, lower 32bits)
  701  */
  702 #define AR5K_AR5212_BSS_ID0     0x8008
  704 /*
  705  * Second BSSID register (MAC address in upper 16 bits)
  706  *
  707  * AID: Association ID
  708  */
  709 #define AR5K_AR5212_BSS_ID1             0x800c
  710 #define AR5K_AR5212_BSS_ID1_AID         0xffff0000
  711 #define AR5K_AR5212_BSS_ID1_AID_S       16
  713 /*
  714  * Backoff slot time register
  715  */
  716 #define AR5K_AR5212_SLOT_TIME   0x8010
  718 /*
  719  * ACK/CTS timeout register
  720  */
  721 #define AR5K_AR5212_TIME_OUT            0x8014
  722 #define AR5K_AR5212_TIME_OUT_ACK        0x00001fff
  723 #define AR5K_AR5212_TIME_OUT_ACK_S      0
  724 #define AR5K_AR5212_TIME_OUT_CTS        0x1fff0000
  725 #define AR5K_AR5212_TIME_OUT_CTS_S      16
  727 /*
  728  * RSSI threshold register
  729  */
  730 #define AR5K_AR5212_RSSI_THR            0x8018
  731 #define AR5K_AR5212_RSSI_THR_M          0x000000ff
  732 #define AR5K_AR5212_RSSI_THR_BMISS      0x0000ff00
  733 #define AR5K_AR5212_RSSI_THR_BMISS_S    8
  735 /*
  736  * Transmit latency register
  737  */
  738 #define AR5K_AR5212_USEC                0x801c
  739 #define AR5K_AR5212_USEC_1              0x0000007f
  740 #define AR5K_AR5212_USEC_1_S            0
  741 #define AR5K_AR5212_USEC_32             0x00003f80
  742 #define AR5K_AR5212_USEC_32_S           7
  743 #define AR5K_AR5212_USEC_TX_LATENCY     0x007fc000
  744 #define AR5K_AR5212_USEC_TX_LATENCY_S   14
  745 #define AR5K_AR5212_USEC_RX_LATENCY     0x1f800000
  746 #define AR5K_AR5212_USEC_RX_LATENCY_S   23
  747 #define AR5K_AR5311_USEC_TX_LATENCY     0x000fc000
  748 #define AR5K_AR5311_USEC_TX_LATENCY_S   14
  749 #define AR5K_AR5311_USEC_RX_LATENCY     0x03f00000
  750 #define AR5K_AR5311_USEC_RX_LATENCY_S   20
  752 /*
  753  * PCU beacon control register
  754  */
  755 #define AR5K_AR5212_BEACON              0x8020
  756 #define AR5K_AR5212_BEACON_PERIOD       0x0000ffff
  757 #define AR5K_AR5212_BEACON_PERIOD_S     0
  758 #define AR5K_AR5212_BEACON_TIM          0x007f0000
  759 #define AR5K_AR5212_BEACON_TIM_S        16
  760 #define AR5K_AR5212_BEACON_ENABLE       0x00800000
  761 #define AR5K_AR5212_BEACON_RESET_TSF    0x01000000
  763 /*
  764  * CFP period register
  765  */
  766 #define AR5K_AR5212_CFP_PERIOD          0x8024
  768 /*
  769  * Next beacon time register
  770  */
  771 #define AR5K_AR5212_TIMER0              0x8028
  773 /*
  774  * Next DMA beacon alert register
  775  */
  776 #define AR5K_AR5212_TIMER1              0x802c
  778 /*
  779  * Next software beacon alert register
  780  */
  781 #define AR5K_AR5212_TIMER2              0x8030
  783 /*
  784  * Next ATIM window time register
  785  */
  786 #define AR5K_AR5212_TIMER3              0x8034
  788 /*
  789  * CFP duration register
  790  */
  791 #define AR5K_AR5212_CFP_DUR             0x8038
  793 /*
  794  * Receive filter register
  795  */
  796 #define AR5K_AR5212_RX_FILTER           0x803c
  797 #define AR5K_AR5212_RX_FILTER_UNICAST   0x00000001
  798 #define AR5K_AR5212_RX_FILTER_MULTICAST 0x00000002
  799 #define AR5K_AR5212_RX_FILTER_BROADCAST 0x00000004
  800 #define AR5K_AR5212_RX_FILTER_CONTROL   0x00000008
  801 #define AR5K_AR5212_RX_FILTER_BEACON    0x00000010
  802 #define AR5K_AR5212_RX_FILTER_PROMISC   0x00000020
  803 #define AR5K_AR5212_RX_FILTER_XR_POLL   0x00000040
  804 #define AR5K_AR5212_RX_FILTER_PROBE_REQ 0x00000080
  806 /*
  807  * Multicast filter register (lower 32 bits)
  808  */
  809 #define AR5K_AR5212_MCAST_FIL0  0x8040
  811 /*
  812  * Multicast filter register (higher 16 bits)
  813  */
  814 #define AR5K_AR5212_MCAST_FIL1  0x8044
  816 /*
  817  * PCU control register
  818  */
  819 #define AR5K_AR5212_DIAG_SW                     0x8048
  820 #define AR5K_AR5212_DIAG_SW_DIS_WEP_ACK         0x00000001
  821 #define AR5K_AR5212_DIAG_SW_DIS_ACK             0x00000002
  822 #define AR5K_AR5212_DIAG_SW_DIS_CTS             0x00000004
  823 #define AR5K_AR5212_DIAG_SW_DIS_ENC             0x00000008
  824 #define AR5K_AR5212_DIAG_SW_DIS_DEC             0x00000010
  825 #define AR5K_AR5212_DIAG_SW_DIS_RX              0x00000020
  826 #define AR5K_AR5212_DIAG_SW_LOOP_BACK           0x00000040
  827 #define AR5K_AR5212_DIAG_SW_CORR_FCS            0x00000080
  828 #define AR5K_AR5212_DIAG_SW_CHAN_INFO           0x00000100
  829 #define AR5K_AR5212_DIAG_SW_EN_SCRAM_SEED       0x00000200
  830 #define AR5K_AR5212_DIAG_SW_ECO_ENABLE          0x00000400
  831 #define AR5K_AR5212_DIAG_SW_SCRAM_SEED_M        0x0001fc00
  832 #define AR5K_AR5212_DIAG_SW_SCRAM_SEED_S        10
  833 #define AR5K_AR5212_DIAG_SW_FRAME_NV0           0x00020000
  834 #define AR5K_AR5212_DIAG_SW_OBSPT_M             0x000c0000
  835 #define AR5K_AR5212_DIAG_SW_OBSPT_S             18
  837 /*
  838  * TSF (clock) register (lower 32 bits)
  839  */
  840 #define AR5K_AR5212_TSF_L32     0x804c
  842 /*
  843  * TSF (clock) register (higher 32 bits)
  844  */
  845 #define AR5K_AR5212_TSF_U32     0x8050
  847 /*
  848  * ADDAC test register
  849  */
  850 #define AR5K_AR5212_ADDAC_TEST  0x8054
  852 /*
  853  * Default antenna register
  854  */
  855 #define AR5K_AR5212_DEFAULT_ANTENNA     0x8058
  857 /*
  858  * Last beacon timestamp register
  859  */
  860 #define AR5K_AR5212_LAST_TSTP   0x8080
  862 /*
  863  * NAV register (current)
  864  */
  865 #define AR5K_AR5212_NAV         0x8084
  867 /*
  868  * RTS success register
  869  */
  870 #define AR5K_AR5212_RTS_OK      0x8088
  872 /*
  873  * RTS failure register
  874  */
  875 #define AR5K_AR5212_RTS_FAIL    0x808c
  877 /*
  878  * ACK failure register
  879  */
  880 #define AR5K_AR5212_ACK_FAIL    0x8090
  882 /*
  883  * FCS failure register
  884  */
  885 #define AR5K_AR5212_FCS_FAIL    0x8094
  887 /*
  888  * Beacon count register
  889  */
  890 #define AR5K_AR5212_BEACON_CNT  0x8098
  892 /*
  893  * XR (eXtended Range) mode register
  894  */
  895 #define AR5K_AR5212_XRMODE                      0x80c0
  896 #define AR5K_AR5212_XRMODE_POLL_TYPE_M          0x0000003f
  897 #define AR5K_AR5212_XRMODE_POLL_TYPE_S          0
  898 #define AR5K_AR5212_XRMODE_POLL_SUBTYPE_M       0x0000003c
  899 #define AR5K_AR5212_XRMODE_POLL_SUBTYPE_S       2
  900 #define AR5K_AR5212_XRMODE_POLL_WAIT_ALL        0x00000080
  901 #define AR5K_AR5212_XRMODE_SIFS_DELAY           0x000fff00
  902 #define AR5K_AR5212_XRMODE_FRAME_HOLD_M         0xfff00000
  903 #define AR5K_AR5212_XRMODE_FRAME_HOLD_S         20
  905 /*
  906  * XR delay register
  907  */
  908 #define AR5K_AR5212_XRDELAY                     0x80c4
  909 #define AR5K_AR5212_XRDELAY_SLOT_DELAY_M        0x0000ffff
  910 #define AR5K_AR5212_XRDELAY_SLOT_DELAY_S        0
  911 #define AR5K_AR5212_XRDELAY_CHIRP_DELAY_M       0xffff0000
  912 #define AR5K_AR5212_XRDELAY_CHIRP_DELAY_S       16
  914 /*
  915  * XR timeout register
  916  */
  917 #define AR5K_AR5212_XRTIMEOUT           0x80c8
  918 #define AR5K_AR5212_XRTIMEOUT_CHIRP_M   0x0000ffff
  919 #define AR5K_AR5212_XRTIMEOUT_CHIRP_S   0
  920 #define AR5K_AR5212_XRTIMEOUT_POLL_M    0xffff0000
  921 #define AR5K_AR5212_XRTIMEOUT_POLL_S    16
  923 /*
  924  * XR chirp register
  925  */
  926 #define AR5K_AR5212_XRCHIRP             0x80cc
  927 #define AR5K_AR5212_XRCHIRP_SEND        0x00000001
  928 #define AR5K_AR5212_XRCHIRP_GAP         0xffff0000
  930 /*
  931  * XR stomp register
  932  */
  933 #define AR5K_AR5212_XRSTOMP             0x80d0
  934 #define AR5K_AR5212_XRSTOMP_TX          0x00000001
  935 #define AR5K_AR5212_XRSTOMP_RX_ABORT    0x00000002
  936 #define AR5K_AR5212_XRSTOMP_RSSI_THRES  0x0000ff00
  938 /*
  939  * First enhanced sleep register
  940  */
  941 #define AR5K_AR5212_SLEEP0              0x80d4
  942 #define AR5K_AR5212_SLEEP0_NEXT_DTIM    0x0007ffff
  943 #define AR5K_AR5212_SLEEP0_NEXT_DTIM_S  0
  944 #define AR5K_AR5212_SLEEP0_ASSUME_DTIM  0x00080000
  945 #define AR5K_AR5212_SLEEP0_ENH_SLEEP_EN 0x00100000
  946 #define AR5K_AR5212_SLEEP0_CABTO        0xff000000
  947 #define AR5K_AR5212_SLEEP0_CABTO_S      24
  949 /*
  950  * Second enhanced sleep register
  951  */
  952 #define AR5K_AR5212_SLEEP1              0x80d8
  953 #define AR5K_AR5212_SLEEP1_NEXT_TIM     0x0007ffff
  954 #define AR5K_AR5212_SLEEP1_NEXT_TIM_S   0
  955 #define AR5K_AR5212_SLEEP1_BEACON_TO    0xff000000
  956 #define AR5K_AR5212_SLEEP1_BEACON_TO_S  24
  958 /*
  959  * Third enhanced sleep register
  960  */
  961 #define AR5K_AR5212_SLEEP2              0x80dc
  962 #define AR5K_AR5212_SLEEP2_TIM_PER      0x0000ffff
  963 #define AR5K_AR5212_SLEEP2_TIM_PER_S    0
  964 #define AR5K_AR5212_SLEEP2_DTIM_PER     0xffff0000
  965 #define AR5K_AR5212_SLEEP2_DTIM_PER_S   16
  967 /*
  968  * BSSID mask registers
  969  */
  970 #define AR5K_AR5212_BSS_IDM0    0x80e0
  971 #define AR5K_AR5212_BSS_IDM1    0x80e4
  973 /*
  974  * TX power control (TPC) register
  975  */
  976 #define AR5K_AR5212_TXPC                0x80e8
  977 #define AR5K_AR5212_TXPC_ACK_M          0x0000003f
  978 #define AR5K_AR5212_TXPC_ACK_S          0
  979 #define AR5K_AR5212_TXPC_CTS_M          0x00003f00
  980 #define AR5K_AR5212_TXPC_CTS_S          8
  981 #define AR5K_AR5212_TXPC_CHIRP_M        0x003f0000
  982 #define AR5K_AR5212_TXPC_CHIRP_S        22
  984 /*
  985  * Profile count registers
  986  */
  987 #define AR5K_AR5212_PROFCNT_TX          0x80ec
  988 #define AR5K_AR5212_PROFCNT_RX          0x80f0
  989 #define AR5K_AR5212_PROFCNT_RXCLR       0x80f4
  990 #define AR5K_AR5212_PROFCNT_CYCLE       0x80f8
  992 /*
  993  * TSF parameter register
  994  */
  995 #define AR5K_AR5212_TSF_PARM            0x8104
  996 #define AR5K_AR5212_TSF_PARM_INC_M      0x000000ff
  997 #define AR5K_AR5212_TSF_PARM_INC_S      0
  999 /*
 1000  * PHY error filter register
 1001  */
 1002 #define AR5K_AR5212_PHY_ERR_FIL         0x810c
 1003 #define AR5K_AR5212_PHY_ERR_FIL_RADAR   0x00000020
 1004 #define AR5K_AR5212_PHY_ERR_FIL_OFDM    0x00020000
 1005 #define AR5K_AR5212_PHY_ERR_FIL_CCK     0x02000000
 1007 /*
 1008  * Rate duration register
 1009  */
 1010 #define AR5K_AR5212_RATE_DUR_0          0x8700
 1011 #define AR5K_AR5212_RATE_DUR(_n)        (AR5K_AR5212_RATE_DUR_0 + ((_n) << 2))
 1013 /*
 1014  * Key table (WEP) register
 1015  */
 1016 #define AR5K_AR5212_KEYTABLE_0          0x8800
 1017 #define AR5K_AR5212_KEYTABLE(_n)        (AR5K_AR5212_KEYTABLE_0 + ((_n) << 5))
 1018 #define AR5K_AR5212_KEYTABLE_OFF(_n, x) (AR5K_AR5212_KEYTABLE(_n) + (x << 2))
 1019 #define AR5K_AR5212_KEYTABLE_TYPE(_n)   AR5K_AR5212_KEYTABLE_OFF(_n, 5)
 1020 #define AR5K_AR5212_KEYTABLE_TYPE_40    0x00000000
 1021 #define AR5K_AR5212_KEYTABLE_TYPE_104   0x00000001
 1022 #define AR5K_AR5212_KEYTABLE_TYPE_128   0x00000003
 1023 #define AR5K_AR5212_KEYTABLE_TYPE_TKIP  0x00000004
 1024 #define AR5K_AR5212_KEYTABLE_TYPE_AES   0x00000005
 1025 #define AR5K_AR5212_KEYTABLE_TYPE_CCM   0x00000006
 1026 #define AR5K_AR5212_KEYTABLE_TYPE_NULL  0x00000007
 1027 #define AR5K_AR5212_KEYTABLE_ANTENNA    0x00000008
 1028 #define AR5K_AR5212_KEYTABLE_MAC0(_n)   AR5K_AR5212_KEYTABLE_OFF(_n, 6)
 1029 #define AR5K_AR5212_KEYTABLE_MAC1(_n)   AR5K_AR5212_KEYTABLE_OFF(_n, 7)
 1030 #define AR5K_AR5212_KEYTABLE_VALID      0x00008000
 1032 #define AR5K_AR5212_KEYTABLE_SIZE       128
 1033 #define AR5K_AR5212_KEYCACHE_SIZE       8
 1035 /*
 1036  * PHY register
 1037  */
 1038 #define AR5K_AR5212_PHY(_n)             (0x9800 + ((_n) << 2))
 1039 #define AR5K_AR5212_PHY_SHIFT_2GHZ      0x00004007
 1040 #define AR5K_AR5212_PHY_SHIFT_5GHZ      0x00000007
 1042 /*
 1043  * PHY turbo mode register
 1044  */
 1045 #define AR5K_AR5212_PHY_TURBO           0x9804
 1046 #define AR5K_AR5212_PHY_TURBO_MODE      0x00000001
 1047 #define AR5K_AR5212_PHY_TURBO_SHORT     0x00000002
 1049 /*
 1050  * PHY agility command register
 1051  */
 1052 #define AR5K_AR5212_PHY_AGC             0x9808
 1053 #define AR5K_AR5212_PHY_AGC_DISABLE     0x08000000
 1055 /*
 1056  * PHY timing register
 1057  */
 1058 #define AR5K_AR5212_PHY_TIMING_3                0x9814
 1059 #define AR5K_AR5212_PHY_TIMING_3_DSC_MAN        0xfffe0000
 1060 #define AR5K_AR5212_PHY_TIMING_3_DSC_MAN_S      17
 1061 #define AR5K_AR5212_PHY_TIMING_3_DSC_EXP        0x0001e000
 1062 #define AR5K_AR5212_PHY_TIMING_3_DSC_EXP_S      13
 1064 /*
 1065  * PHY chip revision register
 1066  */
 1067 #define AR5K_AR5212_PHY_CHIP_ID         0x9818
 1069 /*
 1070  * PHY activation register
 1071  */
 1072 #define AR5K_AR5212_PHY_ACTIVE          0x981c
 1073 #define AR5K_AR5212_PHY_ENABLE          0x00000001
 1074 #define AR5K_AR5212_PHY_DISABLE         0x00000002
 1076 /*
 1077  * PHY agility control register
 1078  */
 1079 #define AR5K_AR5212_PHY_AGCCTL          0x9860
 1080 #define AR5K_AR5212_PHY_AGCCTL_CAL      0x00000001
 1081 #define AR5K_AR5212_PHY_AGCCTL_NF       0x00000002
 1083 /*
 1084  * PHY noise floor status register
 1085  */
 1086 #define AR5K_AR5212_PHY_NF              0x9864
 1087 #define AR5K_AR5212_PHY_NF_M            0x000001ff
 1088 #define AR5K_AR5212_PHY_NF_ACTIVE       0x00000100
 1089 #define AR5K_AR5212_PHY_NF_RVAL(_n)     (((_n) >> 19) & AR5K_AR5212_PHY_NF_M)
 1090 #define AR5K_AR5212_PHY_NF_AVAL(_n)     (-((_n) ^ AR5K_AR5212_PHY_NF_M) + 1)
 1091 #define AR5K_AR5212_PHY_NF_SVAL(_n)     (((_n) & AR5K_AR5212_PHY_NF_M) | (1 << 9))
 1093 /*
 1094  * PHY sleep registers
 1095  */
 1096 #define AR5K_AR5212_PHY_SCR             0x9870
 1097 #define AR5K_AR5212_PHY_SCR_32MHZ       0x0000001f
 1098 #define AR5K_AR5212_PHY_SLMT            0x9874
 1099 #define AR5K_AR5212_PHY_SLMT_32MHZ      0x0000007f
 1100 #define AR5K_AR5212_PHY_SCAL            0x9878
 1101 #define AR5K_AR5212_PHY_SCAL_32MHZ      0x0000000e
 1103 /*
 1104  * PHY PLL control register
 1105  */
 1106 #define AR5K_AR5212_PHY_PLL             0x987c
 1107 #define AR5K_AR5212_PHY_PLL_40MHZ       0x000000aa
 1108 #define AR5K_AR5212_PHY_PLL_44MHZ       0x000000ab
 1109 #define AR5K_AR5212_PHY_PLL_AR5111      0x00000000
 1110 #define AR5K_AR5212_PHY_PLL_AR5112      0x00000040
 1112 /*
 1113  * PHY receiver delay register
 1114  */
 1115 #define AR5K_AR5212_PHY_RX_DELAY        0x9914
 1116 #define AR5K_AR5212_PHY_RX_DELAY_M      0x00003fff
 1118 /*
 1119  * PHY timing IQ control register
 1120  */
 1121 #define AR5K_AR5212_PHY_IQ                      0x9920
 1122 #define AR5K_AR5212_PHY_IQ_CORR_Q_Q_COFF        0x0000001f
 1123 #define AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF        0x000007e0
 1124 #define AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF_S      5
 1125 #define AR5K_AR5212_PHY_IQ_CORR_ENABLE          0x00000800
 1126 #define AR5K_AR5212_PHY_IQ_CAL_NUM_LOG_MAX      0x0000f000
 1127 #define AR5K_AR5212_PHY_IQ_CAL_NUM_LOG_MAX_S    12
 1128 #define AR5K_AR5212_PHY_IQ_RUN                  0x00010000
 1130 /*
 1131  * PHY PAPD probe register
 1132  */
 1133 #define AR5K_AR5212_PHY_PAPD_PROBE              0x9930
 1134 #define AR5K_AR5212_PHY_PAPD_PROBE_TXPOWER      0x00007e00
 1135 #define AR5K_AR5212_PHY_PAPD_PROBE_TXPOWER_S    9
 1136 #define AR5K_AR5212_PHY_PAPD_PROBE_TX_NEXT      0x00008000
 1137 #define AR5K_AR5212_PHY_PAPD_PROBE_TYPE         0x01800000
 1138 #define AR5K_AR5212_PHY_PAPD_PROBE_TYPE_S       23
 1139 #define AR5K_AR5212_PHY_PAPD_PROBE_TYPE_OFDM    0
 1140 #define AR5K_AR5212_PHY_PAPD_PROBE_TYPE_XR      1
 1141 #define AR5K_AR5212_PHY_PAPD_PROBE_TYPE_CCK     2
 1142 #define AR5K_AR5212_PHY_PAPD_PROBE_GAINF        0xfe000000
 1143 #define AR5K_AR5212_PHY_PAPD_PROBE_GAINF_S      25
 1145 /*
 1146  * PHY TX power registers
 1147  */
 1148 #define AR5K_AR5212_PHY_TXPOWER_RATE1                   0x9934
 1149 #define AR5K_AR5212_PHY_TXPOWER_RATE2                   0x9938
 1150 #define AR5K_AR5212_PHY_TXPOWER_RATE_MAX                0x993c
 1151 #define AR5K_AR5212_PHY_TXPOWER_RATE_MAX_TPC_ENABLE     0x00000040
 1152 #define AR5K_AR5212_PHY_TXPOWER_RATE3                   0xa234
 1153 #define AR5K_AR5212_PHY_TXPOWER_RATE4                   0xa238
 1155 /*
 1156  * PHY frame control register
 1157  */
 1158 #define AR5K_AR5212_PHY_FC              0x9944
 1159 #define AR5K_AR5212_PHY_FC_TX_CLIP      0x00000038
 1160 #define AR5K_AR5212_PHY_FC_TX_CLIP_S    3
 1162 /*
 1163  * PHY radar detection enable register
 1164  */
 1165 #define AR5K_AR5212_PHY_RADAR           0x9954
 1166 #define AR5K_AR5212_PHY_RADAR_DISABLE   0x00000000
 1167 #define AR5K_AR5212_PHY_RADAR_ENABLE    0x00000001
 1169 /*
 1170  * PHY antenna switch table registers
 1171  */
 1172 #define AR5K_AR5212_PHY_ANT_SWITCH_TABLE_0      0x9960
 1173 #define AR5K_AR5212_PHY_ANT_SWITCH_TABLE_1      0x9964
 1175 /*
 1176  * PHY clock sleep registers
 1177  */
 1178 #define AR5K_AR5212_PHY_SCLOCK          0x99f0
 1179 #define AR5K_AR5212_PHY_SCLOCK_32MHZ    0x0000000c
 1180 #define AR5K_AR5212_PHY_SDELAY          0x99f4
 1181 #define AR5K_AR5212_PHY_SDELAY_32MHZ    0x000000ff
 1182 #define AR5K_AR5212_PHY_SPENDING        0x99f8
 1183 #define AR5K_AR5212_PHY_SPENDING_AR5111 0x00000018
 1184 #define AR5K_AR5212_PHY_SPENDING_AR5112 0x00000014
 1186 /*
 1187  * PHY timing IQ calibration result register
 1188  */
 1189 #define AR5K_AR5212_PHY_IQRES_CAL_PWR_I 0x9c10
 1190 #define AR5K_AR5212_PHY_IQRES_CAL_PWR_Q 0x9c14
 1191 #define AR5K_AR5212_PHY_IQRES_CAL_CORR  0x9c18
 1193 /*
 1194  * PHY current RSSI register
 1195  */
 1196 #define AR5K_AR5212_PHY_CURRENT_RSSI    0x9c1c
 1198 /*
 1199  * PHY PCDAC TX power register
 1200  */
 1201 #define AR5K_AR5212_PHY_PCDAC_TXPOWER(_n)       (0xa180 + ((_n) << 2))
 1203 /*
 1204  * PHY mode register
 1205  */
 1206 #define AR5K_AR5212_PHY_MODE            0x0a200
 1207 #define AR5K_AR5212_PHY_MODE_MOD        0x00000001
 1208 #define AR5K_AR5212_PHY_MODE_MOD_OFDM   0
 1209 #define AR5K_AR5212_PHY_MODE_MOD_CCK    1
 1210 #define AR5K_AR5212_PHY_MODE_FREQ       0x00000002
 1211 #define AR5K_AR5212_PHY_MODE_FREQ_5GHZ  0
 1212 #define AR5K_AR5212_PHY_MODE_FREQ_2GHZ  2
 1213 #define AR5K_AR5212_PHY_MODE_MOD_DYN    0x00000004
 1214 #define AR5K_AR5212_PHY_MODE_RAD        0x00000008
 1215 #define AR5K_AR5212_PHY_MODE_RAD_AR5111 0
 1216 #define AR5K_AR5212_PHY_MODE_RAD_AR5112 8
 1217 #define AR5K_AR5212_PHY_MODE_XR         0x00000010
 1219 /*
 1220  * PHY CCK transmit control register
 1221  */
 1222 #define AR5K_AR5212_PHY_CCKTXCTL        0xa204
 1223 #define AR5K_AR5212_PHY_CCKTXCTL_WORLD  0x00000000
 1224 #define AR5K_AR5212_PHY_CCKTXCTL_JAPAN  0x00000010
 1226 /*
 1227  * PHY 2GHz gain register
 1228  */
 1229 #define AR5K_AR5212_PHY_GAIN_2GHZ               0xa20c
 1230 #define AR5K_AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX   0x00fc0000
 1231 #define AR5K_AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18
 1233 #endif