AR5K_AR5212_PHY   227 dev/ic/ar5212.c 	hal->ah_phy = AR5K_AR5212_PHY(0);
AR5K_AR5212_PHY   366 dev/ic/ar5212.c 		AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_2GHZ);
AR5K_AR5212_PHY   369 dev/ic/ar5212.c 		AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ);
AR5K_AR5212_PHY   378 dev/ic/ar5212.c 	AR5K_REG_WRITE(AR5K_AR5212_PHY(0x34), 0x00001c16);
AR5K_AR5212_PHY   381 dev/ic/ar5212.c 		AR5K_REG_WRITE(AR5K_AR5212_PHY(0x20), 0x00010000);
AR5K_AR5212_PHY   382 dev/ic/ar5212.c 	srev = (AR5K_REG_READ(AR5K_AR5212_PHY(0x100)) >> 24) & 0xff;
AR5K_AR5212_PHY   387 dev/ic/ar5212.c 	AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ);
AR5K_AR5212_PHY   517 dev/ic/ar5212.c 	AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ);
AR5K_AR5212_PHY   660 dev/ic/ar5212.c 	AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x44),
AR5K_AR5212_PHY   678 dev/ic/ar5212.c 	AR5K_REG_WRITE(AR5K_AR5212_PHY(0x5a),
AR5K_AR5212_PHY   681 dev/ic/ar5212.c 	AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x11),
AR5K_AR5212_PHY   683 dev/ic/ar5212.c 	AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x12),
AR5K_AR5212_PHY   685 dev/ic/ar5212.c 	AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x14),
AR5K_AR5212_PHY   689 dev/ic/ar5212.c 	AR5K_REG_WRITE(AR5K_AR5212_PHY(0x0d),
AR5K_AR5212_PHY   695 dev/ic/ar5212.c 	AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x0a),
AR5K_AR5212_PHY   697 dev/ic/ar5212.c 	AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x19),
AR5K_AR5212_PHY   699 dev/ic/ar5212.c 	AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x49), 4, 0xffffff01);