BMCR_S100         160 dev/mii/dcphy.c 			    sc->mii_inst), BMCR_LOOP|BMCR_S100);
BMCR_S100         218 dev/mii/exphy.c 	PHY_WRITE(sc, MII_BMCR, BMCR_S100|BMCR_AUTOEN|BMCR_FDX);
BMCR_S100         289 dev/mii/icsphy.c 	PHY_WRITE(sc, MII_BMCR, BMCR_S100|BMCR_AUTOEN|BMCR_FDX);
BMCR_S100          71 dev/mii/mii_physubr.c 	{ BMCR_S100,		ANAR_CSMA|ANAR_T4,	0 },
BMCR_S100          73 dev/mii/mii_physubr.c 	{ BMCR_S100,		ANAR_CSMA|ANAR_TX,	0 },
BMCR_S100          75 dev/mii/mii_physubr.c 	{ BMCR_S100|BMCR_FDX,	ANAR_CSMA|ANAR_TX_FD,	0 },
BMCR_S100         424 dev/sbus/be.c  		    BMCR_S100, NULL);
BMCR_S100        1487 dev/sbus/be.c  			bmcr |= BMCR_S100;
BMCR_S100        1489 dev/sbus/be.c  			bmcr &= ~BMCR_S100;
BMCR_S100        1492 dev/sbus/be.c  				bmcr &= ~BMCR_S100;
BMCR_S100        1544 dev/sbus/be.c  				sc->sc_intphy_curspeed = (bmcr & BMCR_S100);
BMCR_S100        1553 dev/sbus/be.c  				    (bmcr & BMCR_S100) ? "100" : "10");
BMCR_S100        1572 dev/sbus/be.c  		bmcr ^= BMCR_S100;
BMCR_S100        1614 dev/sbus/be.c  	switch (bmcr & (BMCR_S100 | BMCR_FDX)) {
BMCR_S100        1615 dev/sbus/be.c  	case (BMCR_S100 | BMCR_FDX):
BMCR_S100        1618 dev/sbus/be.c  	case BMCR_S100: